74AHC1G79GW [NXP]
Single D-type flip-flop; positive-edge trigger; 单一的D- FL型IP- FL操作;正边沿触发
| 型号： | 74AHC1G79GW |
| 厂家： | 
NXP |
| 描述： | Single D-type flip-flop; positive-edge trigger |
| 文件： | 总12页 (文件大小：87K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
INTEGRATED CIRCUITS
DATA SHEET
74AHC1G79; 74AHCT1G79
Single D-type flip-flop;
positive-edge trigger
1999 May 18
Product specification
File under Integrated Circuits, IC06
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
FEATURES
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.
• Symmetrical output impedance
• High noise immunity
TYPICAL
UNIT
SYMBOL
PARAMETER
CONDITIONS
• ESD protection:
AHC1G AHCT1G
HBM EIA/JESD22-A114-A
exceeds 2000 V;
MM EIA/JESD22-A115-A
exceeds 200 V
tPHL/tPLH propagation delay CL = 15 pF;
3.5
3.5
ns
CP to Q
VCC = 5 V
CI
input capacitance
1.5
1.5
16
pF
pF
CPD
power dissipation
capacitance
notes 1 and 2; 15
CL = 50 pF;
• Low power dissipation
• Balanced propagation delays
• Very small 5 pin package
• Output capability: standard.
f = 1 Mhz
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
DESCRIPTION
The 74AHC1G/AHCT1G79 is a
high-speed Si-gate CMOS device.
fo = output frequency in MHz;
CL = output load capacitance in pF;
The 74AHC1G/AHCT1G79 provides
a single positive-edge triggered
D-type flip-flop.
VCC = supply voltage in V.
2. The condition is VI = GND to VCC
.
Information on the data input is
transferred to the Q output on the
LOW-to-HIGH transition of the clock
pulse. The D input must be stable one
set-up time prior to the LOW-to-HIGH
clock transition for predictable
operation.
PINNING
PIN
1
SYMBOL
D
DESCRIPTION
data input
2
CP
clock pulse input
ground (0 V)
3
GND
Q
4
data output
FUNCTION TABLE
5
VCC
DC supply voltage
See note 1.
INPUTS
CP
OUTPUT
D
L
Q + 1
↑
↑
L
L
H
Q
H
X
Note
1. H = HIGH voltage level;
L = LOW voltage level;
↑ = LOW-to-HIGH CP transition;
X = don’t care;
Q + 1 = state after the next
LOW-to-HIGH CP transition.
1999 May 18
2
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
ORDERING AND PACKAGE INFORMATION
PACKAGES
TYPE NUMBER
TEMPERATURE
RANGE
PINS
PACKAGE
MATERIAL
CODE
MARKING
74AHC1G79GW
74AHCT1G79GW
5
5
SC-88A
SC-88A
plastic
plastic
SOT353
SOT353
AP
CP
−40 to +85 °C
page
page
page
D
CP
1
2
3
5
4
V
CC
1
2
D
Q
4
1
2
4
79
Q
GND
MNA441
CP
MNA439
MNA440
Fig.1 Pin configuration.
Fig.2 Logic symbol.
Fig.3 IEC logic symbol.
CP
C
C
C
C
D
TG
C
TG
C
Q
C
C
TG
C
TG
C
MNA442
Fig.4 Logic diagram.
3
1999 May 18
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
RECOMMENDED OPERATING CONDITIONS
74AHC1G
74AHCT1G
SYMBOL
VCC
PARAMETER
CONDITIONS
UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
DC supply voltage
input voltage
2.0
0
5.0
−
5.5
4.5
0
5.0
−
5.5
V
VI
5.5
5.5
V
VO
output voltage
0
−
VCC
+85
0
−
VCC
+85
V
Tamb
operating ambient
temperature range
see DC and AC
characteristics per
device
−40
+25
−40
+25
°C
tr, tf (∆t/∆f) input rise and fall times VCC = 3.3 V ±0.3 V
−
−
−
−
100
20
−
−
−
−
−
ns/V
except for
VCC = 5 V ±0.5 V
20
Schmitt-trigger inputs
LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 134); voltages are referenced to GND (ground = 0 V).
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
MIN.
−0.5
MAX.
+7.0
UNIT
VCC
VI
V
input voltage range
−0.5
−
+7.0
−20
±20
±25
±75
+150
200
V
IIK
DC input diode current
DC output diode current
VI < −0.5
VO < −0.5 or VO > VCC + 0.5 V; note 1
mA
mA
mA
mA
°C
IOK
IO
−
DC output source or sink current −0.5 V < VO < VCC + 0.5 V
DC VCC or GND current
−
ICC
Tstg
PD
−
storage temperature
−65
−
power dissipation per package
temperature range: −40 to +85 °C;
mW
note 2
Notes
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. Above 55 °C the value of PD derates linearly with 2.5 mW/K.
1999 May 18
4
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
MIN. MAX.
UNIT
OTHER
VCC (V)
MIN.
1.5
TYP.
MAX.
VIH
HIGH-level input
voltage
2.0
3.0
5.5
2.0
3.0
5.5
2.0
3.0
4.5
3.0
−
−
−
−
−
−
−
1.5
2.1
3.85
−
−
V
2.1
3.85
−
−
−
−
−
VIL
LOW-level input voltage
0.5
0.9
1.65
−
0.5
0.9
1.65
−
V
V
V
−
−
−
−
VOH
HIGH-level output
voltage; all outputs
VI = VIH or VIL;
IO = −50 µA
1.9
2.9
4.4
2.58
2.0
3.0
4.5
−
1.9
2.9
4.4
2.48
−
−
−
−
HIGH-level output
voltage
VI = VIH or VIL;
IO = −4.0 mA
−
−
VI = VIH or VIL;
4.5
3.94
−
−
3.8
−
IO = −8.0 mA
VOL
LOW-level output
voltage; all outputs
VI = VIH or VIL;
IO = 50 µA
2.0
3.0
4.5
3.0
−
−
−
−
0
0
0
−
0.1
0.1
0.1
0.36
−
−
−
−
0.1
0.1
0.1
0.44
V
V
LOW-level output
voltage
VI = VIH or VIL;
IO = 4 mA
VI = VIH or VIL;
IO = 8 mA
4.5
−
−
0.36
−
0.44
II
input leakage current
VI = VCC or GND 5.5
−
−
−
−
0.1
1.0
−
−
1.0
10
µA
µA
ICC
quiescent supply
current
VI = VCC or GND; 5.5
IO = 0
CI
input capacitance
−
1.5
10
−
10
pF
1999 May 18
5
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
Family 74AHCT1G
Over recommended operating conditions; voltage are referenced to GND (ground = 0 V).
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85 UNIT
OTHER
VCC (V)
4.5 to 5.5 2.0
MIN. TYP. MAX. MIN. MAX.
VIH
VIL
HIGH-level input voltage
LOW-level input voltage
−
−
2.0
−
−
V
V
V
4.5 to 5.5
4.5
−
−
0.8
−
0.8
−
VOH
HIGH-level output
voltage; all outputs
VI = VIH or VIL;
IO = −50 µA
4.4
4.5
4.4
HIGH-level output
voltage
VI = VIH or VIL;
IO = −8.0 mA
4.5
4.5
4.5
3.94
−
−
0
−
−
3.8
−
−
V
V
V
VOL
LOW-level output
voltage; all outputs
VI = VIH or VIL;
IO = 50 µA
0.1
0.36
0.1
0.44
LOW-level output voltage VI = VIH or VIL;
IO = 8 mA
−
−
II
input leakage current
VI = VIH or VIL
5.5
5.5
−
−
−
−
0.1
1.0
−
−
1.0
10
µA
µA
ICC
quiescent supply current VI = VCC or GND;
IO = 0
∆ICC
additional quiescent
supply current per input
pin
VI = 3.4 V
other inputs at
5.5
−
−
−
1.35
10
−
−
1.5
10
mA
pF
VCC or GND; IO = 0
CI
input capacitance
1.5
1999 May 18
6
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
AC CHARACTERISTICS
Type 74AHC1G79
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
Tamb (°C)
SYMBOL
PARAMETER
25
−40 to +85
UNIT
WAVEFORMS
CL
VCC (V)
MIN. TYP. MAX. MIN. MAX.
t
PHL/tPLH propagation delay
CP to Q
see Figs 5 and 6 15 pF 3.0 to 3.6
50 pF 3.0 to 3.6
−
−
−
−
4.9(1) 8.4
6.9(1) 12.0
3.5(2) 5.6
5.1(2) 8.0
1.0
1.0
1.0
1.0
3.0
0
9.8
14.0
7.0
10.0
−
ns
ns
ns
ns
ns
ns
ns
15 pF 4.5 to 5.5
50 pF 4.5 to 5.5
tsu
th
set-up time D to CP
hold time D to CP
4.5 to 5.5 3.0
1.0
−
−
−
4.5 to 5.5 +2.0 −1.0
−
tW
clock pulse width
HIGH or LOW
4.5 to 5.5 3.0
4.5 to 5.5 90
−
−
3.0
−
fmax
maximum clock
pulse frequency
−
90
−
MHz
Notes
1. Typical values at VCC = 3.3 V.
2. Typical values at VCC = 5.0 V.
Type 74AHCT1G79
GND = 0 V; tr = tf ≤ 3.0 ns.
TEST CONDITIONS
WAVEFORMS CL VCC (V)
Tamb (°C)
SYMBOL
PARAMETER
25
MIN. TYP.
−40 to +85 UNIT
MAX. MIN. MAX.
tPHL/tPLH propagation delay
CP to Q
see Figs 5 and 6 15 pF 4.5 to 5.5
50 pF 4.5 to 5.5
−
−
3.5(1)
5.0(1)
1.0
5.0
8.0
−
1.0
1.0
3.0
0
6.0
10.0
−
ns
ns
ns
ns
ns
tsu
th
set-up time D to CP
hold time D to CP
4.5 to 5.5 3.0
4.5 to 5.5 +2.0 −1.0
−
−
tW
clock pulse width
HIGH or LOW
4.5 to 5.5 3.0
−
−
3.0
−
fmax
maximum clock
pulse frequency
4.5 to 5.5 90
−
−
90
−
MHz
Note
1. Typical values at VCC = 5.0 V.
1999 May 18
7
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
AC WAVEFORMS
V
I
D INPUT
GND
V
I
CP INPUT
V
V
M
M
GND
t
t
PLH
PHL
V
OH
V
V
M
Q OUTPUT
M
V
MNA443
OL
VI INPUT
VM
VM
FAMILY
REQUIREMENTS INPUT OUTPUT
AHC1G
GND to VCC 50% VCC 50% VCC
1.5 V 50% VCC
AHCT1G GND to 3.0 V
Fig.5 The clock pulse (CP) to output (Q) propagation delays.
V
handbook, halfpage
CC
V
V
O
I
PULSE
GENERATOR
D.U.T.
C
R
L
T
MNA101
Definitions for test circuit:
CL = load capacitance including jig and probe capacitance (see Chapter “AC characteristics”).
RT = termination resistance should be equal to the output impedance Z0 of the pulse generator.
Fig.6 Load circuitry for switching times.
8
1999 May 18
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
PACKAGE OUTLINE
Plastic surface mounted package; 5 leads
SOT353
D
B
E
A
X
y
H
v
M
A
E
5
4
Q
A
A
1
1
2
3
c
e
1
b
L
p
w
M B
p
e
detail X
0
1
2 mm
scale
DIMENSIONS (mm are the original dimensions)
A
1
(2)
UNIT
A
b
c
D
E
e
e
H
L
Q
v
w
y
p
p
1
E
max
0.30
0.20
1.1
0.8
0.25
0.10
2.2
1.8
1.35
1.15
2.2
2.0
0.45
0.15
0.25
0.15
mm
0.1
1.3
0.65
0.2
0.2
0.1
REFERENCES
JEDEC
EUROPEAN
PROJECTION
OUTLINE
VERSION
ISSUE DATE
IEC
EIAJ
SC-88A
97-02-28
SOT353
1999 May 18
9
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
• Use a double-wave soldering method comprising a
turbulent wave with high upward pressure followed by a
smooth laminar wave.
SOLDERING
Introduction to soldering surface mount packages
This text gives a very brief insight to a complex technology.
A more in-depth account of soldering ICs can be found in
our “Data Handbook IC26; Integrated Circuit Packages”
(document order number 9398 652 90011).
• For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axis is preferred to be parallel to the
transport direction of the printed-circuit board;
There is no soldering method that is ideal for all surface
mount IC packages. Wave soldering is not always suitable
for surface mount ICs, or for printed-circuit boards with
high population densities. In these situations reflow
soldering is often used.
– smaller than 1.27 mm, the footprint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board.
The footprint must incorporate solder thieves at the
downstream end.
• For packages with leads on four sides, the footprint must
be placed at a 45° angle to the transport direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Reflow soldering
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-syringe dispensing before package placement.
During placement and before soldering, the package must
be fixed with a droplet of adhesive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Several methods exist for reflowing; for example,
infrared/convection heating in a conveyor type oven.
Throughput times (preheating, soldering and cooling) vary
between 100 and 200 seconds depending on heating
method.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the
packages should preferable be kept below 230 °C.
Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
Wave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
When using a dedicated tool, all other leads can be
soldered in one operation within 2 to 5 seconds between
270 and 320 °C.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
1999 May 18
10
Philips Semiconductors
Product specification
74AHC1G79;
74AHCT1G79
Single D-type flip-flop; positive-edge trigger
Suitability of surface mount IC packages for wave and reflow soldering methods
SOLDERING METHOD
PACKAGE
WAVE
REFLOW(1)
BGA, SQFP
not suitable
suitable
suitable
suitable
suitable
suitable
HLQFP, HSQFP, HSOP, HTSSOP, SMS not suitable(2)
PLCC(3), SO, SOJ
LQFP, QFP, TQFP
SSOP, TSSOP, VSO
suitable
not recommended(3)(4)
not recommended(5)
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top version).
3. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
DEFINITIONS
Data sheet status
Objective specification
Preliminary specification
Product specification
This data sheet contains target or goal specifications for product development.
This data sheet contains preliminary data; supplementary data may be published later.
This data sheet contains final product specifications.
Limiting values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or
more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation
of the device at these or at any other conditions above those given in the Characteristics sections of the specification
is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information
Where application information is given, it is advisory and does not form part of the specification.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Philips customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such
improper use or sale.
1999 May 18
11
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TAIPEI, Taiwan Tel. +886 2 2134 2886, Fax. +886 2 2134 2874
Ireland: Newstead, Clonskeagh, DUBLIN 14,
Tel. +353 1 7640 000, Fax. +353 1 7640 200
Thailand: PHILIPS ELECTRONICS (THAILAND) Ltd.,
209/2 Sanpavuth-Bangna Road Prakanong, BANGKOK 10260,
Tel. +66 2 745 4090, Fax. +66 2 398 0793
Israel: RAPAC Electronics, 7 Kehilat Saloniki St, PO Box 18053,
TEL AVIV 61180, Tel. +972 3 645 0444, Fax. +972 3 649 1007
Turkey: Yukari Dudullu, Org. San. Blg., 2.Cad. Nr. 28 81260 Umraniye,
ISTANBUL, Tel. +90 216 522 1500, Fax. +90 216 522 1813
Italy: PHILIPS SEMICONDUCTORS, Piazza IV Novembre 3,
20124 MILANO, Tel. +39 02 67 52 2531, Fax. +39 02 67 52 2557
Ukraine: PHILIPS UKRAINE, 4 Patrice Lumumba str., Building B, Floor 7,
252042 KIEV, Tel. +380 44 264 2776, Fax. +380 44 268 0461
Japan: Philips Bldg 13-37, Kohnan 2-chome, Minato-ku,
TOKYO 108-8507, Tel. +81 3 3740 5130, Fax. +81 3 3740 5077
United Kingdom: Philips Semiconductors Ltd., 276 Bath Road, Hayes,
MIDDLESEX UB3 5BX, Tel. +44 181 730 5000, Fax. +44 181 754 8421
Korea: Philips House, 260-199 Itaewon-dong, Yongsan-ku, SEOUL,
Tel. +82 2 709 1412, Fax. +82 2 709 1415
United States: 811 East Arques Avenue, SUNNYVALE, CA 94088-3409,
Tel. +1 800 234 7381, Fax. +1 800 943 0087
Malaysia: No. 76 Jalan Universiti, 46200 PETALING JAYA, SELANGOR,
Tel. +60 3 750 5214, Fax. +60 3 757 4880
Uruguay: see South America
Vietnam: see Singapore
Mexico: 5900 Gateway East, Suite 200, EL PASO, TEXAS 79905,
Tel. +9-5 800 234 7381, Fax +9-5 800 943 0087
Yugoslavia: PHILIPS, Trg N. Pasica 5/v, 11000 BEOGRAD,
Middle East: see Italy
Tel. +381 11 62 5344, Fax.+381 11 63 5777
For all other countries apply to: Philips Semiconductors,
Internet: http://www.semiconductors.philips.com
International Marketing & Sales Communications, Building BE-p, P.O. Box 218,
5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825
© Philips Electronics N.V. 1999
SCA64
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
245002/00/01/pp12
Date of release: 1999 May 18
Document order number: 9397 750 05983
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