74ABT623D,623 [NXP]
74ABT623 - Octal transceiver with dual enable, non-inverting; (3-State) SOP 20-Pin;
| 型号： | 74ABT623D,623 |
| 厂家： | 
NXP |
| 描述： | 74ABT623 - Octal transceiver with dual enable, non-inverting; (3-State) SOP 20-Pin 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总15页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
74ABT623
Octal transceiver with dual enable; non-inverting; 3-state
Rev. 03 — 22 October 2009
Product data sheet
1. General description
The 74ABT623 high performance BiCMOS device combines low static and dynamic
power dissipation with high speed and high output drive.
The 74ABT623 is an octal transceiver featuring non-inverting 3-state bus compatible
outputs in both send and receive directions. This octal bus transceiver is designed for
asynchronous two-way communication between data buses.
The control function implementation allows maximum flexibility in timing. This device
allows data transmission from the A bus to the B bus or from the B bus to the A bus,
depending upon the logic levels at the enable inputs (pins OEAB and OEBA). The enable
inputs can be used to disable the device so that the buses are effectively isolated. The
dual enable function configuration gives this transceiver the capability to store data by
simultaneous enabling of pins OEAB and OEBA. Each output reinforces its input in this
transceiver configuration. Thus, when both control inputs are enabled and all other data
sources to the two sets of the bus lines are at high-impedance OFF-state, both sets of the
bus lines will remain at their last states. The 8-bit codes appearing on the two sets of
buses will be identical.
2. Features
I Octal bidirectional bus interface
I 3-state buffers
I Power-up 3-state
I Output capability: +64 mA and −32 mA
I data inputs are disabled during 3-state mode
I Latch-up protection exceeds 500 mA per JESD78B class II level A
I ESD protection:
N HBM JESD22-A114F exceeds 2000 V
N MM JESD22-A115-A exceeds 200 V
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
3. Ordering information
Table 1.
Type number Package
Temperature range Name
Ordering information
Description
Version
74ABT623D
−40 °C to +85 °C
SO20
plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
74ABT623DB −40 °C to +85 °C
SSOP20
plastic shrink small outline package; 20 leads;
body width 5.3 mm
SOT339-1
74ABT623PW −40 °C to +85 °C
TSSOP20 plastic thin shrink small outline package; 20 leads;
body width 4.4 mm
SOT360-1
4. Functional diagram
19
EN1
1
EN2
1
1
2
18
2
OEAB
2
3
4
5
6
7
8
9
18
A0
A1
A2
A3
A4
A5
A6
A7
B0
B1
B2
B3
B4
B5
B6
B7
3
4
5
6
7
8
9
17
16
15
14
13
12
11
17
16
15
14
13
12
11
OEBA
19
001aaa833
001aaa844
Fig 1. Logic symbol.
Fig 2. IEC logic symbol.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
2 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
OEBA
OEAB
A0
19
1
2
B0
18
A1
A2
A3
A4
A5
A6
A7
3
4
5
6
7
8
9
B1
17
B2
16
B3
15
B4
14
B5
13
B6
12
B7
11
001aaa832
Fig 3. Logic diagram
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
3 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
5. Pinning information
5.1 Pinning
74ABT623
74ABT623
1
2
20
19
18
17
16
15
14
13
12
11
OEAB
A0
V
CC
1
2
20
19
18
17
16
15
14
13
12
11
OEAB
A0
V
CC
OEBA
B0
OEBA
B0
3
A1
3
A1
4
A2
B1
4
A2
B1
5
A3
B2
5
A3
B2
6
A4
B3
6
A4
B3
7
A5
B4
7
A5
B4
8
A6
B5
8
A6
B5
9
A7
B6
9
A7
B6
10
GND
B7
10
GND
B7
001aak828
001aak829
Fig 4. Pin configuration SO20
Fig 5. Pin configuration (T)SSOP20
5.2 Pin description
Table 2.
Symbol
OEAB
A0 to A7
B0 to B7
GND
Pin description
Pin
Description
1
output enable input (active HIGH)
data input or output
data input or output
ground (0 V)
2, 3, 4, 5, 6, 7, 8, 9
18, 17, 16, 15, 14, 13, 12, 11
10
19
20
OEBA
VCC
output enable input (active LOW)
supply voltage
6. Functional description
Table 3.
Function table[1]
Input
Input or output
OEAB
OEBA
An
Bn
L
L
An = Bn
input
Z
input
Bn = An
Z
H
L
H
H
L
H
H
An = Bn
input
input
Bn = An
L
[1] H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
4 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
VCC
VI
Parameter
Conditions
Min
−0.5
−1.2
−0.5
Max
+7.0
+7.0
+5.5
Unit
V
supply voltage
input voltage
output voltage
[1]
[1]
V
VO
output in OFF-state or
HIGH-state
V
IIK
input diode current
output diode current
output current
VI < 0 V
−18
-
mA
mA
mA
°C
IOK
IO
VO < 0 V
−50
-
output in LOW-state
-
128
150
+150
500
[2]
[3]
Tj
junction temperature
storage temperature
total power dissipation
-
Tstg
Ptot
−65
°C
Tamb = −40 °C to +85 °C
-
mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
[3] For SO20 package: Ptot derates linearly with 8 mW/K above 70 °C.
For SSOP20 and TSSOP20 package: Ptot derates linearly with 5.5 mW/K above 60 °C.
8. Recommended operating conditions
Table 5.
Symbol
VCC
Recommended operating conditions
Parameter
Conditions
Min
4.5
0
Typ
Max
5.5
VCC
-
Unit
V
supply voltage
-
-
-
-
-
-
-
-
VI
input voltage
V
VIH
HIGH-level input voltage
LOW-level input voltage
HIGH-level output current
LOW-level output current
input transition rise or fall rate
ambient temperature
2.0
-
V
VIL
0.8
-
V
IOH
−32
-
mA
mA
ns/V
°C
IOL
64
∆t/∆V
Tamb
0
10
in free air
−40
+85
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
5 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
9. Static characteristics
Table 6.
Static characteristics
Symbol Parameter
Conditions
25 °C
−40 °C to +85 °C Unit
Min
Typ Max
−0.9 −1.2
Min
Max
VIK
input clamping voltage VCC = 4.5 V; IIK = −18 mA
-
-
−1.2
V
VOH
HIGH-level output
voltage
VI = VIL or VIH
VCC = 4.5 V; IOH = −3 mA
VCC = 5.0 V; IOH = −3 mA
VCC = 4.5 V; IOH = −32 mA
2.5
3.0
2.0
-
2.9
3.4
2.4
-
-
-
2.5
3.0
2.0
-
-
V
V
V
V
-
-
VOL
II
LOW-level output
voltage
VCC = 4.5 V; IOL = 64 mA;
VI = VIL or VIH
0.42 0.55
0.55
input leakage current VCC = 5.5 V; VI = GND or 5.5 V
OEAB, OEBA
An, Bn
-
-
-
±0.01 ±1.0
±5.0 ±100
±5.0 ±100
-
-
-
±1.0 µA
±100 µA
±100 µA
IOFF
power-off leakage
current
VCC = 0.0 V; VI or VO ≤ 4.5 V
[1]
IO(pu/pd)
power-up/power-down VCC = 2.0 V; VO = 0.5 V;
-
±5.0 ±50
-
±50
µA
output current
VI = GND or VCC; OEAB = GND;
OEBA = VCC
IOZ
OFF-state output
current
VCC = 5.5 V; VI = VIL or VIH
VO = 2.7 V
-
-
-
5.0
−5.0 −50
5.0 50
50
-
-
-
50
−50
50
µA
µA
µA
VO = 0.5 V
ILO
output leakage current HIGH-state; VO = 5.5 V;
CC = 5.5 V; VI = GND or VCC
V
[2]
IO
output current
supply current
VCC = 5.5 V; VO = 2.5 V
VCC = 5.5 V; VI = GND or VCC
outputs HIGH-state
−180 −100 −50
−180
−50
mA
ICC
-
-
-
50
24
50
250
30
-
-
-
250
30
µA
mA
µA
outputs LOW-state
outputs disabled
250
250
[3]
∆ICC
additional supply
current
per input pin; VCC = 5.5 V;
one input pin at 3.4 V, other inputs
at VCC or GND
outputs enabled
outputs disabled
-
-
-
0.5
50
1.5
250
1.5
-
-
-
1.5
250
1.5
mA
mA
mA
one enable input at 3.4 V and other
inputs at VCC or GND; outputs
disabled
0.5
CI
input capacitance
VI = 0 V or VCC
-
-
4
7
-
-
-
-
-
-
pF
pF
CI/O
input/output
capacitance
outputs disabled; VO = 0 V or VCC
[1] This parameter is valid for any VCC between 0 V and 2.1 V, with a transition time of up to 10 ms. From VCC = 2.1 V to VCC = 5 V ± 10 %,
a transition time of up to 100 ms is permitted.
[2] Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
[3] This is the increase in supply current for each input at 3.4 V.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
6 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
10. Dynamic characteristics
Table 7.
Dynamic characteristics
GND = 0 V; for test circuit, see Figure 9.
Symbol Parameter Conditions
25 °C; VCC = 5.0 V −40 °C to +85 °C; Unit
V
CC = 5.0 V ± 0.5 V
Min
Typ Max
Min
Max
tPLH
tPHL
tPZH
tPZL
tPHZ
tPLZ
LOW to HIGH
propagation delay
An to Bn or Bn to An; see Figure 6
An to Bn or Bn to An; see Figure 6
1.0
2.6
2.7
3.4
4.8
3.6
3.1
4.1
4.2
6.5
6.5
6.5
6.5
1.0
4.6
ns
ns
ns
ns
ns
ns
HIGH to LOW
propagation delay
1.0
1.7
1.7
1.7
1.7
1.0
1.7
1.7
1.7
1.7
4.6
7.5
7.5
7.5
7.5
OFF-state to HIGH OEAB, OEBA to An or Bn; see Figure 7
propagation delay and Figure 8
OFF-state to LOW OEAB, OEBA to An or Bn; see Figure 7
propagation delay and Figure 8
HIGH to OFF-state OEAB, OEBA to An or Bn; see Figure 7
propagation delay and Figure 8
LOW to OFF-state OEAB, OEBA to An or Bn; see Figure 7
propagation delay
and Figure 8
11. Waveforms
V
I
An, Bn
input
V
M
GND
t
t
PHL
PLH
V
OH
Bn, An
output
V
M
mna366
V
OL
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 6. Propagation delay input (An, Bn) to output (Bn, An)
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
7 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
V
I
OEAB input
V
M
GND
3.5 V
t
t
PZL
PLZ
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak830
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Enable and disable times for OEAB input.
V
I
OEBA input
V
M
GND
3.5 V
t
t
PZL
PLZ
output
LOW-to-OFF
OFF-to-LOW
V
M
V
X
V
OL
t
t
PZH
PHZ
V
OH
V
Y
output
HIGH-to-OFF
OFF-to-HIGH
V
M
GND
outputs
enabled
outputs
disabled
outputs
enabled
001aak831
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Enable and disable times for OEBA input.
Table 8.
Input
VI
Measurement points
Output
VX
VM
VY
3.0 V
1.5 V
VOL + 0.3 V
VOH − 0.3 V
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
8 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
t
W
V
I
90 %
90 %
negative
pulse
V
V
M
M
10 %
0 V
V
EXT
t
t
t
r
f
V
CC
t
R
L
r
f
V
V
O
I
V
I
G
DUT
90 %
positive
pulse
V
M
V
M
R
T
C
L
R
L
10 %
10 %
0 V
t
W
001aac221
mna616
a. Input pulse definition
b. Test circuit
Test data and VEXT levels are given in Table 9.
CL = Load capacitance including jig and probe capacitance.
Fig 9. Test circuit for measuring switching times
Table 9.
Input
Test data
Load
VEXT
tr, tf
CL
RL
tPHL, tPLH
tPZH, tPHZ
tPZL, tPLZ
≤ 2.5 ns
50 pF
500 Ω
open
open
7.0 V
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
9 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
12. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
y
H
E
v
M
A
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
w
detail X
e
M
b
p
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
max.
(1)
(1)
(1)
UNIT
mm
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
θ
1
2
3
p
E
p
Z
0.3
0.1
2.45
2.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
10.65
10.00
1.1
0.4
1.1
1.0
0.9
0.4
2.65
0.1
0.25
0.01
1.27
0.05
1.4
0.25
0.01
0.25
0.1
8o
0o
0.012 0.096
0.004 0.089
0.019 0.013 0.51
0.014 0.009 0.49
0.30
0.29
0.419
0.394
0.043 0.043
0.016 0.039
0.035
0.016
inches
0.055
0.01 0.004
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT163-1
075E04
MS-013
Fig 10. Package outline SOT163-1.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
10 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm
SOT339-1
D
E
A
X
v
c
H
M
A
y
E
Z
20
11
Q
A
2
A
(A )
3
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(1)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.21
0.05
1.80
1.65
0.38
0.25
0.20
0.09
7.4
7.0
5.4
5.2
7.9
7.6
1.03
0.63
0.9
0.7
0.9
0.5
mm
2
0.65
0.25
1.25
0.2
0.13
0.1
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT339-1
MO-150
Fig 11. Package outline SOT339-1.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
11 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm
SOT360-1
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
θ
L
p
L
1
10
detail X
w
M
b
p
e
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
A
(1)
(2)
(1)
UNIT
A
A
A
b
c
D
E
e
H
L
L
Q
v
w
y
Z
θ
1
2
3
p
E
p
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.1
0.65
0.25
1
0.2
0.13
0.1
Notes
1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.
2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.
REFERENCES
OUTLINE
EUROPEAN
PROJECTION
ISSUE DATE
VERSION
IEC
JEDEC
JEITA
99-12-27
03-02-19
SOT360-1
MO-153
Fig 12. Package outline SOT360-1.
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
12 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
13. Abbreviations
Table 10. Abbreviations
Acronym
BiCMOS
DUT
Description
BIpolar Complementary Metal-Oxide Semiconductor
Device Under Test
ElectroStatic Discharge
Human Body Model
Machine Model
ESD
HBM
MM
14. Revision history
Table 11. Revision history
Document ID
74ABT623_3
Modifications:
Release date
20091022
Data sheet status
Change notice
Supersedes
Product data sheet
-
74ABT623_2
• The format of this data sheet has been redesigned to comply with the new identity
guidelines of NXP Semiconductors.
• Legal texts have been adapted to the new company name where appropriate.
• DIP20 package removed from Section 3 “Ordering information” and Section 12 “Package
outline”.
74ABT623_2
74ABT623_1
19980116
19960925
Product specification
-
-
-
74ABT623_1
-
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
13 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
15. Legal information
15.1 Data sheet status
Document status[1][2]
Product status[3]
Development
Definition
Objective [short] data sheet
This document contains data from the objective specification for product development.
This document contains data from the preliminary specification.
This document contains the product specification.
Preliminary [short] data sheet Qualification
Product [short] data sheet Production
[1]
[2]
[3]
Please consult the most recently issued document before initiating or completing a design.
The term ‘short data sheet’ is explained in section “Definitions”.
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
15.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
15.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from national authorities.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
15.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
16. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
74ABT623_3
© NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 22 October 2009
14 of 15
74ABT623
NXP Semiconductors
Octal transceiver with dual enable; non-inverting; 3-state
17. Contents
1
2
3
4
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information. . . . . . . . . . . . . . . . . . . . . 2
Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5
5.1
5.2
Pinning information. . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6
Functional description . . . . . . . . . . . . . . . . . . . 4
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended operating conditions. . . . . . . . 5
Static characteristics. . . . . . . . . . . . . . . . . . . . . 6
Dynamic characteristics . . . . . . . . . . . . . . . . . . 7
Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10
Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 13
Revision history. . . . . . . . . . . . . . . . . . . . . . . . 13
7
8
9
10
11
12
13
14
15
Legal information. . . . . . . . . . . . . . . . . . . . . . . 14
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 14
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
15.1
15.2
15.3
15.4
16
17
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 22 October 2009
Document identifier: 74ABT623_3
相关型号：
74ABT623DB,118
74ABT623 - Octal transceiver with dual enable, non-inverting; (3-State) SSOP2 20-Pin
NXP
74ABT623PW,118
74ABT623 - Octal transceiver with dual enable, non-inverting; (3-State) TSSOP2 20-Pin
NXP
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