74ABT573DB-T [NXP]
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| 型号： | 74ABT573DB-T |
| 厂家： | 
NXP |
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Philips Semiconductors
Product specification
74ABT573A
Octal D-type transparent latch (3-State)
The 74ABT573A device is an octal transparent latch coupled to
eight 3-State output buffers. The two sections of the device are
controlled independently by Enable (E) and Output Enable (OE)
control gates. The 74ABT573A is functionally identical to the
74ABT373 but has a flow-through pinout configuration to facilitate
PC board layout and allow easy interface with microprocessors.
FEATURES
• 74ABT573A is flow-through pinout version of 74ABT373
• Inputs and outputs on opposite side of package allow easy
interface to microprocessors
• 3-State output buffers
• Common output enable
• Latch-up protection exceeds 500mA per JEDEC Std 17
The data on the D inputs are transferred to the latch outputs when
the Latch Enable (E) input is High. The latch remains transparent to
the data inputs while E is High, and stores the data that is present
one setup time before the High-to-Low enable transition.
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
• Power-up 3-State
• Power-up reset
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the latch operation.
DESCRIPTION
When OE is Low, the latched or transparent data appears at the
outputs. When OE is High, the outputs are in the High-impedance
”OFF” state, which means they will neither drive nor load the bus.
The 74ABT573A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
Dn to Qn
2.8
3.3
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
3
6
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or V
O CC
OUT
CCZ
I
Outputs disabled; V =5.5V
100
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT573A N
DWG NUMBER
SOT146-1
20-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT573A N
74ABT573A D
74ABT573A DB
74ABT573A PW
20-Pin plastic SO
74ABT573A D
SOT163-1
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
74ABT573A DB
74ABT573APW DH
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
SYMBOL
NUMBER
FUNCTION
1
OE
Output enable input (active-Low)
Data inputs
OE
D0
1
2
3
4
5
20
19
18
17
16
V
2, 3, 4, 5,
6, 7, 8, 9
CC
D0-D7
Q0
19, 18, 17,
16, 15, 14,
13, 12
D1
Q1
Q2
Q3
Q4
Q5
Q6
Q7
E
Q0-Q7
Data outputs
D2
D3
11
10
20
E
Enable input (active-High)
Ground (0V)
D4
6
7
15
14
13
12
11
GND
D5
V
CC
Positive supply voltage
D6
8
D7
9
GND
10
SA00185
1
1995 Sep 06
853–1455 15703
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
LOGIC SYMBOL (IEEE/IEC)
LOGIC SYMBOL
1
EN
11
2
3
4
5
6
7
8
9
C1
2
3
4
5
6
7
8
9
19
18
17
16
15
14
13
12
2D
1
D0 D1 D2 D3 D4 D5 D6 D7
11
1
E
OE
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
19 18 17 16 15 14 13 12
SA00187
SA00186
FUNCTION TABLE
INPUTS
INTERNAL
REGISTER
OUTPUTS
Q0 – Q7
OPERATING MODE
OE
E
Dn
L
L
H
H
L
H
L
H
L
H
Enable and read register
L
L
↓
↓
l
h
L
H
L
H
Latch and read register
Hold
L
L
X
NC
NC
H
H
L
H
X
Dn
NC
Dn
Z
Z
Disable outputs
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
NC= No change
X
Z
↓
=
=
=
Don’t care
High impedance “off” state
High-to-Low E transition
LOGIC DIAGRAM
D0
2
D1
D2
D3
D4
D5
D6
D7
3
4
5
6
7
8
9
D
E
D
E
D
E
D
E
D
E
D
E
D
E
D
E
Q
Q
Q
Q
Q
Q
Q
Q
11
E
1
OE
19
Q0
18
Q1
17
Q2
16
Q3
15
Q4
14
Q5
13
Q6
12
Q7
SA00188
2
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
CC
I
IK
–0.5 to +7.0
–18
V
mA
V
DC input diode current
V < 0
I
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
PARAMETER
LIMITS
UNIT
Min
4.5
0
Max
V
DC supply voltage
5.5
V
V
CC
V
Input voltage
V
CC
I
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
SYMBOL
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
Min
Typ
Max
Min
Max
V
Input clamp voltage
V
V
V
V
V
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
IK
CC
CC
CC
CC
CC
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
Power-up output low
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.55
0.55
0.55
0.55
OL
I
IL
V
RST
V
CC
= 5.5V; I = 1mA; V = GND or V
CC
0.13
V
O
I
3
voltage
I
Input leakage current
V
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
CC
CC
I
I
Power-off leakage current
Power-up/down 3-State
= 0.0V; V or V ≤ 4.5V
±100
±100
OFF
O
I
= 2.0V; V = 0.5V; V = Don’t Care;
O
OE
I
/I
±5.0
±50
±50
µA
PU PD
4
output current
V = GND or V
I CC
I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
IH
I
= 5.5V; V = 0.5V; V = V or V
O I IL
OZL
IH
I
= 5.5V; V = 5.5V; V = GND or V
CC
CEX
O
I
1
I
O
Output current
= 5.5V; V = 2.5V
–40
–180
250
30
–40
–180
250
30
O
I
= 5.5V; Outputs High, V = GND or V
100
24
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3-State;
I
100
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0V and 2.1V with a transition time of up to 10msec. For V = 2.1V to V = 5V " 10%, a
CC
CC
CC
transition time of up to 100µsec is permitted.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
t
t
Propagation delay
Dn to Qn
1.5
2.2
2.8
3.3
4.0
4.8
1.5
2.2
4.5
5.3
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
E to Qn
1.2
1.8
2.5
3.0
4.0
4.4
1.2
1.8
4.5
4.7
PLH
PHL
t
t
Output enable time
to High and Low level
4
5
1.2
2.7
3.0
3.8
4.5
5.3
1.2
2.7
5.2
5.7
PZH
PZL
t
t
Output disable time
from High and Low level
4
5
1.5
1.2
2.8
2.2
4.1
3.4
1.5
1.2
4.5
3.8
PHZ
PLZ
4
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to E
1.0
1.0
0.3
0.2
1.0
1.0
s
3
3
1
ns
ns
ns
t (H)
Hold time, High or Low
Dn to E
1.0
1.0
–0.1
–0.2
1.0
1.0
h
t (L)
h
E pulse width
High
t (H)
w
2.0
0.7
2.0
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
V
V
V
E
M
M
M
V
V
OE
Qn
M
t
M
t
(H)
t
w
PZH
PHZ
t
t
PLH
PHL
V
–0.3V
OH
V
M
V
V
M
Qn
M
0V
SA00063
SA00066
Waveform 1. Propagation Delay, Enable to Output, and Enable
Pulse Width
Waveform 4. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
OE
V
V
M
Dn
M
V
V
M
t
M
t
t
t
PLZ
PZL
PLH
PHL
V
Qn
M
V
V
M
Qn
M
V
V
+0.3V
OL
OL
SA00064
SA00332
Waveform 2. Propagation Delay for Data to Outputs
Waveform 5. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
V
V
V
V
M
Dn
M
M
M
t (H)
s
t (L)
s
t (H)
h
t (L)
h
E
V
V
M
M
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00065
Waveform 3. Data Setup and Hold Times
5
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type transparent latch (3-State)
74ABT573A
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
R
L
L
0V
(t
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
6
1995 Sep 06
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