74ABT374A [NXP]
Octal D-type flip-flop; positive-edge trigger 3-State; 八路D型触发器;正边沿触发三态
| 型号： | 74ABT374A |
| 厂家： | 
NXP |
| 描述： | Octal D-type flip-flop; positive-edge trigger 3-State |
| 文件： | 总6页 (文件大小：71K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
FEATURES
• 8-bit positive edge triggered register
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
• 3-State output buffers
• Output capability: +64mA/–32mA
• Latch-up protection exceeds 500mA per Jedec Std 17
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop’s Q output.
• Power-up 3-State
• Power-up reset
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
• Live insertion/extraction permitted
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance “OFF” state, which
means they will neither drive nor load the bus.
QUICK REFERENCE DATA
CONDITIONS
= 25°C; GND = 0V
SYMBOL
PARAMETER
TYPICAL
UNIT
T
amb
t
t
Propagation delay
CP to Qn
3.4
3.8
PLH
PHL
C = 50pF; V = 5V
ns
L
CC
C
Input capacitance
Output capacitance
Total supply current
V = 0V or V
CC
4
7
pF
pF
µA
IN
I
C
Outputs disabled; V = 0V or V
O CC
OUT
CCZ
I
Outputs disabled; V =5.5V
110
CC
ORDERING INFORMATION
PACKAGES
TEMPERATURE RANGE OUTSIDE NORTH AMERICA
NORTH AMERICA
74ABT374A N
DWG NUMBER
SOT146-1
20-Pin Plastic DIP
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
–40°C to +85°C
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374A PW
20-Pin plastic SO
74ABT374A D
SOT163-1
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
74ABT374A DB
74ABT374APW DH
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
SYMBOL
NUMBER
FUNCTION
1
OE
Output enable input (active-Low)
Data inputs
20
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
V
CC
3, 4, 7, 8,
13, 14, 17,
18
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
D0-D7
2, 5, 6, 9,
12, 15, 16,
19
Q0-Q7
Data outputs
11
10
20
CP
Clock pulse input (active rising edge)
Ground (0V)
GND
V
CC
Positive supply voltage
GND 10
11
CP
SA00110
1
1995 Sep 06
853-1448 15704
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
LOGIC SYMBOL
LOGIC SYMBOL (IEEE/IEC)
3
4
7
8
13 14 17 18
1
EN
11
C1
D0 D1 D2 D3 D4 D5 D6 D7
11
1
CP
OE
3
2
5
1D
4
7
8
6
9
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
13
14
12
15
2
5
6
9
12 15 16 19
17
18
16
19
SA00111
SA00112
FUNCTION TABLE
INPUTS
OUTPUTS
Q0 – Q7
INTERNAL
REGISTER
OPERATING MODE
OE
CP
Dn
L
L
↑
↑
↑
↑
↑
l
h
L
L
H
Latch and read register
Hold
H
L
X
NC
NC
Dn
NC
Z
H
H
X
Disable outputs
Dn
Z
H
h
L
l
=
=
=
=
High voltage level
High voltage level one set-up time prior to the Low-to-High clock transition
Low voltage level
Low voltage level one set-up time prior to the Low-to-High clock transition
NC= No change
X
Z
↑
=
=
=
=
Don’t care
High impedance “off” state
Low-to-High clock transition
not a Low-to-High clock transition
↑
LOGIC DIAGRAM
D0
3
D1
D2
D3
D4
13
D5
14
D6
17
D7
18
4
7
8
D
D
D
D
D
D
D
D
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP
Q
CP Q
11
CP
1
OE
2
5
6
9
12
Q4
15
Q5
16
Q6
19
Q7
Q0
Q1
Q2
Q3
SA00113
2
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0
mA
V
OK
3
V
DC output voltage
output in Off or High state
output in Low state
–0.5 to +5.5
128
OUT
OUT
I
DC output current
mA
°C
T
stg
Storage temperature range
–65 to 150
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
MIN
4.5
0
MAX
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Input transition rise or fall rate
2.0
V
IH
V
0.8
–32
64
V
IL
I
mA
mA
ns/V
°C
OH
I
OL
∆t/∆v
0
10
T
amb
Operating free-air temperature range
–40
+85
3
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40°C
to +85°C
amb
PARAMETER
TEST CONDITIONS
T
amb
= +25°C
UNIT
SYMBOL
MIN
TYP
MAX
MIN
MAX
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5V; I = –18mA
–0.9
2.9
–1.2
–1.2
V
V
V
V
V
V
IK
IK
= 4.5V; I = –3mA; V = V or V
2.5
3.0
2.0
2.5
3.0
2.0
OH
I
IL
IH
V
OH
High-level output voltage
= 5.0V; I = –3mA; V = V or V
3.4
OH
I
IL
IH
= 4.5V; I = –32mA; V = V or V
IH
2.4
OH
I
IL
V
OL
Low-level output voltage
= 4.5V; I = 64mA; V = V or V
IH
0.42
0.13
0.55
0.55
0.55
0.55
OL
I
IL
3
V
RST
Power-up output low voltage
= 5.5V; I = 1mA; V = GND or V
O I
CC
I
Input leakage current
V
V
= 5.5V; V = GND or 5.5V
±0.01
±5.0
±1.0
±1.0
µA
µA
I
CC
I
I
Power-off leakage current
= 0.0V; V or V ≤ 4.5V
±100
±100
OFF
CC
O
I
Power-up/down 3-State
output current
V
CC
V
OE
= 0.0V; I = 1mA; V = GND or V
= Don’t Care
;
O
I
CC
I
/I
±5.0
±50
±50
µA
PU PD
I
3-State output High current
3-State output Low current
Output High leakage current
V
V
V
V
V
V
V
= 5.5V; V = 2.7V; V = V or V
IH
5.0
–5.0
5.0
50
–50
50
50
–50
50
µA
µA
µA
mA
µA
mA
OZH
CC
CC
CC
CC
CC
CC
CC
O
I
IL
I
= 5.5V; V = 0.5V; V = V or V
O I IL IH
OZL
CEX
I
= 5.5V; V = 0.5V; V = GND or V
O
I
CC
1
I
O
Output current
= 5.5V; V = 2.5V
–50
–100
110
24
–180
250
30
–50
–180
250
30
O
I
= 5.5V; Outputs High, V = GND or V
CCH
I
CC
I
Quiescent supply current
= 5.5V; Outputs Low, V = GND or V
CCL
I
CC
= 5.5V; Outputs 3–State;
I
110
0.5
250
1.5
250
1.5
µA
CCZ
V = GND or V
I
CC
Additional supply current per
V
CC
= 5.5V; one input at 3.4V,
∆I
mA
CC
2
input pin
other inputs at V or GND
CC
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
AC CHARACTERISTICS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
Max
T
= -40 to
+85 C
= +5.0V ±0.5V
amb
o
T
V
= +25 C
amb
CC
o
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
V
CC
Min
Typ
Min
Max
f
Maximum clock frequency
1
1
200
300
200
ns
ns
MAX
t
t
Propagation delay
CP to Qn
1.7
2.0
3.4
3.8
4.5
4.9
1.7
2.0
5.1
5.2
PLH
PHL
t
t
Output enable time
to High and Low level
3
4
1.2
2.2
3.5
4.3
4.5
5.4
1.2
2.2
5.4
6.2
PZH
PZL
ns
ns
t
t
Output disable time
from High and Low level
3
4
1.8
1.5
3.6
3.0
4.7
4.1
1.8
1.5
5.2
4.3
PHZ
PLZ
4
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
AC SETUP REQUIREMENTS
GND = 0V, t = t = 2.5ns, C = 50pF, R = 500Ω
R
F
L
L
LIMITS
o
o
T
V
= +25 C
T
V
= -40 to +85 C
amb
CC
amb
CC
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0V
= +5.0V ±0.5V
Min
Typ
Min
t (H)
t (L)
s
Setup time, High or Low
Dn to CP
1.5
1.2
0.6
0.3
1.5
1.2
s
2
2
1
ns
ns
ns
t (H)
Hold time, High or Low
Dn to CP
1.0
1.0
–0.3
–0.5
1.0
1.0
h
t (L)
h
t (H)
CP pulse width
High or Low
2.0
2.8
0.8
1.0
2.0
2.8
w
t (L)
w
AC WAVEFORMS
V
M
= 1.5V, V = GND to 3.0V
IN
1/f
MAX
V
V
M
OE
Qn
M
CP
Qn
VM
t
VM
VM
t
t
t
PHZ
PZH
t
(H)
t
(L)
w
w
PHL
PLH
V
–0.3V
OH
V
M
VM
VM
0V
SA00056
SA00066
Waveform 1. Propagation Delay, Clock Input to Output, Clock
Pulse Width, and Maximum Clock Frequency
Waveform 3. 3-State Output Enable Time to High Level and
Output Disable Time from High Level
V
V
V
V
Dn
CP
M
M
M
M
OE
V
V
M
M
t (H)
s
t (H)
h
t (L)
s
t (L)
h
t
t
PLZ
PZL
V
V
V
M
M
M
Qn
V
+0.3V
0V
OL
NOTE: The shaded areas indicate when the input is permitted
to change for predictable output performance.
SA00107
SA00067
Waveform 2. Data Setup and Hold Times
Waveform 4. 3-State Output Enable Time to Low Level and
Output Disable Time from Low Level
5
1995 Sep 06
Philips Semiconductors
Product specification
Octal D-type flip-flop; positive-edge trigger
(3-State)
74ABT374A
TEST CIRCUIT AND WAVEFORM
V
t
W
AMP (V)
90%
CC
90%
7.0V
NEGATIVE
PULSE
V
V
M
M
10%
10%
90%
R
L
0V
(t
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0V
SWITCH POSITION
V
= 1.5V
M
TEST
SWITCH
closed
closed
open
Input Pulse Definition
t
t
PLZ
PZL
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0V
Rep. Rate
1MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500ns 2.5ns 2.5ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00012
6
1995 Sep 06
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