74ABT16841ADGG,112 [NXP]
74ABT16841A - 20-bit bus interface latch (3-State) TSSOP 56-Pin;
| 型号： | 74ABT16841ADGG,112 |
| 厂家： | 
NXP |
| 描述： | 74ABT16841A - 20-bit bus interface latch (3-State) TSSOP 56-Pin 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总12页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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INTEGRATED CIRCUITS
74ABT16841A
20-bit bus interface latch (3-State)
Product data
2004 Feb 02
Replaces data sheet 74ABT16841A/74ABTH16841A of 2002 Dec 17
Philips
Semiconductors
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
FEATURES
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra
data width for wider data/address paths of buses carrying parity.
• High speed parallel latches
• Live insertion/extraction permitted
The 74ABT16841A consists of two sets of ten D-type latches with
3-State outputs. The flip-flops appear transparent to the data when
Latch Enable (nLE) is HIGH. This allows asynchronous operation,
as the output transition follows the data in transition. On the nLE
HIGH-to-LOW transition, the data that meets the set-up and hold
time is latched.
• Extra data width for wide address/data paths or buses carrying
parity
• Power-up 3-State
• Power-up reset
• Ideal where high speed, light loading, or increased fan-in are
Data appears on the bus when the Output Enable (nOE) is LOW.
When nOE is HIGH the output is in the high-impedance state.
required with MOS microprocessors
• Output capability: +64 mA / –32 mA
• Latch-up protection exceeds 500 mA per Jedec Std 17
• ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
QUICK REFERENCE DATA
CONDITIONS
= 25 °C; GND = 0 V
SYMBOL
PARAMETER
TYPICAL UNIT
T
amb
t
t
Propagation delay
nDx to nQx
3.1
2.2
PLH
PHL
C = 50 pF; V = 5 V
ns
L
CC
C
Input capacitance
Output capacitance
V = 0 V or V
CC
4
7
pF
pF
IN
I
C
V = 0 V or V ; 3-State
O CC
OUT
CCZ
I
Outputs disabled; V = 5.5 V
500
10
µA
mA
CC
Quiescent supply current
I
Outputs LOW; V = 5.5 V
CC
CCL
ORDERING INFORMATION
T
amb
= –40 °C to +85 °C
Package
Name
Type number
Description
Version
74ABT16841ADL
SSOP56
TSSOP56
plastic shrink small outline package; 56 leads; body width 7.5 mm
plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT371-1
SOT364-1
74ABT16841ADGG
PIN DESCRIPTION
PIN NUMBER
SYMBOL
FUNCTION
55, 54, 52, 51, 49, 48, 47, 45, 44, 43
42, 41, 40, 38, 37, 36, 34, 33, 31, 30
1D0 – 1D9
2D0 – 2D9
Data inputs
2, 3, 5, 6, 8, 9, 10, 12, 13, 14
15, 16, 17, 19, 20, 21, 23, 24, 26, 27
1Q0 – 1Q9
2Q0 – 2Q9
Data outputs
1, 28
56, 29
1OE, 2OE
1LE, 2LE
GND
Output enable inputs (active-LOW)
Latch enable inputs (active rising edge)
Ground (0 V)
4, 11, 18, 25, 32, 39, 46, 53
7, 22, 35, 50
V
CC
Positive supply voltage
2
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
PIN CONFIGURATION
LOGIC SYMBOL (IEEE/IEC)
56 1LE
55 1D0
54 1D1
53 GND
52 1D2
51 1D3
1OE
1Q0
1Q1
GND
1Q2
1Q3
1
2
3
4
5
6
7
8
9
1
1OE
1LE
2OE
2LE
EN2
C1
56
28
29
EN4
C3
55
54
52
51
49
48
47
45
44
2
1D
2
1D0
1D1
1D2
1D3
1D4
1D5
1D6
1D7
1D8
1Q0
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
3
5
50
V
V
CC
CC
49 1D4
48 1D5
47 1D6
46 GND
45 1D7
44 1D8
43 1D9
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
1Q4
1Q5
6
8
1Q6 10
GND 11
9
10
12
13
1Q7
1Q8
12
13
1Q9 14
2Q0 15
43
42
41
40
38
37
36
34
33
31
30
14
15
16
17
19
20
21
23
24
26
27
1D9
2D0
2D1
2D2
2D3
2D4
2D5
2D6
2D7
2D8
2D9
1Q9
2Q0
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2Q9
3D
4
16
2Q1
2Q2 17
GND 18
2Q3
19
2Q4 20
2Q5 21
22
V
35
34
V
CC
CC
2D6
2Q6 23
2Q7 24
GND 25
2Q8 26
33 2D7
32 GND
31 2D8
SH00081
2Q9 27
2OE 28
30
2D9
FUNCTION TABLE
29 2LE
SA00076
INPUTS
OUTPUTS
OPERATING MODE
nOE nLE
nDx
nQ0 – nQ9
L
L
H
H
L
H
L
H
Transparent
Latched
LOGIC SYMBOL
L
L
↓
↓
l
h
L
H
55
54
52
51
49
48
47
45
44
43
H
L
X
L
X
X
Z
High impedance
Hold
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7 1D8 1D9
NC
56
1
1LE
H
h
= HIGH voltage level
=
1OE
HIGH voltage level one set-up time prior to the HIGH-to-LOW
LE transition
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
L
l
=
=
LOW voltage level
LOW voltage level one set-up time prior to the HIGH-to-LOW
LE transition
2
3
5
6
8
9
10
34
12
33
13
31
14
30
↓
=
HIGH-to-LOW LE transition
42
41
40
38
37
36
NC= No change
X
Z
=
=
Don’t care
High impedance “off” state
2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9
29
28
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
3
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
nD8
nD9
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
D
L
Q
Q
Q
Q
Q
Q
Q
Q
Q
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
nQ8
nQ9
SH00024
1, 2
ABSOLUTE MAXIMUM RATINGS
SYMBOL
PARAMETER
DC supply voltage
CONDITIONS
RATING
UNIT
V
V
CC
I
IK
–0.5 to +7.0
–18
DC input diode current
V < 0 V
I
mA
V
3
V
I
DC input voltage
–1.2 to +7.0
–50
I
DC output diode current
V
O
< 0 V
mA
V
OK
3
V
OUT
DC output voltage
Output in Off or HIGH state
Output in LOW state
–0.5 to +5.5
128
I
DC output current
mA
OUT
Output in HIGH state
–64
T
stg
Storage temperature range
–65 to 150
°C
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.
3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS
SYMBOL
PARAMETER
UNIT
Min
4.5
0
Max
V
CC
DC supply voltage
5.5
V
V
V
I
Input voltage
V
CC
V
HIGH-level input voltage
LOW-level Input voltage
HIGH-level output current
LOW-level output current
Input transition rise or fall rate
2.0
–
–
V
IH
V
0.8
–32
64
V
IL
I
–
mA
mA
ns/V
°C
OH
I
OL
–
∆t/∆v
0
5
T
amb
Operating free-air temperature range
–40
+85
4
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
DC ELECTRICAL CHARACTERISTICS
LIMITS
T
= –40 °C
to +85 °C
amb
T
amb
= +25 °C
SYMBOL
PARAMETER
TEST CONDITIONS
UNIT
Min
–
Typ
–0.9
2.9
Max
–1.2
–
Min
–
Max
–1.2
–
V
Input clamp voltage
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V; I = –18 mA
V
V
IK
IK
= 4.5 V; I = –3 mA; V = V or V
2.5
3.0
2.0
–
2.5
3.0
2.0
–
OH
I
IL
IH
IH
V
OH
HIGH-level output voltage
= 5.0 V; I = –3 mA; V = V or V
3.4
–
–
V
OH
I
IL
= 4.5 V; I = –32 mA; V = V or V
IH
2.4
–
–
V
OH
I
IL
V
OL
LOW-level output voltage
= 4.5 V; I = 64 mA; V = V or V
IH
0.42
0.13
0.55
0.55
±1
0.55
0.55
±1.0
±100
V
OL
I
IL
3
V
RST
Power-up output voltage
= 5.5 V; I = 1 mA; V = GND or V
CC
–
–
V
O
I
I
Input leakage current
= 5.5 V; V = V or GND
–
±0.01
–
µA
µA
I
I
CC
I
Power-off leakage current
= 0.0 V; V or V ≤ 4.5 V
–
±5.0 ±100
–
OFF
O
I
V
V
= 2.1 V; V = 0.5 V; V = GND or V
= Don’t care
;
Power-up/down 3-State
output current
CC
OE
O
I
CC
CC
I
–
±5.0
±50
–
±50
µA
PU/PD
4
I
3-State output High current
3-State output Low current
Output High leakage current
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V; V = 2.7 V; V = V or V
–
–
5.0
–5.0
5.0
–70
0.5
10
10
–10
50
–
–
10
–10
50
µA
µA
OZH
O
I
IL
IH
IH
I
= 5.5 V; V = 0.5 V; V = V or V
O I IL
OZL
I
= 5.5 V; V = 5.5 V; V = GND or V
–
–
µA
CEX
O
I
1
I
O
Output current
= 5.5 V; V = 2.5 V
–50
–
–180
1
–50
–
–180
1
mA
mA
mA
mA
O
I
I
= 5.5 V; Outputs High, V = GND or V
CCH
I
CC
Quiescent supply current
I
= 5.5 V; Outputs Low, V = GND or V
–
19
–
19
CCL
I
CC
= 5.5 V; Outputs 3-State; V = GND or V
–
0.5
1
–
1
CCZ
I
CC
Additional supply current per
input pin
V
CC
V
CC
= 5.5 V; one input at 3.4 V, other inputs at
or GND
∆I
CC
–
0.2
1
–
1
mA
2
NOTES:
1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
2. This is the increase in supply current for each input at 3.4 V.
3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.
4. This parameter is valid for any V between 0 V and 2.1 V with a transition time of up to 10 msec. From V = 2.1 V to V = 5 V ± 10% a
CC
CC
CC
transition time of up to 100 µsec is permitted.
5. Unused pins at V or GND.
CC
AC CHARACTERISTICS
GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= +5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0 V ±0.5 V
CC
MIN
TYP
MAX
MIN
MAX
t
t
Propagation delay
nDx to nQx
1.1
1.5
3.1
2.2
4.1
3.1
1.1
1.5
4.9
3.6
PLH
PHL
2
1
ns
ns
ns
ns
t
t
Propagation delay
nLE to nQx
1.5
1.0
2.5
2.1
3.3
2.8
1.5
1.0
3.7
3.1
PLH
PHL
t
t
Output enable time
to HIGH and LOW level
4
5
1.2
1.2
2.4
2.2
3.2
2.9
1.2
1.2
4.0
3.6
PZH
PZL
t
t
Output disable time
from HIGH and LOW level
4
5
1.8
1.5
3.0
2.5
4.0
3.2
1.8
1.5
4.9
3.7
PHZ
PLZ
5
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
AC SET-UP REQUIREMENTS
GND = 0 V, t = t = 2.5 ns, C = 50 pF, R = 500 Ω
R
F
L
L
LIMITS
T
V
= +25 °C
= +5.0 V
T
= –40 °C to +85 °C
amb
CC
amb
V
SYMBOL
PARAMETER
WAVEFORM
UNIT
= +5.0 V ±0.5 V
CC
Min
Typ
Min
Max
t (H)
t (L)
s
Set-up time, HIGH or LOW
nDx to nLE
2.0
1.0
1.0
0.4
2.0
1.0
–
–
s
3
ns
t (H)
t (L)
h
Hold time, HIGH or LOW
nDx to nLE
2.0
2.0
–0.3
–0.7
2.0
2.0
–
–
h
3
1
ns
ns
t (H)
w
nLE pulse width HIGH
2.9
1.9
2.9
–
AC WAVEFORMS
V
M
= 1.5 V, V = GND to 3.0 V
IN
3.0V or V
whichever
is less
CC
3.0V or V
CC
whichever
is less
nOE
V
V
V
t
nLE
M
M
M
V
V
M
M
0V
0V
t
t
PZH
PHZ
t
(H)
w
t
V
PHL
PLH
OH
V
V
OH
V
Y
V
M
V
V
M
nQx
M
nQx
0V
OL
SH00007
SA00078
Waveform 4. 3-State Output Enable Time to HIGH Level
and Output Disable Time from HIGH Level
Waveform 1. Propagation Delay, Latch Enable Input to Output,
and Enable Pulse Width
3.0V or V
CC
nOE
nQx
whichever
is less
3.0V or V
CC
whichever
is less
V
V
M
M
t
0V
V
V
M
M
nDx INPUT
t
PZL
PLZ
0V
3.0V or V
CC
t
t
PHL
PLH
V
M
V
X
3.0V or V
CC
0V
whichever
is less
V
OL
nQx OUTPUT
V
V
M
M
SH00008
0V
Waveform 5. 3-State Output Enable Time to LOW Level and
Output Disable Time from LOW Level
SA00079
Waveform 2. Propagation Delay for Data to Outputs
3.0V or V
CC
whichever
is less
V
V
V
V
M
nDx
nLE
M
M
M
0V
t (H)
t (L)
s
t
(H)
t (L)
h
s
h
3.0V or V
CC
whichever
is less
V
V
M
M
0V
NOTE: The shaded areas indicate when the input is
permitted to change for predictable output performance.
SA00080
Waveform 3. Data Set-up and Hold Times
6
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
TEST CIRCUIT AND WAVEFORM
t
W
V
AMP (V)
90%
CC
90%
7.0 V
NEGATIVE
PULSE
V
V
M
10%
M
10%
R
L
0 V
(t
V
V
OUT
IN
PULSE
GENERATOR
D.U.T.
t
t
(t
(t
)
t
t
)
THL
F
TLH
R
)
(t )
F
R
R
L
C
TLH
R
THL
T
L
AMP (V)
90%
M
90%
POSITIVE
PULSE
V
V
M
Test Circuit for 3-State Outputs
10%
10%
t
W
0 V
SWITCH POSITION
V
= 1.5 V
M
TEST
SWITCH
Input Pulse Definition
t
closed
PLZ
PZL
t
closed
open
All other
INPUT PULSE REQUIREMENTS
DEFINITIONS
R = Load resistor; see AC CHARACTERISTICS for value.
L
FAMILY
Amplitude
3.0 V
Rep. Rate
1 MHz
t
t
t
F
W
R
C = Load capacitance includes jig and probe capacitance;
L
see AC CHARACTERISTICS for value.
74ABT
500 ns 2.5 ns 2.5 ns
R = Termination resistance should be equal to Z
T
of
OUT
pulse generators.
SA00654
7
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
8
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm
SOT364-1
9
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
REVISION HISTORY
Rev
Date
Description
_3
20040202
Product data (9397 750 12821); 853-1797 ECN 01–A15433 of 27 January 2004.
Replaces data sheet 74ABT_H16841A_2 of 2002 Dec 17 (9397 750 10845).
Modifications:
• Delete all references to 74ABTH16841A (product discontinued).
_2
_1
20021217
19980227
Product data (9397 750 10845); ECN 853-1797 29296 of 12 December 2002.
Supersedes data of 27 February 1998 (9397 750 03506).
Product specification (9397 750 03506). ECN 853-1797 19025 of 27 February 1998.
10
2004 Feb 02
Philips Semiconductors
Product data
20-bit bus interface latch (3-State)
74ABT16841A
Data sheet status
Product
status
Definitions
[1]
Level
Data sheet status
[2] [3]
I
Objective data
Development
This data sheet contains data from the objective specification for product development.
Philips Semiconductors reserves the right to change the specification in any manner without notice.
II
Preliminary data
Product data
Qualification
Production
This data sheet contains data from the preliminary specification. Supplementary data will be published
at a later date. Philips Semiconductors reserves the right to change the specification without notice, in
order to improve the design and supply the best possible product.
III
This data sheet contains data from the product specification. Philips Semiconductors reserves the
right to make changes at any time in order to improve the design, manufacturing and supply. Relevant
changes will be communicated via a Customer Product/Process Change Notification (CPCN).
[1] Please consult the most recently issued data sheet before initiating or completing a design.
[2] The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL
http://www.semiconductors.philips.com.
[3] For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status.
Definitions
Short-form specification — The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see
the relevant data sheet or data handbook.
Limitingvaluesdefinition— Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting
values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given
in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.
Application information — Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no
representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support — These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be
expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree
to fully indemnify Philips Semiconductors for any damages resulting from such application.
Right to make changes — Philips Semiconductors reserves the right to make changes in the products—including circuits, standard cells, and/or software—described
or contained herein in order to improve design and/or performance. When the product is in full production (status ‘Production’), relevant changes will be communicated
viaaCustomerProduct/ProcessChangeNotification(CPCN).PhilipsSemiconductorsassumesnoresponsibilityorliabilityfortheuseofanyoftheseproducts,conveys
nolicenseortitleunderanypatent, copyright, ormaskworkrighttotheseproducts, andmakesnorepresentationsorwarrantiesthattheseproductsarefreefrompatent,
copyright, or mask work right infringement, unless otherwise specified.
Koninklijke Philips Electronics N.V. 2004
Contact information
All rights reserved. Printed in U.S.A.
For additional information please visit
http://www.semiconductors.philips.com.
Fax: +31 40 27 24825
Date of release: 02-04
9397 750 12821
For sales offices addresses send e-mail to:
sales.addresses@www.semiconductors.philips.com.
Document order number:
Philips
Semiconductors
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