M39208-15WNB1T_技术文档

M39208

Single Chip 2 Mbit Flash and 64 Kbit Parallel EEPROM Memory

PRELIMINARY DATA

2.7V to 3.6V SUPPLY VOLTAGE for

PROGRAM, ERASE and READ OPARATIONS

100ns ACCESS TIME

(Flash and EEPROM blocks)

WRITE, PROGRAM and ERASE STATUS BITS

CONCURRENT MODE (Read Flash while

writing to EEPROM)

100,000 ERASE/WRITE CYCLES

10 YEARS DATA RETENTION

LOW POWER CONSUMPTION

– Stand-by mode: 60µA

TSOP32 (NA)

8 x 20 mm

TSOP32 (NB)

8 x 14 mm

– Automatic Stand-by mode

– Deep Power Down mode

64 bytes ONE TIME PROGRAMMABLE

MEMORY

Figure 1. Logic Diagram

STANDARD EPROM/OTP MEMORY

PACKAGE

EXTENDED TEMPERATURE RANGES

DESCRIPTION

V

CC

The M39208 is a memory device combining Flash

and EEPROM into a single chip and using single

supply voltage. The memory is mapped in two

blocks: 2 Mbit of Flash memory and 64 Kbit of

EEPROM memory. Each space is independant for

writing, in concurrent mode the Flash Memory can

be read while the EEPROM is being written.

18

8

A0-A17

DQ0-DQ7

W

EE

EF

G

M39208

Table 1. Signal Names

A0-A17

DQ0-DQ7

EE

Address Inputs

Data Input / Outputs

EEPROM Block Enable

Flash Block Enable

Output Enable

EF

G

V

SS

AI02589

W

Write Enable

V_CC

Supply Voltage

Ground

V_SS

February 1999

1/30

This is preliminary information on a new product now in development or undergoing evaluation. Details are subject to change without notice.

M39208

Table 2. Absolute Maximum Ratings ⁽¹⁾

Symbol

T_A

Parameter

Value

–40 to 85

–50 to 125

–65 to 150

–0.6 to 5

Unit

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

Input or Output Voltages

Supply Voltage

C

°

T_BIAS

T_STG

(2)

V_IO

V

V_CC

–0.6 to 5

V

(2)

V_A9, V_G, V_EF

A9, G, EF Voltage

–0.6 to 13.5

Notes: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings"

may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other

conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum

Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other

relevant quality documents.

2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.

Figure 2. TSOP Pin Connections

of the data can be secured with the help of the

Software Data Protection (SDP).

The M39208 Flash Memory block offers 4 sectors

of 64 Kbytes, each sector may be erased individu-

ally, and programmed Byte-by-Byte. Each sector

can be separately protected and unprotected

against program and erase. Sector erasure may be

suspended, while data is read from other sectors

of the Flash memory block (or EEPROM memory

block), and then resumed.

A11

A9

1

32

G

A10

EF

A8

A13

A14

A17

W

DQ7

DQ6

DQ5

DQ4

DQ3

During a Program or Erase cycle in the Flash

memory block or during a Write in the EEPROM

memory block, the status of the M39208 internal

logic can be read on the Data Outputs DQ7,DQ6,

DQ5 and DQ3.

V

8

9

25

24

CC

EE

M39208

V

SS

A16

A15

A12

A7

DQ2

DQ1

DQ0

A0

PIN DESCRIPTION

Address Inputs (A0-A17). The address inputs for

the memory array are latched during a write opera-

tion. A0-A12 access locations in the EEPROM

memoryblockA0-A17 accesslocationsin the Flash

memory block. The memory block selected is given

by the state on the EE and EF inputs respectively.

A6

A1

A5

A2

A4

16

17

A3

AI02587

When a specific voltage (V_ID) is applied on the A9

address input, additional specific areas can be

accessed: Read the Manufacturer identifier, Read

the Flash block identifier, Read/Write the EEPROM

block identifier, Verify the Flash Sector Protection

Status.

DESCRIPTION (Cont’d)

Data Input/Output (DQ0-DQ7). A write operation

inputs one byte which is latched when EE (or EF)

and Write Enable W are driven active.

An additional 64 bytes of EPROM are One Time

Programmable.

Data read is valid when one Chip Enable (Chip

Enable Flash or Chip Enable EEPROM) and Out-

put Enable are driven active. The output is high

The M39208 EEPROM memory block may be writ-

ten by byte or by page of 64 bytes and the integrity

2/30

M39208

Figure 3. Flash Block Sectors

TOP

BOTTOM

ADDRESS ADDRESS

A17

1

A16

1

0

1

0

3FFFFh

2FFFFh

1FFFFh

0FFFFh

30000h

20000h

10000h

00000h

1

0

64K Bytes Block

0

AI02588

impedance when the chip is deselected (both EE

and EF driven high) or the outputs are disabled (G

driven high).

During Sector Protect and Sector Unprotect opera-

tions, the G input must be forced to V_IDlevel (12V

+ 0.5V) (for Flash memory block only).

Read operations are used to output the contents

from the memory, the Manufacturer identifier, the

Flash Sector protection Status, the Flash block

Identifier, the EEPROM identifier or the OTP row

content.

Memory Block Enable (EE and EF). The Memory

Block Enable (EE or EF) activates the memory

control logic, input buffers, decoders and sense

amplifiers. When the EE input is driven high, the

EEPROM memory block is not selected; when the

EF input is driven high, the Flash memory block is

not selected. Attempts to access both EEPROM

and Flash blocks (EE low and EF low) are forbid-

den. Switching between the two memory block

enables (EE and EF) must not be made on the

same clock cycle, a delay ofgreater than t_EHFLmust

be inserted.

The M39208 is in standby when both EF and EE

are High (when no internal Erase or programming

is running). The power consumption is reduced to

the standby level and the outputs are in the high

impedance state, independent of the Output En-

able G or Write Enable W inputs.

After 150ns of inactivity and when the addresses

are driven at CMOS levels, the chip automatically

enters a pseudo standbymode where consumption

is reduced to the CMOS standby value, while the

outputs continue to drive the bus.

Write Enable (W). Addresses are latched on the

falling edge of W, and Data Inputs are latched on

the rising edge of W.

OPERATIONS

The M39208 memory is addressed through 18

inputs A0-A17 and provides data on eight Data

Inputs/Outputs DQ0-DQ7 with the help of four con-

trol lines: Chip Enable EEPROM (EE), Chip Enable

Flash (EF), Output Enable (E) and Write Enable

(W) inputs.

An operation is defined as the basic decoding of

the logic level applied to the control input pins (EF,

EE, G, W) and the specified voltages applied on

the relevant address pins. These operations are

detailed in Table 3.

Read. Both Chip Enable and Output Enable (that

is EF and G or EE and G) must be low in order to

read the output of the memory.

Read operations are used to output the contents

from the Flash or EEPROM block, the Manufac-

turer identifier, the Flash Sector protection Status,

the Flash block Identifier, the EEPROM identifier or

the OTP row content.

Notes:

– The Chip Enable input mainly provides power

control and should be used for device selection.

The Output Enable input should be used to gate

data onto the output in combination with active

EF or EE input signals.

Output Enable (G). The Output Enable gates the

outputs through the data buffers during a read

operation. The data outputs are in the high imped-

ance state when the Output Enable G is High.

– The data read depends on the previous instruc-

tion entered into the memory (see Table 4).

3/30

M39208

Table 3. Basic Operations

Operation

EF

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

EE

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

G

W

V_IH

V_IL

X

DQ0 - DQ7

Read in Flash Block

Read in EEPROM Block

Write in Flash Block

Write in EEPROM Block

Hi-Z

V_IL

V_IH

X

Read

Write

Output Disable

X

Hi-Z

Standby

X

Hi-Z

Note: X = V_ILor V_IH.

Write. AWrite operation can be used for two goals:

– either write data in the EEPROM memory block

– or enter a sequence of bytes composing an

instruction.

the correct number of bytes are properly received

and the time between two consecutive bytes is

shorter than the time-out value.

The sequencing of any instruction must be followed

exactly, any invalid combination of instruction bytes

or time-out between two consecutive bytes will

reset the device logic into a Read memory state

(when addressing the Flash block) or directly de-

coded as a single operation when addressing the

EEPROM block.

The reader should note that Programming a Flash

byte is an instruction (see Instructions paragraph).

Writing data requires:

– the Chip Enable (either EE or EF) to be Low

– the Write Enable (W) to be Low with Output

Enable (G) High.

The M39208 set of instructions includes:

– Program a byte in the Flash block

– Read a Flash sector protection status

Addresses in Flash block (or EEPROM block) are

latched on the falling edge of W or EF (EE) which-

ever occurs last; the data to be written in Flash

block(EEPROM block) islatchedon the rising edge

of W or EF (EE) whichever occurs first.

– Erase instructions: Flash Sector Erase, Flash

Block Erase, Flash Sector Erase Suspend, Flash

Sector Erase Resume

– EEPROM power down

– Deep power down

Specific Read and Write Operations. Device

specific data is accessed through operations de-

coding the V_IDlevel applied on A9 (V_ID= 12V +

0.5V) and the logic levels applied on address inputs

(A0, A1, A6). These specific operations are:

– Set/Reset the EEPROM software write protec-

tion (SDP)

– OTP row access

– Reset and Return

– Read the Manufacturer identifier

– Read the Device identifier

– Read identifiers: read the manufacturer identi-

fier, Read the Flash block identifier

– Define the Flash Sector protection

– Read the EEPROM identifier

– Write the EEPROM identifier

These instructions are detailed in Table 4.

For efficient decoding of the instruction, the two first

bytes of an instruction are the coded cycles and are

followed by a command byte or a confirmation byte.

The coded cycles consist of writing the data AAh at

address 5555h during the first cycle and data 55h

at address 2AAAh during the second cycle.

Note: The OTP row (64 bytes) is accessed with a

specific software sequence detailed in the para-

graph "Write in OTP row".

Instructions

An instruction is defined as a sequence of specific

Write operations. Each received byte is sequen-

tially decoded (and not executed as standard Write

operations) and the instruction is executed when

In the specific case of the Erase instruction, the

instruction expects confirmation by two additional

coded cycles.

4/30

M39208

Table 4. Instructions ⁽¹⁾

Instruction

EE

EF

Cycle 1

Cycle 2

Cycle 3

Cycle 4

Cycle 5

Cycle 6

Cycle 7

Read

Identifier

with

(A0,A1,A6)

at (0,0,0)

Read Manufacturer

Identifier ⁽²⁾

AAh

55h

90h

1

0

@5555h @2AAAh @5555h

Read

identifier

with

(A0,A1,A6)

at (1,0,0)

Read Flash

Identifier ⁽²⁾

AAh

55h

90h

1

0

1

0

1

0

@5555h @2AAAh @5555h

AAh

55h

90h

Read

byte 1

Read

byte 2

Read

byte N

Read OTP Row

@5555h @2AAAh @5555h

Read

Identifier

with

(A0,A1,A6)

at (0,1,0)

Read Block

AAh

55h

90h

Protection Status ⁽²⁾

@5555h @2AAAh @5555h

AAh

55h

A0h

Data

Program a Flash Byte

1

0

@5555h @2AAAh @5555h @address

30h

Erase one Flash

Block

AAh 55h 80h AAh

@5555h @2AAAh @5555h @5555h @2AAAh

55h

@Sector @Sector

address address⁽³⁾

AAh 55h 80h AAh 55h

@5555h @2AAAh @5555h @5555h @2AAAh @5555h

10h

Erase the Whole Flash

Suspend Block Erase

B0h

@any

address

30h

@any

Resume Block Erase

1

0

address

EEPROM Power

Down

AAh

55h

30h

0

1

0

1

0

1

@5555h @2AAAh @5555h

20h

@5555h

Deep Power Down

SDP Enable

(EEPROM)

AAh

55h

A0h

Write

byte 1

Write

byte 2

Write

byte N

@5555h @2AAAh @5555h

SDP Disable

(EEPROM)

AAh 55h 80h

@5555h @2AAAh @5555h @5555h @2AAAh @5555h

AAh

55h

20h

AAh

55h

B0h

Write

byte 1

Write

byte 2

Write

byte N

Write in OTP Row

@5555h @2AAAh @5555h

Return (from OTP

Read or EEPROM

Power Down)

F0h @

any

address

0

1

0

F0h

@any

Address

AAh

55h

Reset

@5555h @2AAAh

F0h

@any

address

Reset (short

instruction)

Notes: 1. AAh @5555h means Write byte AAh at address 5555h.

2. This instruction can also be performed as a simple Read operation with A9=V_ID(refer to READ chapter).

3. Additional blocks to be erased must be entered within 80µs.

5/30

M39208

Table 5. Device Identifiers

Other

Addresses

Identifier

EF

V_IL

V_IH

EE

V_IH

V_IL

G

W

A0

V_IL

V_IH

X

A1

V_IL

X

A6

V_IL

A9

V_ID

DQ0 - DQ7

20h

Read the

Manufacturer

Identifier

V_IL

V_IH

Don’t Care

Read the Flash

Block Identifier

t.b.d.

Read the

EEPROM Block

Identifier

64 bytes

user

defined

Note: X = Don’t Care.

POWER SUPPLY and CURRENT CONSUMP-

TION

Read data (Flash and EEPROM blocks)

Both Chip Enable EF (or EE) and Output Enable

(G) must be low in order to read the data from the

memory.

EEPROM Power Down. The M39208 can be set

with the EEPROM in power down with the help of

the EEPROM power down instruction (see Table

4). Once the EEPROM power down instruction is

decoded, the EEPROM block cannot be accessed

unless a further Return instruction is decoded.

Read the Manufacturer Identifier

The manufacturer’s identifier can be read with two

methods: a Read operation or a Read instruction.

Read Operation. The manufacturer’sidentifier can

be read with a Read operation with specific logic

levels applied on A0, A1, A6 and the V_IDlevel (V_ID

= 12V + 0.5V) on A9 (see Table 5).

Deep Power Down. The M39208 can be set in the

lowest I_CCconsumption mode with the help of the

Deep Power Down instruction (see Table 4). Once

the instruction is decoded, the device is set in a

sleep mode until a Reset instruction is decoded.

Read Instruction. The manufacturer’s identifier

can also be read with a single instruction composed

of 4 operations: 3 specific Write operations (see

Table 4) and a Read which outputs the Manufac-

turer identifier, the Flash block identifieror the Flash

sector protection status.

Power Up. The M39208 internallogic isreset upon

a power-up condition to Read memory status. Any

Write operation in EEPROM is inhibited during the

first 5 ms following the power-up.

Either EF, EE or W must be tied to V_IHduring

Power-up for the maximum security of the data

contents and to remove the possibility of a byte

being written on the first rising edge of EF, EE or

W. Any write cycle initiation is locked when Vcc is

Read the Flash Block Identifier

The Flash block identifier can be read with two

methods: a Read operation or a Read instruction.

Read Operation. The Flash block identifier (t.b.d.)

can be read with a single Read operation with

specific logic levels applied on A0, A1, A6 and the

V_IDlevel on A9 (see Table 5).

below V_LKO

.

READ

Read operations and instructions can be used to:

Read Instruction. The Flash block identifier can

also be read with an instruction composed of 4

operations: 3 specific Write operations and a Read

(see Table 4).

– read the contents of the Memory Array (Flash

block and EEPROM block)

– read the Memory Array (Flash block and

EEPROM block) status and identifiers.

6/30

M39208

Table 6. Status Bit

EF

EE

DQ7

DQ6

DQ5

DQ4

DQ3

DQ2

DQ1

DQ0

Data

Toggle

Flag

Error

Flag

Erase

Flash

V_IL

V_IH

X

Polling

Time-out

Data

Polling

Toggle

Flag

EEPROM

V_IL

X

Note: X = Not guaranteed value, can be read either ’1’ or ’0’.

Read the EEPROM Block Identifier

true logic value is read on DQ7 (in a Read opera-

tion).

The EEPROM block identifier (64 bytes, user de-

fined) can be read with a single Read operation with

A6 = ’0’ and A9 = V_ID(see Table 5).

Flash memory block specific features:

– Data Polling is effective after the fourth W pulse

(for programming) or after the sixth W pulse (for

Erase). It must be performed at the address

being programmed or at an address within the

Flash sector being erased.

Read the OTP Row

The OTP row is mapped in the EEPROM block

(EE = ’0’, EF = ’1’). Read of the OTP row (64 bytes)

is by an instruction (see Table 4) composed of three

specific Write operations of data bytes at three

specific memory locations (each location in a dif-

ferent page) before reading the OTP row content.

– During an Erase instruction, DQ7 outputs a ’0’.

After completion of the instruction, DQ7 will out-

put the last bit programmed (that is a ’1’ after

erasing).

When accessing the OTP row, only the LSB ad-

dresses (A6 to A0) are decoded where A6 must be

’0’.

– if the byte to be programmed is in a protected

Flash sector, the instruction is ignored.

Each Read of the OTP row has to be followed by

the Return instruction (see Table 4).

– If all the Flash sectors to be erased are pro-

tected, DQ7 will be set to ’0’ for about 100µs, and

then return to the previous addressed byte. No

erasure will be performed.

Read the Flash Sector Protection Status

Reading the Flash sector protection status is by an

instruction similar to the Read Manufacturer iden-

tifier instruction, the only difference being the value

of the logic levels applied on A0, A1, A6, while A16

and A17 define the Flash sector whose protection

has to be verified. Such a read instruction will

output a 01h if the Flash sector is protected and a

00h if the Flash sector is not protected.

– if all sectors are protected, a Bulk Erase instruc-

tion is ignored.

Toggle flag, DQ6. The M39208 also offers another

way for determining when the EEPROM write or

the Flash memory Program instruction is com-

pleted. During the internal Write operation, the DQ6

will toggle from ’0’ to ’1’ and ’1’ to ’0’ on subsequent

attempts to read any byte of the memory, when

either G , EE or EF is low.

The Flash sector protection status can also be

verified with a Read operation (see chapter: Flash

block specific features), with V_IDon A9.

When the internal cycle is completed the toggling

will stop and the data read on DQ0-DQ7 is the

addressed memory byte. The device is now acces-

sible for a new Read or Write operation. The opera-

tion is completed when two successive reads yield

the same output data.

Read the Status Bits

The M39208 provides several Write operation

status flags which may be used to minimize the

application write (or erase or program) time. These

signals are available on the I/O port bits when

programming (or erasing) are in progress.

Flash memory block specific features:

Data Polling flag, DQ7. When Erasing or Pro-

gramming into the Flash block (or when Writing into

the EEPROM block), bit DQ7 outputs the comple-

ment of the bit being entered for Program-

ming/Writing on DQ7. Once the Program

instruction or the Write operation is performed, the

a. the Toggle bit is effective after the fourth W pulse

(for programming) or after the sixth W pulse (for

Erase).

b. If the byte to be programmed belongs to a pro-

tected Flash sector, the instruction is ignored and:

7/30

M39208

Figure 4. EEPROM SDP Enable Flowcharts

SDP

Set

SDP

not Set

WRITE AAh in

Address 5555h

WRITE AAh in

Address 5555h

Page

Write

Instruction

WRITE 55h in

Address 2AAAh

WRITE 55h in

Address 2AAAh

Page

Write

Instruction

WRITE A0h in

Address 5555h

WRITE A0h in

Address 5555h

WRITE

is enabled

SDP is set

WRITE Data to

be Written in

any Address

Write

in Memory

Write Data

+

SDP ENABLE ALGORITHM

SDP Set

after tWC

AI01698B

– if all the Flash sectors selected for erasure

are protected, DQ6 will toggle to ’0’ for about

100µs, and then return to the previous ad-

dressed byte.

±20% unless anadditional Sector Eraseinstruction

is decoded. After this time period or when the

additional Sector Erase instruction is decoded,

DQ3 is set to ’1’.

– if all sectors are protected, the Bulk Erase in-

struction is ignored.

WRITE a BYTE (or a PAGE) in EEPROM

Error flag, DQ5 (Flash block only). This bit is set

to ’1’ when there is a failure during either a Flash

byte programming or a Sector erase or the Bulk

Erase.

It should be noticed that writing in the EEPROM

block is an operation, it is not an instruction (as for

Programming a byte in the Flash block).

Write a Byte in EEPROM Block

In case of error in Flash sector erase or byte

program, the Flash sector in which the error oc-

curred or to which the programmed byte belongs,

must not be used any longer (other Flash sectors

may still be used). The Error bit resets after Reset

instruction.

A write operation is initiated when Chip Enable EE

is Low and Write Enable W is Low with Output

EnableGHigh. Addresses arelatchedon the falling

edge of W, EE whichever occurs last.

Once initiated, the write operation is internally

timed until completion, that is during a time t_W.

During a correct Program or Erase, the Error bit will

set to ’0’.

The status of the write operation can be found by

reading the Data Polling and Toggle bits (as de-

tailed in the READ chapter) or the Ready/Busy

output. This Ready/Busy output is driven low from

the write of the byte being written until the comple-

tion of the internal Write sequence.

Erase Time-out flag, DQ3 (Flash block only).

The Erase Timer bit reflects the time-out period

allowed between two consecutive Sector Erase

instructions. The Erase timer bit is set to ’0’ after a

Sector Erase instruction for a time period of 100µs

8/30

M39208

Table 7. Write the EEPROM Block Identifier

Other

Addresses

EF

EE

G

W

A6

A9

DQ0 - DQ7

64 bytes User Defined

V_IH

V_IL

V_IH

V_IL

V_ID

Don’t Care

Figure 5. SDP disable Flowchart

period (between two consecutive Write operations)

that is smaller than the t_WLWLvalue. If this period of

time exceeds the t_WLWLvalue, the internal program-

ming cycle will start.

WRITE AAh in

Address 5555h

EEPROM Block Software Data Protection

A protection instruction allows the user to inhibit all

write modes to the EEPROM block: the Software

Data Protection (referenced as SDP in the follow-

ing). The SDP feature is useful for protecting the

EEPROM memory from inadvertent write cycles

that may occur during uncontrolled bus conditions.

WRITE 55h in

Address 2AAAh

WRITE 80h in

Address 5555h

Page

Write

Instruction

The M39208 is shipped as standard in the unpro-

tected state meaning that the EEPROM memory

contents can be changed by the user. After the SDP

enable instruction, the device enters the Protect

Mode where no further write operations have any

effect on the EEPROM memory contents.

WRITE AAh in

Address 5555h

WRITE 55h in

Address 2AAAh

The device remains in this mode until a valid SDP

disable instruction is received whereby the device

reverts to the unprotected state.

WRITE 20h in

Address 5555h

To enable the Software Data Protection, the device

has to be written (with a Page Write) with three

specific data bytes at three specific memory loca-

tions (each location in a different page) as shown

in Figure 4. This sequence provides an unlock key

to enable the write action, and, at the same time,

SDP continues to be set. Any further Write in

EEPROM when the SDP is set will use this same

sequence of three specific data bytes at three

specific memory locations followed by the bytes to

write. The first SDP enable sequence can be di-

rectly followed by the bytes to written.

Unprotected State

after

tWC (Write Cycle time)

AI01699B

Write a Page in EEPROM Block

The Page write allows up to 64 bytes within the

same EEPROM page to be consecutively latched

into the memory prior to initiating a programming

cycle. All bytes must be located in a single page

address, that is A6-A12 must be the same for all

bytes. Once initiated, the Page write operation is

internally timed until completion, that is during a

Similarly, to disable the Software Data Protection

the user has to write specific data bytes into six

different locations with a Page Write addressing

different bytes in different pages, as shown in Fig-

ure 5.

time t_WC

.

The Software Data Protection state is non-volatile

and is notchangedby poweron/offsequences. The

SDP enable/disable instructions set/reset an inter-

nal non-volatile bit and therefore will require a write

time t_WC, This Write operation can be monitored

only on the Toggle bit (status bit DQ6).

The status of the write operation can be seen by

reading the Data Polling and Toggle bits (as de-

tailed in the READ chapter).

A Page write is composed of successive Write

instructions which must be sequenced within a time

9/30

M39208

Figure 6. Data Polling Flowchart

Figure 7. Data Toggle Flowchart

START

READ DQ5 & DQ7

at VALID ADDRESS

READ

DQ5 & DQ6

DQ6

NO

=

DQ7

=

DATA

YES

TOGGLE

NO

YES

NO

DQ5

= 1

DQ5

= 1

YES

READ DQ7

READ DQ6

DQ6

NO

TOGGLE

DQ7

=

DATA

YES

=

NO

YES

FAIL

PASS

AI01369

AI01370

Write OTP Row

formed in a similar way: the Flash memory requires

an instruction (see Instruction chapter) for Erasing

and another instruction for Programming one (or

more) byte(s), the EEPROM memory is directly

written with a simple operation (see Operation

chapter).

Program Instuction. During the execution of the

Program instruction, the Flash block memory will

not accept any further instructions.

Writing (only one time) in the OTP row (64 bytes)

is enabled by an instruction. This instruction is

composed of three specific Write operationsof data

bytes at three specific memory locations (each

location in a different page) followed by the the data

to store in the OTP row (refer to Table 4).

When accessing the OTP row, the only LSB ad-

dresses (A6 to A0) are decoded, with A6 = ’0’.

The Flash block memory can be programmed byte-

by-byte. The program instruction is a sequence of

three specific Write operations followed by writing

the address and data byte to be programmed into

the Flash block memory (see Table 4). The M39208

automatically starts and performs the programming

after the fourth write operation.

Write the EEPROM Block Identifier

The EEPROM block identifier can be written with a

single Write operation with specific logic levels

applied on A6 and the V_IDlevel on A9 (see Table

7).

PROGRAM in the Flash BLOCK

It should be noted that writing data into the

EEPROM block and the Flash block is not per-

During programming, the memory status may be

checked by reading the status bits DQ5, DQ6 and

DQ7, as detailed in the following sections.

10/30

M39208

Data Polling. Polling on DQ7 is a method of check-

ing whether a Program or an Erase instruction is in

progress or completed (see Figure 6). When a

Program instruction is in progress, data bit DQ7 is

the complement of the original data bit 7; when

DQ7 is identical to the old data and the Error bit

DQ5 is still ’0’, the instruction is complete. To de-

termine if DQ7 is valid, each poll must store the

original data for comparison, and if they are the

same, it can be considered that the operation was

successful. The Error bit DQ5 is checked to ensure

timing limits have not exceeded.

b. Writing in the EEPROM memory is an operation

triggering an automatic sequencing of byte erase

followed by a byte write. Writing in EEPROM does

not require a specific erase operation before writ-

ing.

Bulk Erase Instruction. The Bulk Erase instruc-

tion uses six write operations followed by Read

operations of the status register bits, as described

in Table 4. If any byte of the Bulk Erase instruction

is wrong, the Bulk Erase instruction aborts and the

device is reset to the Read Flash memory status.

During a Bulk Erase, the memory status may

checked by reading the status bits DQ5, DQ6 and

DQ7, as detailed in the "PROGRAM in the Flash

BLOCK" chapter. The Error bit (DQ5) returns a ’1’

if there has been an Erase Failure (maximum num-

ber of erase cycles have been executed).

When an Erase operation is in progress, DQ7 is

always ’0’, and will be ’1’ when finished, so long as

DQ5= ’0’.

In all cases, when DQ5 is ’1’, DQ7 should be

checked again, in case DQ7 changed simultane-

ously with DQ5. If DQ7 = true data (Program) or

DQ7 = ’1’ (Erase), the operation is successful and

execution should return to the caller. A suggested

second read will provide all true data (Program) or

all FFh (Erase). Otherwise, this should be flagged

as an error, and the device should be Reset.

It is not necessary to program the array with 00h,

the M39208 will automatically do this before eras-

ing to FFh.

During the execution of the Bulk Erase instruction,

the Flash block logic does not accept any instruc-

tion.

Data Toggle. Checking the Toggle bit DQ6 is an

alternative method of checking if Program or Erase

operations are in progress or completed (see Fig-

ure 7). When an operation is in progress, data bit

DQ6 constantly toggles for successive read opera-

tions. When DQ6 no longer toggles and the Error

bit DQ5 is ’0’, the operation is completed. To deter-

mine if DQ6 has toggled, each polling action re-

quires 2 consecutive read operations of the data,

and if the data read is the same, it can be consid-

ered that the operation was successful. The Error

bit DQ5 is checked to ensure timing limits have not

been exceeded. In all cases, when DQ5 is ’1’, DQ6

should be checked again, in case DQ6 has

changed simultaneously with DQ5. If DQ6 has

stopped toggling, the operation is successful and

execution should return to the caller. A suggested

second read will provide all true data (Program) or

all FFh (Erase). Otherwise, this event should be

flagged as an error, and the device should be

Reset.

Sector Erase in Flash Block. The Sector Erase

instruction uses six write operations, as described

in Table 4. Additional Flash Sector Erase confirm

commands and Flash sector addresses can written

subsequently to erase other Flash sectors in par-

allel, without further coded cycles, if the additional

instruction is transmited in a shorter time than the

timeout period to end of period. The input of a new

Sector Erase instruction will restart the time-out

period.

The status of the internal timer can be monitored

through the level of DQ3 (Erase time-out bit), ifDQ3

is ’0’ the Sector Erase instruction has been re-

ceived and the timeout is counting; if DQ3 is ’1’, the

timeout has expired and the M39208 is erasing the

Flash sector(s). Before and during Erase timeout,

any instruction different than Erase suspend and

Erase Resume will abort the instruction and reset

the device to read array mode.

It is not necessary to program the Flash sector with

00h as the M39208 will do this automatically before

erasing (byte = FFh).

ERASE in the Flash BLOCK

It should be noted that:

During a Sector Erase, the memory status may be

checked by reading the status bits DQ5, DQ6 and

DQ7, as detailed in the "Program instruction" chap-

ter. During the execution of the erase instruction,

the Flash block logic accepts only the Reset and

Erase Suspend instructions (erasure of one Flash

sector may be suspended, in order to read data

from another Flash sector, and then resumed).

a. Programming any byte of one Flash sector (or

bulk) requires that the Flash sector (or bulk) has

been previously erased (once for all bytes within

the sector or bulk) with the correct instruction (see

Instructions chapter).

11/30

M39208

Table 8. Flash Sector Protection

EF

EE

G

W

A0

A1

A6

A9

A12

A16

A17

DQ0 - DQ7

V_IL

V_IH

V_ID

V_IL

X

V_ID

X

SA

SA Protection Activation

Verify the protection status:

SA when DQ0= 1, the sector is

protected

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

V_IL

V_ID

X

SA

Notes: X = Don’t care.

SA = Software Address.

Table 9. Flash Unprotection

EF

EE

G

W

A0

A1

A6

A9

A12 A15 A16 A17

DQ0 - DQ7

Activation of Unprotected

Mode

V_ID

V_IH

V_ID

V_IL

X

V_ID

V_IH

X

V_IH

X

Verify the protection status:

SA when 00h, the sector is

unprotected

V_IL

V_IH

V_IL

V_IH

V_IL

V_IH

SA

Notes: X = Don’t care.

SA = Software Address.

Erase Suspend Instruction. When a Flash Sector

Erase operation is in progress, the Erase Suspend

instruction may suspend the operation by writing

B0h at any address (see Table 4). This allows

reading of data from another Flash sector while

erase is in progress. Erase suspend is accepted

only during the Flash Sector Erase instruction exe-

cution and defaults to read array mode. An Erase

Suspend instruction entered during an Erase

timeout will, in addition to suspending the erase,

terminates the timeout.

eration may be resumed by this instruction. The

Erase Resume instruction consists of writing 30h

at any address (see Table 4).

FLASH BLOCK SPECIFIC FEATURES

Flash Sector Protection. Each Flash sector can

be separately protected against Program or Erase.

Flash Sector Protection provides additional data

security, as it disables all program or erase opera-

tions. This mode is activated when both A9 and G

are set to V_ID(12V + 0.5V) and the Flash sector

address is applied on A16 and A17, as shown in

Figure 8 and Table 8.

The Toggle bit DQ6 stops toggling when the

M39208 internal logic is suspended. The Toggle bit

status must be monitored at an address out of the

Flash sector being erased. Toggle bit will stop

toggling between 0.1µs and 15µs after the Erase

Suspend instruction has been written. The M39208

will then automatically be set into Read Flash Block

Memory Array mode.

Flash sector protection is programmed with the

help of a specific sequence of levels applied on EF,

EE, G, A0, A1, A6, A9, A16 and A17; this sequence

includes a verification of the Protection status on

DQ0 as shown in Table 8.

When erase is suspended, Reading from Flash

sectors being erased will output invalid data, a

Read from Flash sector not being erased is valid.

During an Erase Suspend, the Flash memory will

respond only to Erase Resume and Reset instruc-

tions.

Any attempt to program or erase a protected Flash

sector will be ignored by the device.

Remarks:

– The Verify operation is a read with a simulated

worst case conditions. This allows a guarantee

of the retention of the Protection status

A Reset instruction will definitively abort erasure

and can leave invalid data in the Flash sectors

being erased.

– During the application life, the Sector protection

status can be accessed with a regular Read

instruction without applying a "high voltage" V_ID

on A9. This instruction is detailed in Table 4.

Erase Resume Instruction. If an Erase Suspend

instruction was previously executed, the erase op-

12/30

M39208

Figure 8. Sector Protection Flowchart

START

SECTOR ADDRESS

on A16, A17

EE = V

IH

n = 0

G, A9 = V

EF = V

,

ID

IL

Wait 4µs

W = V

IL

Wait 100µs

W = V

IH

G = V

IH

Wait 4µs

READ DQ0 at PROTECTION

ADDRESS: A0, A6 = V , A1 = V and

IL

IH

A16, A17 DEFINING SECTOR

NO

DQ0

= 1

YES

A9 = V

IH

++n

NO

= 25

PASS

YES

A9 = V

IH

FAIL

AI02598

13/30

M39208

Figure 9. Sector Unprotecting Flowchart

START

EE = EF = V

n = 0

IH

A6, A12, A15 = V

IH

G, A9 = V

IH

Wait 4µs

EF, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

EF, G = V

IH

Wait 4µs

READ at UNPROTECTION

ADDRESS: A1, A6 = V , A0 = V and

IH

IL

INCREMENT

SECTOR

A16, A17 DEFINING SECTOR

(see Note 1)

NO

YES

DATA

=

00h

NO

++n

LAST

NO

= 1000

SECT.

YES

FAIL

YES

PASS

AI02597

Note: 1. A6 is kept at V_IHduring unprotection algorithm in order to secure best unprotection verification. During all other protection status

reads, A6 must be kept at V_IL.

14/30

M39208

Table 10. AC Measurement Conditions

Figure 11. Output AC Testing Load Circuit

Input Rise and Fall Times

Input Pulse Voltages

10ns

≤

V

CC

0.45V to 2.4V

0.8V and 2V

1.5V

Input Timing Ref. Voltages

Output Timing Ref. Voltages

I

OL

DEVICE

UNDER

TEST

Figure 10. AC Testing Input Output Waveform

C

= 30pF

L

I

OH

2.4V

1.5V

C

V

includes JIG capacitance

= 1.5V when the DEVICE

L

OUT

0.45V

UNDER TEST is in the

Hi-Z output state.

AI01950

AI02596B

Table 11. Capacitance ⁽¹⁾(T_A= 25 °C, f = 1 MHz )

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

V_IN= 0V

C_OUT

V_OUT= 0V

12

pF

Note: 1. Sampled only, not 100% tested.

Flash Sector Unprotection. Flash sectors can be

unprotected to allow updating of their contents.

Note that the Sector Unprotection unprotects all

sectors (sector 0 up to sector 7).

– During the application life, the Sector protection

status can be accessed with a regular Read

instruction without "high voltage" V_IDon A9. This

instruction is detailed in Table 4.

Reset Instruction. The Reset instruction resets

the device internal logic in a few µs. Reset is an

instruction of either one write operation or three

write operations (refer to Table 4).

Flash Sector Unprotection is activated with a spe-

cific sequence of levels applied on EF, EE, G, A0,

A1, A6, A9, A12 and A15; this sequence includes a

verification of the Protection status on DQ0-DQ7

as shown in Figure 9 and Table 9.

Supply Rails. Normal precautions must be taken

for supply voltage decoupling, each device in a

system should have the V_CCrail decoupled with a

0.1µF capacitor close to the V_CCand V_SSpins. The

printed circuit board trace width should be sufficient

to carry the V_CCprogram and erase currents re-

quired.

This allows a guarantee of the retention of the

Protection status.

Remarks:

– The Verify operation is a read with a simulated

worst case conditions. This allows a guarantee

of the retention of the Protection status

15/30

M39208

Table 12. DC Characteristics

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

Symbol

I_LI

Parameter

Input Leakage Current

Output Leakage Current

Test Condition

0V

Min

Max

Unit

V

IN

V

1

A

≤

±

µ

CC

I_LO

0V

V

OUT

V

≤

CC

≤

µ

EE = V_IH, EF = V_IL, G =

V_IH, f = 6MHz

(1)

I_CC1

Supply Current (Read Flash) TTL

15

mA

Supply Current (Read EEPROM)

TTL

EE = V_IL, EF = V_IH, G =

V_IH, f = 6MHz

I_CC2

I_CC3

I_CC4

I_CC5

I_CC6

15

60

20

2

Supply Current (Standby) CMOS

EF = EE = V_CC0.2V

A

µ

±

Supply Current (Flash Block

Program or Erase)

Byte program, Sector or

Chip Erase in progress

mA

Supply Current (EEPROM Write)

During t_WC

Supply Current in Deep Power

Down Mode

After a Deep Power Down

instruction (see Table 4)

A

µ

V_IL

V_IH

V_OL

V_OH

V_ID

I_ID

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

A9 High Voltage

V_IDCurrent

–0.5

0.8

VCC + 0.3

0.45

V

0.7 V_CC

V

I_OL= 1.8mA

I_OH= –100 A

V_CC–0.4

11.5

µ

12.5

100

A9 = V_ID

A

µ

V_CCMinimum for Write, Erase and

Program

V_LKO

2

2.3

V

Note: 1. When reading the Flash block when an EEPROM byte(s) is under a write cycle, the supply current is I_CC1+ I_CC5

.

GLOSSARY

– the Flash memory requires an instruction (see

Instruction chapter) for Erasing and another in-

struction for Programming one (or more) byte(s)

– the EEPROM memory is directly written with a

simple operation (see Operation chapter).

SDP: Software Data Protection. Used for protect-

ing the EEPROM block against false Write opera-

tions (as in noisy environments).

Block: EEPROM block (64 Kbit) or Flash block (2

Mbit)

Bulk: the whole Flash block (2 Mbit)

Sector: 64 Kbyte of Flash memory

Page: 64 bytes of EEPROM

Write and Program: Writing (into the EEPROM

block) and programming (the Flash block) is not

performed in a similar way:

16/30

M39208

Figure 12. Read Mode AC Waveforms

17/30

M39208

Table 13. Read AC Characteristics

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

M39208

-120

Symbol

Alt

Parameter

Test Condition

Unit

-100

-150

Min Max Min Max Min Max

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL),

G = V_IL

Address Valid to Next

Address Valid

t_AVAV

t_RC

100

120

150

ns

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL),

G = V_IL

Address Valid to

Output Valid

t_AVQV

t_ACC

100

120

150

Chip Enable Low to

Output Transition

(1)

t_ELQX

t_LZ

t_CE

t_OLZ

t_OE

t_OH

t_HZ

t_OH

t_DF

G = V_IL

0

ns

Chip Enable Low to

Output Valid

(2)

t_ELQV

100

40

120

55

150

55

Output Enable Low to

Output Transition

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL)

(1)

t_GLQX

Output Enable Low to

Output Valid

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL)

(2)

t_GLQV

Chip Enable High to

Output Transition

t_EHQX

G = V_IL

Chip Enable High to

Output Hi-Z

(1)

t_EHQZ

30

40

Output Enable High to

Output Transition

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL)

t_GHQX

Output Enable High to

Output Hi-Z

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL)

(1)

t_GHQZ

30

40

(EE, EF) = (V_IL, V_IH) or

(EE, EF) = (V_IH, V_IL),

G = V_IL

Address Transition to

Output Transition

t_AXQX

t_OH

0

ns

EE (EF) Active to EF

(EE)

t_EHFL

t_CED

100

Notes: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t_ELQV- t_GLQVafter the falling edge of EE (or EF) without increasing t_ELQV

.

18/30

M39208

Figure 13. Write AC Waveforms, W Controlled

WRITE CYCLE

VALID

A0-A17

tWLAX

tAVWL

tWHEH

E ⁽¹⁾

tELWL

G

tWHGL

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7

V

CC

tVCHEL

AI02594

Notes: Address are latched on the falling edge of W, Data is latched on the rising edge of W.

E is either EF when EE = V_IHor EE when EF = V_IH.

19/30

M39208

Figure 14. Write AC Waveforms, E Controlled

WRITE CYCLE

VALID

A0-A17

tELAX

tAVEL

tEHWH

W

tWLEL

tEHGL

G

tGHEL

tELEH

(1)

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7

V

CC

tVCHWL

AI02593

Notes: Address are latched on the falling edge of E, Data is latched on the rising edge of E.

E is either EF when EE = V_IHor EE when EF = V_IH.

20/30

M39208

Table 14. Write AC Characteristics, Write Enable Controlled

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

M39208

-120

Symbol

Alt

Parameter

Unit

-100

-150

Min

Max

Min

Max

Min

Max

Address Valid to Next

Address Valid

t_AVAV

t_WC

t_CS

t_WP

t_DS

100

120

0

150

ns

Chip Enable Low to Write

Enable Low

(2)

t_ELWL

0

50

0

65

0

Write Enable Low to Write

Enable High

t_WLWH

t_DVWH

t_WHDX

50

0

Input Valid to Write Enable

High

Write Enable High to Input

Transition

t_DH

t_CH

t_WPH

t_AS

Write Enable High to Chip

Enable High

(2)

t_WHEH

0

Write Enable High to Write

Enable Low

t_WHWL

t_AVWL

t_WLAX

30

0

30

0

35

0

Address Valid to Write

Enable Low

Write Enable Low to Address

Transition

t_AH

50

65

Output Enable High to Write

Enable Low

t_GHWL

0

50

8

0

50

8

0

50

8

t_VCHEL

t_VCS

V_CCHigh to Chip Enable Low

s

µ

Write Enable High to Output

Valid (Program)

(1)

t_WHQV1

s

Write Enable High to Output

Valid (Sector Erase)

(1)

t_WHQV2

0.5

30

80

0.5

30

80

0.5

30

80

sec

µs

Time Out between 2

consecutive Section Erase

t_WHWL0

t_WHGL

Write Enable High to Output

Enable Low

t_OEH

0

ns

Notes: 1. Time is measured to Data Polling or Toggle Bit, t_WHQV= t_WHQ7V+ t_Q7VQV

2. Chip Enable means (EE, EF) = (V_IL, V_IH) or (EE, EF) = (V_IH, V_IL).

21/30

M39208

Table 15. Write AC Characteristics, EE or EF Controlled

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

M39208

-120

Symbol

Alt

Parameter

Unit

-100

-150

Min

Max

Min

Max

Min

Max

Time-out after the Last Byte

Write

t_WLWL

t_WC

t_BLC

150

s

µ

Write Cycle Time (EEPROM)

10

ms

ns

Address Valid to Next Address

Valid

t_AVAV

100

0

120

0

150

0

Write Enable Low to Memory

Block Enable Low

t_WLEL

t_ELEH

t_DVEH

t_EHDX

t_EHWH

t_EHEL

t_AVEL

t_ELAX

t_WS

t_CP

ns

Memory Block Enable Low to

Memory Block Enable High

50

0

50

0

65

0

Input Valid to Memory Block

Enable High

t_DS

Memory Block Enable High to

Input Transition

t_DH

t_WH

t_CPH

t_AS

Memory Block Enable High to

Write Enable High

0

Memory Block Enable High to

Memory Block Enable Low

30

0

30

0

35

0

Address Valid to Memory Block

Enable Low

Memory Block Enable Low to

Address Transition

t_AH

50

65

Output Enable High to Memory

Block Enable Low

t_GHEL

0

50

8

0

50

8

0

50

8

t_VCHWL

t_VCS

V_CCHigh to Write Enable Low

s

µ

Memory Block Enable High to

Output Valid (Program)

(1)

t_EHQV1

Memory Block Enable High to

Output Valid (Sector Erase)

(1)

t_EHQV2

0.5

0

30

0.5

0

30

0.5

0

30

sec

ns

Memory Block Enable High to

Output Enable Low

t_EHGL

t_OEH

Notes: 1. Time is measured to Data Polling or Toggle Bit, t_WHQV= t_WHQ7V+ t_Q7VQV

.

22/30

M39208

Figure 15. Data Polling DQ7 AC Waveforms

23/30

M39208

Table 16. Data Polling and Toggle Bit AC Characteristics ⁽¹⁾

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

M39208

-120

Test

Conditions

Symbol

Parameter

Unit

-100

-150

Min

Max

Min

Max

Min

Max

EF = 0

EE = 1

Write Enable High to DQ7 Valid

(Program, W Controlled)

t_WHQ7V1

t_WHQ7V2

10

s

µ

EF = 0

EE = 1

Write Enable High to DQ7 Valid

(Sector Erase, W Controlled)

1.5

10

30

1.5

30

1.5

10

30

sec

Flash Block Enable High to

DQ7 Valid (Program, EF

Controlled)

EF = 0

EE = 1

t_EHQ7V1

10

s

µ

Flash Block Enable High to

DQ7 Valid (Sector Erase, EF

Controlled)

EF = 0

EE = 1

t_EHQ7V2

1.5

30

40

1.5

30

50

1.5

30

55

sec

ns

EF = 0

EE = 1

Q7 Valid to Output Valid (Data

Polling)

t_Q7VQV

Notes: 1. All other timings are defined in Read AC Characteristics table.

Table 17. Program, Erase Times and Program, Erase Endurance Cycles (Flash Block)

(T_A= 0 to 70°C or –20 to 85°C or –40 to 85°C; V_CC= 2.7 V to 3.6V)

M39208

Parameter

Unit

Min

Typ

8

Max

30

Chip Program (Byte)

Chip Erase (Preprogrammed)

Chip Erase

sec

3

10

1

Sector Erase (Preprogrammed)

Sector Erase

30

2

Byte Program

10

s

µ

Program/Erase Cycles (per Sector)

100,000

cycles

24/30

M39208

Figure 16. Data Toggle DQ6 AC Waveforms

25/30

M39208

Figure 17. EEPROM Page Write Mode AC Waveforms, W Controlled

A0-A12

Addr 0

Addr 1

Addr 2

Addr n

E

G

tWHWL

tWLWL

W

tWLWH

Byte 0

Byte 1

Byte 2

Byte n

DQ0-DQ7

AI00600

26/30

M39208

ORDERING INFORMATION SCHEME

Example:

M39208

-15 W NA

1

T

Speed

Operating Voltage

Package

Temp. Range

Option

-10 100ns

-12 120ns

-15 150ns

W

2.7V to 3.6V

NA TSOP32

8 x 20mm

1

5

6

0 to 70 C

T

Tape & Reel

Packing

°

–20 to 85 C

°

TSOP32

NB

–40 to 85 C

°

8 x 14mm

Devices are shipped from the factory with the memory content set at all "1’s" (FFh).

For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,

please contact the STMicroelectronics Sales Office nearest to you.

27/30

M39208

TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 14mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

14.20

12.50

8.10

-

Typ

Max

0.047

0.006

0.041

0.011

0.008

0.559

0.492

0.319

-

A

A1

A2

B

0.05

0.95

0.17

0.10

13.80

12.30

7.90

-

0.002

0.037

0.007

0.004

0.543

0.484

0.311

-

C

D

D1

E

e

0.50

0.020

L

0.50

0.70

0.020

0.028

0

°

5

°

0

°

5

°

α

N

32

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

28/30

M39208

TSOP32 - 32 lead Plastic Thin Small Outline, 8 x 20mm

mm

Min

inches

Min

Symb

Typ

Max

1.20

0.15

1.05

0.27

0.21

20.20

18.50

8.10

-

Typ

Max

0.047

0.007

0.041

0.011

0.008

0.795

0.728

0.319

-

A

A1

A2

B

0.05

0.95

0.15

0.10

19.80

18.30

7.90

-

0.002

0.037

0.006

0.004

0.780

0.720

0.311

-

C

D

D1

E

e

0.50

0.020

L

0.50

0.70

0.020

0.028

0

°

5

°

0

°

5

°

α

N

32

CP

0.10

0.004

A2

1

N

e

E

B

N/2

D1

D

A

CP

DIE

C

TSOP-a

A1

α

L

Drawing is not to scale.

29/30

M39208

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences

of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted

by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not

authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

STMicroelectronics GROUP OF COMPANIES

Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Mexico - Morocco - The Netherlands -

Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.

http://www.st.com

30/30


型号：	M39208-15WNB1T
厂家：	NUMONYX B.V
描述：	Flash, 256KX8, 150ns, PDSO32, 8 X 14 MM, PLASTIC, TSOP-32 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管内存集成电路
文件：	总30页 (文件大小：218K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M39208-15WNB1T [NUMONYX]

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