M29W160ET70ZA3E_技术文档

M29W160ET

M29W160EB

16 Mbit (2Mb x8 or 1Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

SUPPLY VOLTAGE

Figure 1. Packages

–

V

_CC= 2.7V to 3.6V for Program, Erase

and Read

ACCESS TIMES: 70, 90ns

PROGRAMMING TIME

–

10μs per Byte/Word typical

35 MEMORY BLOCKS

TSOP48 (N)

12 x 20mm

–

1 Boot Block (Top or Bottom Location)

2 Parameter and 32 Main Blocks

PROGRAM/ERASE CONTROLLER

FBGA

–

Embedded Byte/Word Program

algorithms

ERASE SUSPEND and RESUME MODES

TFBGA48 (ZA)

6 x 8mm

–

Read and Program another Block during

Erase Suspend

UNLOCK BYPASS PROGRAM COMMAND

Faster Production/Batch Programming

–

BGA

TEMPORARY BLOCK UNPROTECTION

MODE

COMMON FLASH INTERFACE

FBGA64 (ZS)

11 x 13 mm

–

64 bit Security Code

LOW POWER CONSUMPTION

Standby and Automatic Standby

–

100,000 PROGRAM/ERASE CYCLES per

BLOCK

ELECTRONIC SIGNATURE

–

Manufacturer Code: 0020h

Top Device Code M29W160ET: 22C4h

Bottom Device Code M29W160EB: 2249h

Automotive Grade Parts Available

June 2009

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M29W160ET, M29W160EB

TABLE OF CONTENTS

FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Figure 1. Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 3. TSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. FBGA 64-ball Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Block Addresses (x8). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Figure 7. Block Addresses (x16). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ0-DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Inputs/Outputs (DQ8-DQ14). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Data Input/Output or Address Input (DQ15A-1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Reset/Block Temporary Unprotect (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Ready/Busy Output (RB). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Byte/Word Organization Select (BYTE). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V_CCSupply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

V

_SSGround. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Special Bus Operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Protection and Blocks Unprotection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 2. Bus Operations, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Table 3. Bus Operations, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Read/Reset Command.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Auto Select Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

Unlock Bypass Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Unlock Bypass Program Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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M29W160ET, M29W160EB

Unlock Bypass Reset Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Chip Erase Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Suspend Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Erase Resume Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 4. Commands, 16-bit mode, BYTE = V_IH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 5. Commands, 8-bit mode, BYTE = V_IL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 6. Program/Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 18

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Data Polling Bit (DQ7). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Toggle Bit (DQ6).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Error Bit (DQ5). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Timer Bit (DQ3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Alternative Toggle Bit (DQ2).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 7. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Figure 8. Data Polling Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Figure 9. Data Toggle Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 8. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 9. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 11.AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 10. Device Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Table 11. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 12.Read Mode AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 12. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 13.Write AC Waveforms, Write Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 13. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Figure 14.Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Table 14. Write AC Characteristics, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 15.Reset/Block Temporary Unprotect AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 15. Reset/Block Temporary Unprotect AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 26

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 16.TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline, top view . 27

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 27

Figure 17.TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline, bottom view. . . . . 28

Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data. . . . . . . . 28

Figure 18.FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package outline, bottom view29

Table 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data . . 29

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M29W160ET, M29W160EB

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

Table 19. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

APPENDIX A.BLOCK ADDRESS TABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 20. Top Boot Block Addresses, M29W160ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

Table 21. Bottom Boot Block Addresses, M29W160EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

APPENDIX B.COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 22. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 23. CFI Query Identification String. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 24. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

Table 25. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 26. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

APPENDIX C.BLOCK PROTECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Programmer Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

In-System Technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 28. Programmer Technique Bus Operations, BYTE = V_IHor V_{IL . . . . . . . . . . . . . . . . . . . . . . . . . . . 36}

Figure 19.Programmer Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Figure 20.Programmer Equipment Chip Unprotect Flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Figure 21.In-System Equipment Block Protect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Figure 22.In-System Equipment Chip Unprotect Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table 29. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

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M29W160ET, M29W160EB

SUMMARY DESCRIPTION

The M29W160E is a 16 Mbit (2Mb x8 or 1Mb x16)

non-volatile memory that can be read, erased and

reprogrammed. These operations can be per-

formed using a single low voltage (2.7 to 3.6V)

supply. On power-up the memory defaults to its

Read mode where it can be read in the same way

as a ROM or EPROM.

command set required to control the memory is

consistent with JEDEC standards.

The blocks in the memory are asymmetrically ar-

ranged, see Figures 6 and 7, Block Addresses.

The first or last 64 KBytes have been divided into

four additional blocks. The 16 KByte Boot Block

can be used for small initialization code to start the

microprocessor, the two 8 KByte Parameter

Blocks can be used for parameter storage and the

remaining 32K is a small Main Block where the ap-

plication may be stored.

Chip Enable, Output Enable and Write Enable sig-

nals control the bus operation of the memory.

They allow simple connection to most micropro-

cessors, often without additional logic.

The memory is divided into blocks that can be

erased independently so it is possible to preserve

valid data while old data is erased. Each block can

be protected independently to prevent accidental

Program or Erase commands from modifying the

memory. Program and Erase commands are writ-

ten to the Command Interface of the memory. An

on-chip Program/Erase Controller simplifies the

process of programming or erasing the memory by

taking care of all of the special operations that are

required to update the memory contents.

The memory is offered TSOP48 (12 x 20mm) and

TFBGA48 (0.8mm pitch) packages. The memory

is supplied with all the bits erased (set to ’1’).

The end of a program or erase operation can be

detected and any error conditions identified. The

Figure 2. Logic Diagram

Table 1. Signal Names

A0-A19

DQ0-DQ7

DQ8-DQ14

DQ15A–1

E

Address Inputs

Data Inputs/Outputs

Data Input/Output or Address Input

Chip Enable

V

CC

20

15

A0-A19

DQ0-DQ14

DQ15A–1

W

E

G

Output Enable

M29W160ET

M29W160EB

W

Write Enable

G

RB

RP

Reset/Block Temporary Unprotect

Ready/Busy Output

Byte/Word Organization Select

Supply Voltage

RP

RB

BYTE

V_CC

V

SS

V_SS

Ground

AI06849B

NC

Not Connected Internally

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M29W160ET, M29W160EB

Figure 3. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

BYTE

V

SS

DQ15A–1

DQ7

DQ14

DQ6

A8

DQ13

DQ5

A19

NC

W

DQ12

DQ4

RP

NC

RB

A18

A17

A7

12

13

37

36

V

M29W160ET

M29W160EB

CC

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI06850

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M29W160ET, M29W160EB

Figure 4. TFBGA Connections (Top view through package)

1

2

3

4

5

6

A9

A13

A

B

A3

A4

A7

A17

A6

RB

NC

W

RP

A8

A10

A12

A14

C

D

E

F

A2

A1

A0

E

A18

NC

A11

A5

NC

A19

DQ5

DQ12

A15

DQ2

DQ10

DQ11

DQ3

DQ7

DQ14

DQ13

DQ6

DQ0

DQ8

DQ9

DQ1

A16

BYTE

DQ15

A–1

G

H

G

V

CC

V

DQ4

V

SS

AI02985B

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M29W160ET, M29W160EB

Figure 5. FBGA 64-ball Connections (Top view through package)

7

8

1

2

3

4

5

6

RB

W

RP

NC

A

B

NC

A3

A4

A7

A17

A6

A9

A8

A13

A12

NC

V

/WP

PP

A2

A1

A0

E

A18

NC

A10

A11

DQ7

A14

A15

A16

BYTE

C

D

NC

A5

A19

V

CC

DQ2

NC

DQ5

DQ0

V

SS

E

F

V

NC

DQ8

DQ9

DQ1

DQ10

DQ11

DQ3

DQ12

DQ14

DQ13

DQ6

CC

DQ15

A–1

V

NC

G

NC

CC

G

H

V

NC

DQ4

SS

AI12719_16-Mbit_bis

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M29W160ET, M29W160EB

Figure 6. Block Addresses (x8)

M29W160ET

Top Boot Block Addresses (x8)

M29W160EB

Bottom Boot Block Addresses (x8)

1FFFFFh

16 KByte

1FC000h

1FBFFFh

1FFFFFh

64 KByte

1F0000h

1EFFFFh

8 KByte

1FA000h

1F9FFFh

1E0000h

Total of 31

64 KByte Blocks

8 KByte

1F8000h

1F7FFFh

32 KByte

1F0000h

1EFFFFh

01FFFFh

64 KByte

32 KByte

8 KByte

16 KByte

1E0000h

010000h

00FFFFh

008000h

007FFFh

Total of 31

64 KByte Blocks

006000h

005FFFh

01FFFFh

64 KByte

010000h

00FFFFh

004000h

003FFFh

64 KByte

000000h

AI06851

Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.

9/42

M29W160ET, M29W160EB

Figure 7. Block Addresses (x16)

M29W160ET

M29W160EB

Top Boot Block Addresses (x16)

Bottom Boot Block Addresses (x16)

FFFFFh

8 KWord

FE000h

FDFFFh

FFFFFh

32 KWord

F8000h

F7FFFh

4 KWord

FD000h

FCFFFh

F0000h

Total of 31

32 KWord Blocks

4 KWord

FC000h

FBFFFh

16 KWord

F8000h

F7FFFh

0FFFFh

32 KWord

16 KWord

4 KWord

8 KWord

F0000h

08000h

07FFFh

04000h

03FFFh

Total of 31

32 KWord Blocks

03000h

02FFFh

0FFFFh

32 KWord

08000h

07FFFh

02000h

01FFFh

32 KWord

00000h

AI06852

Note: Also see Appendix A, Tables 20 and 21 for a full listing of the Block Addresses.

10/42

M29W160ET, M29W160EB

SIGNAL DESCRIPTIONS

See Figure 2, Logic Diagram, and Table 1, Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the Program/Erase Con-

troller.

Data Inputs/Outputs (DQ0-DQ7). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation. During Bus

Write operations they represent the commands

sent to the Command Interface of the Program/

Erase Controller.

Read and Bus Write operations after t_PHELor

t

_RHEL, whichever occurs last. See the Ready/Busy

Output section, Table 15 and Figure 15, Reset/

Temporary Unprotect AC Characteristics for more

details.

Holding RP at V_IDwill temporarily unprotect the

protected Blocks in the memory. Program and

Erase operations on all blocks will be possible.

The transition from V_IHto V_IDmust be slower than

t_PHPHH

.

Ready/Busy Output (RB). The Ready/Busy pin

is an open-drain output that can be used to identify

when the device is performing a Program or Erase

operation. During Program or Erase operations

Ready/Busy is Low, V_OL. Ready/Busy is high-im-

pedance during Read mode, Auto Select mode

and Erase Suspend mode.

After a Hardware Reset, Bus Read and Bus Write

operations cannot begin until Ready/Busy be-

comes high-impedance. See Table 15 and Figure

15, Reset/Temporary Unprotect AC Characteris-

tics.

Data Inputs/Outputs (DQ8-DQ14). The Data In-

puts/Outputs output the data stored at the selected

address during a Bus Read operation when BYTE

is High, V_IH. When BYTE is Low, V_IL, these pins

are not used and are high impedance. During Bus

Write operations the Command Register does not

use these bits. When reading the Status Register

these bits should be ignored.

The use of an open-drain output allows the Ready/

Busy pins from several memories to be connected

to a single pull-up resistor. A Low will then indicate

that one, or more, of the memories is busy.

Data Input/Output or Address Input (DQ15A-1).

When BYTE is High, V_IH, this pin behaves as a

Data Input/Output pin (as DQ8-DQ14). When

BYTE is Low, V_IL, this pin behaves as an address

pin; DQ15A–1 Low will select the LSB of the Word

on the other addresses, DQ15A–1 High will select

the MSB. Throughout the text consider references

to the Data Input/Output to include this pin when

BYTE is High and references to the Address In-

puts to include this pin when BYTE is Low except

when stated explicitly otherwise.

Chip Enable (E). The Chip Enable, E, activates

the memory, allowing Bus Read and Bus Write op-

erations to be performed. When Chip Enable is

High, V_IH, all other pins are ignored.

Byte/Word Organization Select (BYTE). The

Byte/Word Organization Select pin is used to

switch between the 8-bit and 16-bit Bus modes of

the memory. When Byte/Word Organization Se-

lect is Low, V_IL, the memory is in 8-bit mode, when

it is High, V_IH, the memory is in 16-bit mode.

V

_CCSupply Voltage. The V_CCSupply Voltage

supplies the power for all operations (Read, Pro-

gram, Erase etc.).

The Command Interface is disabled when the V_CC

Supply Voltage is less than the Lockout Voltage,

V

_LKO. This prevents Bus Write operations from ac-

Output Enable (G). The Output Enable, G, con-

trols the Bus Read operation of the memory.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the memory’s Com-

mand Interface.

cidentally damaging the data during power up,

power down and power surges. If the Program/

Erase Controller is programming or erasing during

this time then the operation aborts and the memo-

ry contents being altered will be invalid.

A 0.1μF capacitor should be connected between

the V_CCSupply Voltage pin and the V_SSGround

pin to decouple the current surges from the power

supply. The PCB track widths must be sufficient to

carry the currents required during program and

Reset/Block Temporary Unprotect (RP). The

Reset/Block Temporary Unprotect pin can be

used to apply a Hardware Reset to the memory or

to temporarily unprotect all Blocks that have been

protected.

A Hardware Reset is achieved by holding Reset/

Block Temporary Unprotect Low, V_IL, for at least

erase operations, I_CC3

.

V

_SSGround. The V_SSGround is the reference for

all voltage measurements. The two V_SSpins of the

device must be connected to the system ground.

t

_PLPX. After Reset/Block Temporary Unprotect

goes High, V_IH, the memory will be ready for Bus

11/42

M29W160ET, M29W160EB

BUS OPERATIONS

There are five standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby and Automatic Standby. See

Tables 2 and 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

ance state. To reduce the Supply Current to the

Standby Supply Current, I_CC2, Chip Enable should

be held within V_CC± 0.2V. For the Standby current

level see Table 11, DC Characteristics.

During program or erase operations the memory

will continue to use the Program/Erase Supply

Current, I_CC3, for Program or Erase operations un-

til the operation completes.

Automatic Standby. If CMOS levels (V_CC± 0.2V)

are used to drive the bus and the bus is inactive for

150ns or more the memory enters Automatic

Standby where the internal Supply Current is re-

duced to the Standby Supply Current, I_CC2. The

Data Inputs/Outputs will still output data if a Bus

Read operation is in progress.

Bus Read. Bus Read operations read from the

memory cells, or specific registers in the Com-

mand Interface. A valid Bus Read operation in-

volves setting the desired address on the Address

Inputs, applying a Low signal, V_IL, to Chip Enable

and Output Enable and keeping Write Enable

High, V_IH. The Data Inputs/Outputs will output the

value, see Figure 12, Read Mode AC Waveforms,

and Table 12, Read AC Characteristics, for details

of when the output becomes valid.

Bus Write. Bus Write operations write to the

Command Interface. A valid Bus Write operation

begins by setting the desired address on the Ad-

dress Inputs. The Address Inputs are latched by

the Command Interface on the falling edge of Chip

Enable or Write Enable, whichever occurs last.

The Data Inputs/Outputs are latched by the Com-

mand Interface on the rising edge of Chip Enable

or Write Enable, whichever occurs first. Output En-

able must remain High, V_IH, during the whole Bus

Write operation. See Figures 13 and 14, Write AC

Waveforms, and Tables 13 and 14, Write AC

Characteristics, for details of the timing require-

ments.

Special Bus Operations. Additional bus opera-

tions can be performed to read the Electronic Sig-

nature and also to apply and remove Block

Protection. These bus operations are intended for

use by programming equipment and are not usu-

ally used in applications. They require V_IDto be

applied to some pins.

Electronic Signature. The memory has two

codes, the manufacturer code and the device

code, that can be read to identify the memory.

These codes can be read by applying the signals

listed in Tables 2 and 3, Bus Operations.

Block Protection and Blocks Unprotection.

Each block can be separately protected against

accidental Program or Erase. Protected blocks

can be unprotected to allow data to be changed.

Output Disable. The Data Inputs/Outputs are in

the high impedance state when Output Enable is

High, V_IH.

Standby. When Chip Enable is High, V_IH, the

memory enters Standby mode and the Data In-

puts/Outputs pins are placed in the high-imped-

There are two methods available for protecting

and unprotecting the blocks, one for use on pro-

gramming equipment and the other for in-system

use. Block Protect and Blocks Unprotect opera-

tions are described in Appendix C.

Table 2. Bus Operations, BYTE = V_IL

Data Inputs/Outputs

Address Inputs

Operation

E

G

W

DQ15A–1, A0-A19

DQ14-DQ8

DQ7-DQ0

Data Output

Data Input

Hi-Z

V_IL

X

V_IL

V_IH

X

V_IH

V_IL

V_IH

X

Bus Read

Cell Address

Hi-Z

Bus Write

Command Address

Hi-Z

Output Disable

Standby

X

Hi-Z

V_IH

Hi-Z

A0 = V_IL, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

Read Manufacturer

Code

V_IL

V_IH

Hi-Z

20h

A0 = V_IH, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

C4h (M29W160ET)

49h (M29W160EB)

Read Device Code

Note: X = V or V

IL

.

IH

12/42

M29W160ET, M29W160EB

Table 3. Bus Operations, BYTE = V_IH

Address Inputs

A0-A19

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

Bus Read

E

G

W

V_IL

X

V_IL

V_IH

X

V_IH

V_IL

V_IH

X

Cell Address

Data Output

Data Input

Hi-Z

Bus Write

Command Address

Output Disable

Standby

X

V_IH

Hi-Z

A0 = V_IL, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

Read Manufacturer

Code

V_IL

V_IH

0020h

A0 = V_IH, A1 = V_IL, A9 = V_ID,

Others V_ILor V_IH

22C4h (M29W160ET)

2249h (M29W160EB)

Read Device Code

Note: X = V or V

.

IH

IL

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. Failure to observe a valid sequence of Bus

Write operations will result in the memory return-

ing to Read mode. The long command sequences

are imposed to maximize data security.

From the Auto Select mode the Manufacturer

Code can be read using a Bus Read operation

with A0 = V_ILand A1 = V_IL. The other address bits

may be set to either V_ILor V_IH. The Manufacturer

Code for Numonyx is 0020h.

The Device Code can be read using a Bus Read

operation with A0 = V_IHand A1 = V_IL. The other

address bits may be set to either V_ILor V_IH. The

Device Code for the M29W160ET is 22C4h and

for the M29W160EB is 2249h.

The address used for the commands changes de-

pending on whether the memory is in 16-bit or 8-

bit mode. See either Table 4, or 5, depending on

the configuration that is being used, for a summary

of the commands.

The Block Protection Status of each block can be

read using a Bus Read operation with A0 = V_IL,

A1 = V_IH, and A12-A19 specifying the address of

the block. The other address bits may be set to ei-

ther V_ILor V_IH. If the addressed block is protected

then 01h is output on Data Inputs/Outputs DQ0-

DQ7, otherwise 00h is output.

Program Command. The Program command

can be used to program a value to one address in

the memory array at a time. The command re-

quires four Bus Write operations, the final write op-

eration latches the address and data, and starts

the Program/Erase Controller.

Read/Reset Command. The Read/Reset com-

mand returns the memory to its Read mode where

it behaves like a ROM or EPROM, unless other-

wise stated. It also resets the errors in the Status

Register. Either one or three Bus Write operations

can be used to issue the Read/Reset command.

The Read/Reset Command can be issued, be-

tween Bus Write cycles before the start of a pro-

gram or erase operation, to return the device to

read mode. Once the program or erase operation

has started the Read/Reset command is no longer

accepted. The Read/Reset command will not

abort an Erase operation when issued while in

Erase Suspend.

Auto Select Command. The Auto Select com-

mand is used to read the Manufacturer Code, the

Device Code and the Block Protection Status.

Three consecutive Bus Write operations are re-

quired to issue the Auto Select command. Once

the Auto Select command is issued the memory

remains in Auto Select mode until a Read/Reset

command is issued. Read CFI Query and Read/

Reset commands are accepted in Auto Select

mode, all other commands are ignored.

If the address falls in a protected block then the

Program command is ignored, the data remains

unchanged. The Status Register is never read and

no error condition is given.

During the program operation the memory will ig-

nore all commands. It is not possible to issue any

command to abort or pause the operation. Typical

program times are given in Table 6. Bus Read op-

erations during the program operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the program operation has completed the

memory returns to the Read mode, unless an error

13/42

M29W160ET, M29W160EB

has occurred. When an error occurs the memory

continues to output the Status Register. A Read/

Reset command must be issued to reset the error

condition and return to Read mode.

Note that the Program command cannot change a

bit set at ’0’ back to ’1’. One of the Erase Com-

mands must be used to set all the bits in a block or

in the whole memory from ’0’ to ’1’.

times are given in Table 6. All Bus Read opera-

tions during the Chip Erase operation will output

the Status Register on the Data Inputs/Outputs.

See the section on the Status Register for more

details.

After the Chip Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read Mode.

Unlock Bypass Command. The Unlock Bypass

command is used in conjunction with the Unlock

Bypass Program command to program the memo-

ry. When the access time to the device is long (as

with some EPROM programmers) considerable

time saving can be made by using these com-

mands. Three Bus Write operations are required

to issue the Unlock Bypass command.

The Chip Erase Command sets all of the bits in un-

protected blocks of the memory to ’1’. All previous

data is lost.

Block Erase Command. The Block Erase com-

mand can be used to erase a list of one or more

blocks. Six Bus Write operations are required to

select the first block in the list. Each additional

block in the list can be selected by repeating the

sixth Bus Write operation using the address of the

additional block. The Block Erase operation starts

the Program/Erase Controller about 50μs after the

last Bus Write operation. Once the Program/Erase

Controller starts it is not possible to select any

more blocks. Each additional block must therefore

be selected within 50μs of the last block. The 50μs

timer restarts when an additional block is selected.

The Status Register can be read after the sixth

Bus Write operation. See the Status Register sec-

tion for details on how to identify if the Program/

Erase Controller has started the Block Erase oper-

ation.

Once the Unlock Bypass command has been is-

sued the memory will only accept the Unlock By-

pass Program command and the Unlock Bypass

Reset command. The memory can be read as if in

Read mode.

Unlock Bypass Program Command. The Un-

lock Bypass Program command can be used to

program one address in memory at a time. The

command requires two Bus Write operations, the

final write operation latches the address and data,

and starts the Program/Erase Controller.

The Program operation using the Unlock Bypass

Program command behaves identically to the Pro-

gram operation using the Program command. A

protected block cannot be programmed; the oper-

ation cannot be aborted and the Status Register is

read. Errors must be reset using the Read/Reset

command, which leaves the device in Unlock By-

pass Mode. See the Program command for details

on the behavior.

Unlock Bypass Reset Command. The Unlock

Bypass Reset command can be used to return to

Read/Reset mode from Unlock Bypass Mode.

Two Bus Write operations are required to issue the

Unlock Bypass Reset command. Read/Reset

command does not exit from Unlock Bypass

Mode.

Chip Erase Command. The Chip Erase com-

mand can be used to erase the entire chip. Six Bus

Write operations are required to issue the Chip

Erase Command and start the Program/Erase

Controller.

If any selected blocks are protected then these are

ignored and all the other selected blocks are

erased. If all of the selected blocks are protected

the Block Erase operation appears to start but will

terminate within about 100μs, leaving the data un-

changed. No error condition is given when protect-

ed blocks are ignored.

During the Block Erase operation the memory will

ignore all commands except the Erase Suspend

command. Typical block erase times are given in

Table 6. All Bus Read operations during the Block

Erase operation will output the Status Register on

the Data Inputs/Outputs. See the section on the

Status Register for more details.

After the Block Erase operation has completed the

memory will return to the Read Mode, unless an

error has occurred. When an error occurs the

memory will continue to output the Status Regis-

ter. A Read/Reset command must be issued to re-

set the error condition and return to Read mode.

If any blocks are protected then these are ignored

and all the other blocks are erased. If all of the

blocks are protected the Chip Erase operation ap-

pears to start but will terminate within about 100μs,

leaving the data unchanged. No error condition is

given when protected blocks are ignored.

During the erase operation the memory will ignore

all commands. It is not possible to issue any com-

mand to abort the operation. Typical chip erase

The Block Erase Command sets all of the bits in

the unprotected selected blocks to ’1’. All previous

data in the selected blocks is lost.

Erase Suspend Command. The Erase Suspend

Command may be used to temporarily suspend a

14/42

M29W160ET, M29W160EB

Block Erase operation and return the memory to

Read mode. The command requires one Bus

Write operation.

an Erase Suspend. The Read/Reset command

must be issued to return the device to Read Array

mode before the Resume command will be ac-

cepted.

Erase Resume Command. The Erase Resume

command must be used to restart the Program/

Erase Controller from Erase Suspend. An erase

can be suspended and resumed more than once.

The Program/Erase Controller will suspend within

the Erase Suspend Latency Time (refer to Table 6

for value) of the Erase Suspend Command being

issued. Once the Program/Erase Controller has

stopped the memory will be set to Read mode and

the Erase will be suspended. If the Erase Suspend

command is issued during the period when the

memory is waiting for an additional block (before

the Program/Erase Controller starts) then the

Erase is suspended immediately and will start im-

mediately when the Erase Resume Command is

issued. It is not possible to select any further

blocks to erase after the Erase Resume.

Read CFI Query Command. The Read CFI

Query Command is used to read data from the

Common Flash Interface (CFI) Memory Area. This

command is valid when the device is in the Read

Array mode, or when the device is in Auto Select

mode.

One Bus Write cycle is required to issue the Read

CFI Query Command. Once the command is is-

sued subsequent Bus Read operations read from

the Common Flash Interface Memory Area.

The Read/Reset command must be issued to re-

turn the device to the previous mode (the Read Ar-

ray mode or Auto Select mode). A second Read/

Reset command would be needed if the device is

to be put in the Read Array mode from Auto Select

mode.

During Erase Suspend it is possible to Read and

Program cells in blocks that are not being erased;

both Read and Program operations behave as

normal on these blocks. If any attempt is made to

program in a protected block or in the suspended

block then the Program command is ignored and

the data remains unchanged. The Status Register

is not read and no error condition is given. Read-

ing from blocks that are being erased will output

the Status Register.

See Appendix B, Tables 22, 23, 24, 25, 26 and 27

for details on the information contained in the

Common Flash Interface (CFI) memory area.

It is also possible to issue the Auto Select, Read

CFI Query and Unlock Bypass commands during

15/42

M29W160ET, M29W160EB

Table 4. Commands, 16-bit mode, BYTE = V_IH

Bus Write Operations

3rd 4th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command

1st

2nd

5th

6th

1

3

4

3

X

F0

AA

Read/Reset

555

2AA

55

X

F0

90

A0

20

Auto Select

Program

555

PA

PD

Unlock Bypass

Program

2

X

A0

PA

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

555

2AA

555

80

555

AA

2AA

55

555

BA

10

30

Block Erase

6+ 555

Erase Suspend

Erase Resume

Read CFI Query

1

X

55

98

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

mands on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-

gram/Erase Controller completes and the memory returns to Read Mode.

CFI Query. Command is valid when device is ready to read array data or when device is in Auto Select mode.

16/42

M29W160ET, M29W160EB

Table 5. Commands, 8-bit mode, BYTE = V_IL

Bus Write Operations

3rd 4th

Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data

Command

1st

2nd

5th

6th

1

3

4

3

X

F0

AA

Read/Reset

AAA

555

55

X

F0

90

A0

20

Auto Select

Program

AAA

PA

PD

Unlock Bypass

Program

2

X

A0

PA

PD

Unlock Bypass Reset

Chip Erase

2

6

X

90

AA

B0

30

X

00

55

AAA

555

AAA

80

AAA

AA

555

55

AAA

BA

10

30

Block Erase

6+ AAA

Erase Suspend

Erase Resume

Read CFI Query

1

X

AA

98

Note: X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block.

All values in the table are in hexadecimal.

The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A19, DQ8-DQ14 and DQ15 are Don’t

Care. DQ15A–1 is A–1 when BYTE is V or DQ15 when BYTE is V

.

IH

IL

Read/Reset. After a Read/Reset command, read the memory as normal until another command is issued.

Auto Select. After an Auto Select command, read Manufacturer ID, Device ID or Block Protection Status.

Program, Unlock Bypass Program, Chip Erase, Block Erase. After these commands read the Status Register until the Program/

Erase Controller completes and the memory returns to Read Mode. Add additional Blocks during Block Erase Command with additional

Bus Write Operations until Timeout Bit is set.

Unlock Bypass. After the Unlock Bypass command issue Unlock Bypass Program or Unlock Bypass Reset commands.

Unlock Bypass Reset. After the Unlock Bypass Reset command read the memory as normal until another command is issued.

Erase Suspend. After the Erase Suspend command read non-erasing memory blocks as normal, issue Auto Select and Program com-

mands on non-erasing blocks as normal.

Erase Resume. After the Erase Resume command the suspended Erase operation resumes, read the Status Register until the Pro-

gram/Erase Controller completes and the memory returns to Read Mode.

CFI Query. Command is valid when device is ready to read array data or when device is in Auto Select mode.

17/42

M29W160ET, M29W160EB

Table 6. Program/Erase Times and Program/Erase Endurance Cycles

Typ ^(1,2)

Max⁽²⁾

60 ⁽³⁾

Parameter

Min

Unit

s

Chip Erase

29

1.6 ⁽⁴⁾

25 ⁽⁴⁾

Block Erase (64 KBytes)

Erase Suspend Latency Time

Program (Byte or Word)

0.8

20

s

μs

s

200 ⁽³⁾

120 ⁽³⁾

60 ⁽³⁾

13

Chip Program (Byte by Byte)

26

Chip Program (Word by Word)

Program/Erase Cycles (per Block)

Data Retention

13

s

100,000

20

cycles

years

Note: 1. Typical values measured at room temperature and nominal voltages.

2. Sampled, but not 100% tested.

3. Maximum value measured at worst case conditions for both temperature and V after 100,000 program/erase cycles .

CC

4. Maximum value measured at worst case conditions for both temperature and V

.

CC

STATUS REGISTER

Bus Read operations from any address always

read the Status Register during Program and

Erase operations. It is also read during Erase Sus-

pend when an address within a block being erased

is accessed.

Toggle Bit (DQ6). The Toggle Bit can be used to

identify whether the Program/Erase Controller has

successfully completed its operation or if it has re-

sponded to an Erase Suspend. The Toggle Bit is

output on DQ6 when the Status Register is read.

The bits in the Status Register are summarized in

Table 7, Status Register Bits.

During Program and Erase operations the Toggle

Bit changes from ’0’ to ’1’ to ’0’, etc., with succes-

sive Bus Read operations at any address. After

successful completion of the operation the memo-

ry returns to Read mode.

Data Polling Bit (DQ7). The Data Polling Bit can

be used to identify whether the Program/Erase

Controller has successfully completed its opera-

tion or if it has responded to an Erase Suspend.

The Data Polling Bit is output on DQ7 when the

Status Register is read.

During Erase Suspend mode the Toggle Bit will

output when addressing a cell within a block being

erased. The Toggle Bit will stop toggling when the

Program/Erase Controller has suspended the

Erase operation.

During Program operations the Data Polling Bit

outputs the complement of the bit being pro-

grammed to DQ7. After successful completion of

the Program operation the memory returns to

Read mode and Bus Read operations from the ad-

dress just programmed output DQ7, not its com-

plement.

During Erase operations the Data Polling Bit out-

puts ’0’, the complement of the erased state of

DQ7. After successful completion of the Erase op-

eration the memory returns to Read Mode.

If any attempt is made to erase a protected block,

the operation is aborted, no error is signalled and

DQ6 toggles for approximately 100μs. If any at-

tempt is made to program a protected block or a

suspended block, the operation is aborted, no er-

ror is signalled and DQ6 toggles for approximately

1μs.

Figure 9, Data Toggle Flowchart, gives an exam-

ple of how to use the Data Toggle Bit.

In Erase Suspend mode the Data Polling Bit will

output a ’1’ during a Bus Read operation within a

block being erased. The Data Polling Bit will

change from a ’0’ to a ’1’ when the Program/Erase

Controller has suspended the Erase operation.

Figure 8, Data Polling Flowchart, gives an exam-

ple of how to use the Data Polling Bit. A Valid Ad-

dress is the address being programmed or an

address within the block being erased.

Error Bit (DQ5). The Error Bit can be used to

identify errors detected by the Program/Erase

Controller. The Error Bit is set to ’1’ when a Pro-

gram, Block Erase or Chip Erase operation fails to

write the correct data to the memory. If the Error

Bit is set a Read/Reset command must be issued

before other commands are issued. The Error bit

is output on DQ5 when the Status Register is read.

18/42

M29W160ET, M29W160EB

Note that the Program command cannot change a

bit set to ’0’ back to ’1’ and attempting to do so will

set DQ5 to ‘1’. A Bus Read operation to that ad-

dress will show the bit is still ‘0’. One of the Erase

commands must be used to set all the bits in a

block or in the whole memory from ’0’ to ’1’

During Chip Erase and Block Erase operations the

Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with

successive Bus Read operations from addresses

within the blocks being erased. A protected block

is treated the same as a block not being erased.

Once the operation completes the memory returns

to Read mode.

During Erase Suspend the Alternative Toggle Bit

changes from ’0’ to ’1’ to ’0’, etc. with successive

Bus Read operations from addresses within the

blocks being erased. Bus Read operations to ad-

dresses within blocks not being erased will output

the memory cell data as if in Read mode.

After an Erase operation that causes the Error Bit

to be set the Alternative Toggle Bit can be used to

identify which block or blocks have caused the er-

ror. The Alternative Toggle Bit changes from ’0’ to

’1’ to ’0’, etc. with successive Bus Read Opera-

tions from addresses within blocks that have not

erased correctly. The Alternative Toggle Bit does

not change if the addressed block has erased cor-

rectly.

Erase Timer Bit (DQ3). The Erase Timer Bit can

be used to identify the start of Program/Erase

Controller operation during a Block Erase com-

mand. Once the Program/Erase Controller starts

erasing the Erase Timer Bit is set to ’1’. Before the

Program/Erase Controller starts the Erase Timer

Bit is set to ’0’ and additional blocks to be erased

may be written to the Command Interface. The

Erase Timer Bit is output on DQ3 when the Status

Register is read.

Alternative Toggle Bit (DQ2). The Alternative

Toggle Bit can be used to monitor the Program/

Erase controller during Erase operations. The Al-

ternative Toggle Bit is output on DQ2 when the

Status Register is read.

Table 7. Status Register Bits

Operation

Program

Address

DQ7

DQ6

DQ5

DQ3

DQ2

RB

Any Address

DQ7

Toggle

0

–

0

Program During Erase

Suspend

Any Address

DQ7

Toggle

0

–

0

Program Error

Chip Erase

Any Address

DQ7

Toggle

1

0

–

1

0

1

–

0

1

0

1

Toggle

Erasing Block

Toggle

Block Erase before

timeout

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

Block Erase

Erase Suspend

Erase Error

Non-Erasing Block

Erasing Block

Toggle

No Toggle

Toggle

No Toggle

Non-Erasing Block

Good Block Address

Faulty Block Address

Data read as normal

0

Toggle

1

No Toggle

Toggle

1

Note: Unspecified data bits should be ignored.

19/42

M29W160ET, M29W160EB

Figure 8. Data Polling Flowchart

Figure 9. Data Toggle Flowchart

START

READ DQ6

READ DQ5 & DQ7

at VALID ADDRESS

READ

DQ5 & DQ6

DQ7

=

DATA

YES

DQ6

NO

=

TOGGLE

NO

YES

NO

DQ5

= 1

NO

DQ5

= 1

YES

READ DQ7

at VALID ADDRESS

READ DQ6

TWICE

DQ7

=

DATA

YES

DQ6

=

NO

FAIL

TOGGLE

YES

FAIL

PASS

AI03598

AI01370C

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings" table may cause per-

manent damage to the device. Exposure to Abso-

lute Maximum Rating conditions for extended

periods may affect device reliability. These are

stress ratings only and operation of the device at

these or any other conditions above those indicat-

ed in the Operating sections of this specification is

not implied. Refer also to the Numonyx SURE Pro-

gram and other relevant quality documents.

Table 8. Absolute Maximum Ratings

Symbol

T_BIAS

Parameter

Min

–50

–65

–0.6

Max

125

Unit

°C

V

Temperature Under Bias

Storage Temperature

T_STG

150

Input or Output Voltage ^(1,2)

Supply Voltage

V_IO

V_CC

V_ID

V_CC+0.6

4

V

Identification Voltage

13.5

V

Note: 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.

2. Maximum voltage may overshoot to V +2V during transition and for less than 20ns during transitions.

CC

20/42

M29W160ET, M29W160EB

DC AND AC PARAMETERS

This section summarizes the operating measure-

ment conditions, and the DC and AC characteris-

tics of the device. The parameters in the DC and

AC characteristics Tables that follow, are derived

from tests performed under the Measurement

Conditions summarized in Table 9, Operating and

AC Measurement Conditions. Designers should

check that the operating conditions in their circuit

match the operating conditions when relying on

the quoted parameters.

Table 9. Operating and AC Measurement Conditions

M29W160E

80 ¹

Parameter

70

7A

90

Unit

Min

Max

Min

Max

Min

Max

Min

Max

V_CCSupply Voltage

2.7

3.6

2.7

3.6

2.5

3.6

2.7

3.6

V

Ambient Operating

Temperature

85 / 125 ²

30

–40

85

–40

125

–40

85

°C

Load Capacitance

(C_L)

30

pF

ns

V

Input Rise and Fall

Times

10

0 to V_CC

10

Input Pulse

Voltages

0 to V_CC

V_CC/2

0 to V_CC

V_CC/2

0 to V_CC

V_CC/2

Input and Output

Timing Ref.

Voltages

V

_CC/2

V

1.This option is allowed only with –40 °C to 125 °C devices.

2.85 °C is for industrial part code, while 125 °C is for the autograde part.

Figure 10. AC Measurement I/O Waveform

Figure 11. AC Measurement Load Circuit

V

CC

V

CC

V

/2

CC

25kΩ

0V

DEVICE

UNDER

TEST

AI04498

25kΩ

0.1µF

C

L

AI04499

C

includes JIG capacitance

L

21/42

M29W160ET, M29W160EB

Table 10. Device Capacitance

Symbol

C_IN

Parameter

Input Capacitance

Output Capacitance

Test Condition

_IN= 0V

Min

Max

6

Unit

pF

V

C_OUT

V_OUT= 0V

12

pF

Note: Sampled only, not 100% tested.

Table 11. DC Characteristics

Symbol

I_LI

Parameter

Test Condition

0V ≤ V_IN≤ V_CC

0V ≤ V_OUT≤ V_CC

Min

Typ

Max

±1

Unit

Input Leakage Current

Output Leakage Current

μA

I_LO

±1

E = V_IL, G = V_IH,

f = 6MHz

I_CC1

Supply Current (Read)

4.5

35

10

mA

μA

mA

E = V_CC±0.2V,

RP = V_CC±0.2V

I_CC2

Supply Current (Standby)

100

Supply Current

(Program/Erase)

Program/Erase

Controller active

(1)

20

I_CC3

V_IL

V_IH

V_OL

V_OH

V_ID

I_ID

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Identification Voltage

Identification Current

–0.5

0.8

V

0.7V_CC

V_CC+0.3

0.45

I_OL= 1.8mA

V

V_CC–0.4

11.5

I_OH= –100μA

V

12.5

100

V

A9 = V_ID

μA

Program/Erase Lockout

Supply Voltage

V_LKO

1.8

2.3

V

Note: 1. Sampled only, not 100% tested.

22/42

M29W160ET, M29W160EB

Figure 12. Read Mode AC Waveforms

tAVAV

VALID

A0-A19/

A–1

tAVQV

tAXQX

E

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQX

tGLQV

tGHQX

tGHQZ

DQ0-DQ7/

DQ8-DQ15

VALID

tBHQV

BYTE

tELBL/tELBH

tBLQZ

AI02922

Table 12. Read AC Characteristics

M29W160E

70/7A/80 ⁽²⁾

Symbol

Alt

Parameter

Test Condition

Unit

90

E = V_IL,

Min

t_AVAV

t_RC

Address Valid to Next Address Valid

Address Valid to Output Valid

70

90

ns

G = V_IL

E = V_IL,

Max

t_AVQV

t_ACC

90

G = V_IL

(1)

t_LZ

t_CE

t_OLZ

t_OE

t_HZ

G = V_IL

E = V_IL

G = V_IL

E = V_IL

Chip Enable Low to Output Transition

Chip Enable Low to Output Valid

Output Enable Low to Output Transition

Output Enable Low to Output Valid

Chip Enable High to Output Hi-Z

Output Enable High to Output Hi-Z

Min

Max

Min

0

ns

t_ELQX

t_ELQV

70

0

90

0

(1)

t_GLQX

t_GLQV

Max

25

35

30

(1)

t_EHQZ

(1)

t_DF

t_GHQZ

t_EHQX

t_GHQX

t_AXQX

Chip Enable, Output Enable or Address

Transition to Output Transition

t_OH

Min

0

5

0

5

ns

t_ELBL

t_ELBH

t_ELFL

t_ELFH

Chip Enable to BYTE Low or High

Max

t_BLQZ

t_BHQV

t_FLQZ

t_FHQV

BYTE Low to Output Hi-Z

BYTE High to Output Valid

Max

25

30

40

ns

Note: 1. Sampled only, not 100% tested.

2. 70 ns becomes 80 ns if the 80 ns device code is used.

23/42

M29W160ET, M29W160EB

Figure 13. Write AC Waveforms, Write Enable Controlled

tAVAV

A0-A19/

VALID

A–1

tWLAX

tAVWL

tWHEH

E

tELWL

tWHGL

G

tGHWL

tWLWH

W

tWHWL

tWHDX

tDVWH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHEL

RB

tWHRL

AI02923

Table 13. Write AC Characteristics, Write Enable Controlled

M29W160E

Symbol

Alt

Parameter

Unit

70/7A/80 ⁽²⁾

90

0

t_AVAV

t_ELWL

t_WC

t_CS

t_WP

t_DS

Address Valid to Next Address Valid

Chip Enable Low to Write Enable Low

Write Enable Low to Write Enable High

Input Valid to Write Enable High

Min

Max

70

0

ns

t_WLWH

t_DVWH

t_WHDX

t_WHEH

t_WHWL

t_AVWL

t_WLAX

t_GHWL

t_WHGL

45

0

50

0

t_DH

t_CH

t_WPH

t_AS

Write Enable High to Input Transition

Write Enable High to Chip Enable High

Write Enable High to Write Enable Low

Address Valid to Write Enable Low

Write Enable Low to Address Transition

Output Enable High to Write Enable Low

Write Enable High to Output Enable Low

Program/Erase Valid to RB Low

0

30

0

30

0

t_AH

45

0

50

0

t_OEH

t_BUSY

t_VCS

0

(1)

30

50

35

t_WHRL

t_VCHEL

V_CCHigh to Chip Enable Low

Min

50

μs

Note: 1. Sampled only, not 100% tested.

2. 70 ns becomes 80 ns if the 80 ns device code is used.

24/42

M29W160ET, M29W160EB

Figure 14. Write AC Waveforms, Chip Enable Controlled

tAVAV

A0-A19/

VALID

A–1

tELAX

tAVEL

tEHWH

tEHGL

W

tWLEL

G

tGHEL

tELEH

E

tEHEL

tEHDX

tDVEH

VALID

DQ0-DQ7/

DQ8-DQ15

V

CC

tVCHWL

RB

tEHRL

AI02924

Table 14. Write AC Characteristics, Chip Enable Controlled

M29W160E

Unit

Symbol

Alt

Parameter

70/7A/80 ⁽²⁾

90

t_AVAV

t_WLEL

t_ELEH

t_DVEH

t_EHDX

t_EHWH

t_EHEL

t_AVEL

t_ELAX

t_GHEL

t_EHGL

t_WC

t_WS

t_CP

Address Valid to Next Address Valid

Write Enable Low to Chip Enable Low

Chip Enable Low to Chip Enable High

Input Valid to Chip Enable High

Min

70

0

90

0

ns

45

0

50

0

t_DS

t_DH

t_WH

t_CPH

t_AS

Chip Enable High to Input Transition

Chip Enable High to Write Enable High

Chip Enable High to Chip Enable Low

Address Valid to Chip Enable Low

Chip Enable Low to Address Transition

Output Enable High Chip Enable Low

Chip Enable High to Output Enable Low

0

30

0

30

0

t_AH

45

0

50

0

t_OEH

t_BUSY

t_VCS

0

(1)

Program/Erase Valid to RB Low

V_CCHigh to Write Enable Low

Max

Min

30

50

35

50

ns

t_EHRL

t_VCHWL

μs

Note: 1. Sampled only, not 100% tested.

2. 70 ns becomes 80 ns if the 80 ns device code is used.

25/42

M29W160ET, M29W160EB

Figure 15. Reset/Block Temporary Unprotect AC Waveforms

W, E, G

tPHWL, tPHEL, tPHGL

RB

tRHWL, tRHEL, tRHGL

tPHPHH

tPLPX

RP

tPLYH

AI02931B

Table 15. Reset/Block Temporary Unprotect AC Characteristics

M29W160E

Symbol

Alt

Parameter

Unit

70/7A/80

90

(1)

t_PHWL

RP High to Write Enable Low, Chip Enable Low,

Output Enable Low

t_PHEL

t_RH

Min

50

ns

(1)

t_PHGL

(1)

t_RHWL

RB High to Write Enable Low, Chip Enable Low,

Output Enable Low

(1)

t_RB

0

ns

t_RHEL

(1)

t_RHGL

t_PLPX

t_RP

RP Pulse Width

Min

500

10

500

10

ns

(1)

t_READY

t_VIDR

RP Low to Read Mode

RP Rise Time to V_ID

Max

μs

t_PLYH

(1)

Min

500

ns

t_PHPHH

Note: 1. Sampled only, not 100% tested.

26/42

M29W160ET, M29W160EB

PACKAGE MECHANICAL

Figure 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline, top view

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

Note: Drawing is not to scale.

Table 16. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

Typ

Max

A

A1

A2

B

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

α

0

5

0

5

27/42

M29W160ET, M29W160EB

Figure 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Outline, bottom view

D

D1

FD

FE

SD

SE

BALL "A1"

E

E1

ddd

e

b

A

A2

A1

BGA-Z32

Table 17. TFBGA48 6x8mm - 6x8 ball array, 0.80 mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.260

0.0102

0.900

0.0354

0.350

5.900

–

0.450

0.0138

0.2323

–

0.0177

D

6.000

4.000

6.100

0.2362

0.1575

0.2402

D1

ddd

E

–

0.100

0.0039

8.000

5.600

0.800

1.000

1.200

0.400

7.900

8.100

0.3150

0.2205

0.0315

0.0394

0.0472

0.0157

0.3110

0.3189

E1

e

–

FD

FE

SD

SE

28/42

M29W160ET, M29W160EB

Figure 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package outline, bottom view

D

D1

FD

FE

SD

SE

E

E1

ddd

BALL "A1"

A

e

b

A2

A1

BGA-Z23

Table 18. FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data

millimeters

inches

Min

—

Symbol

Typ

—

Min

—

Max

1.40

0.53

—

Typ

—

Max

A

A1

A2

b

0.055

0.48

0.80

—

0.43

—

0.018

0.031

—

0.016

—

0.025

0.437

—

0.55

10.90

—

0.65

11.10

—

0.021

0.429

—

D

11.00

7.00

—

0.433

0.275

—

D1

ddd

e

—

0.15

—

0.0059

—

1.00

13.0

7.00

2.00

3.00

0.50

—

0.039

0.511

0.275

0.078

0.118

0.0196

—

E

12.90

—

13.10

—

0.507

—

0.515

—

E1

FD

FE

SD

SE

—

29/42

M29W160ET, M29W160EB

PART NUMBERING

Table 19. Ordering Information Scheme

Example:

M29W160EB

7A

N

3

S

E

Device Type

M29 = Parallel Flash Memory

Device Function

W = 2.7 V to 3.6 V main family

Array Size

160E = 16 Mbit Memory Array

Configuration

T = Top Boot

B = Bottom Boot

Speed Class

7A = 70 ns device speed in conjunction with temperature

range = 6 to denote Auto Grade (–40 to 85 °C) parts

70 = 70 ns device speed in conjunction with temperature

range = 6 to denote Industrial Grade (–40 to 85 °C) parts;

or in conjunction with temperature range = 3 to denote

Auto Grade (–40 to 125 °C) parts

80 = 80 ns access time Auto Device in conjunction with

temperature range = 3 and voltage extension = S

90 = 90 ns device speed in conjunction with temperature

range = 6 to denote Industrial Grade (–40 to 85 °C) parts

Package Option

N = TSOP48: 12 x 20 mm

ZA = TFBGA48: 6x8 mm, 0.80mm pitch

ZS = FBGA64: 11 x 13 mm, 1 mm pitch

Temperature Range

6 = Temperature range (–40 to 85 °C)

3 = Automotive temperature range (–40 to 125 °C)

Voltage Extension

Blank = Standard option

S = V_CCmin extension to 2.5 °C and available only with 80

ns Speed Class Option

Packing Option

Blank = Standard Packing

T = Tape and Reel Packing

E = RoHS, Standard Packing

F = RoHS, Tape & Reel Packing

Devices are shipped from the factory with the memory content bits erased to ’1’.

For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device,

please contact the Numonyx Sales Office nearest to you.

30/42

M29W160ET, M29W160EB

APPENDIX A. BLOCK ADDRESS TABLE

Table 20. Top Boot Block Addresses,

M29W160ET

Table 21. Bottom Boot Block Addresses,

M29W160EB

Size

(KBytes)

Address Range

(x8)

Address Range

(x16)

Size

(KBytes)

Address Range

(x8)

Address Range

(x16)

#

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

16

8

1FC000h-1FFFFFh FE000h-FFFFFh

1FA000h-1FBFFFh FD000h-FDFFFh

1F8000h-1F9FFFh FC000h-FCFFFh

1F0000h-1F7FFFh F8000h-FBFFFh

1E0000h-1EFFFFh F0000h-F7FFFh

1D0000h-1DFFFFh E8000h-EFFFFh

1C0000h-1CFFFFh E0000h-E7FFFh

1B0000h-1BFFFFh D8000h-DFFFFh

1A0000h-1AFFFFh D0000h-D7FFFh

190000h-19FFFFh C8000h-CFFFFh

180000h-18FFFFh C0000h-C7FFFh

170000h-17FFFFh B8000h-BFFFFh

160000h-16FFFFh B0000h-B7FFFh

150000h-15FFFFh A8000h-AFFFFh

140000h-14FFFFh A0000h-A7FFFh

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

64

32

8

1F0000h-1FFFFFh F8000h-FFFFFh

1E0000h-1EFFFFh F0000h-F7FFFh

1D0000h-1DFFFFh E8000h-EFFFFh

1C0000h-1CFFFFh E0000h-E7FFFh

1B0000h-1BFFFFh D8000h-DFFFFh

1A0000h-1AFFFFh D0000h-D7FFFh

190000h-19FFFFh C8000h-CFFFFh

180000h-18FFFFh C0000h-C7FFFh

170000h-17FFFFh B8000h-BFFFFh

160000h-16FFFFh B0000h-B7FFFh

150000h-15FFFFh A8000h-AFFFFh

140000h-14FFFFh A0000h-A7FFFh

130000h-13FFFFh 98000h-9FFFFh

120000h-12FFFFh 90000h-97FFFh

110000h-11FFFFh 88000h-8FFFFh

100000h-10FFFFh 80000h-87FFFh

0F0000h-0FFFFFh 78000h-7FFFFh

0E0000h-0EFFFFh 70000h-77FFFh

0D0000h-0DFFFFh 68000h-6FFFFh

0C0000h-0CFFFFh 60000h-67FFFh

0B0000h-0BFFFFh 58000h-5FFFFh

0A0000h-0AFFFFh 50000h-57FFFh

090000h-09FFFFh 48000h-4FFFFh

080000h-08FFFFh 40000h-47FFFh

070000h-07FFFFh 38000h-3FFFFh

060000h-06FFFFh 30000h-37FFFh

050000h-05FFFFh 28000h-2FFFFh

040000h-04FFFFh 20000h-27FFFh

030000h-03FFFFh 18000h-1FFFFh

020000h-02FFFFh 10000h-17FFFh

010000h-01FFFFh 08000h-0FFFFh

008000h-00FFFFh 04000h-07FFFh

006000h-007FFFh 03000h-03FFFh

004000h-005FFFh 02000h-02FFFh

000000h-003FFFh 00000h-01FFFh

8

32

64

130000h-13FFFFh

120000h-12FFFFh

110000h-11FFFFh

100000h-10FFFFh

0F0000h-0FFFFFh

98000h-9FFFFh

90000h-97FFFh

88000h-8FFFFh

80000h-87FFFh

78000h-7FFFFh

0E0000h-0EFFFFh 70000h-77FFFh

0D0000h-0DFFFFh 68000h-6FFFFh

0C0000h-0CFFFFh 60000h-67FFFh

0B0000h-0BFFFFh 58000h-5FFFFh

0A0000h-0AFFFFh 50000h-57FFFh

090000h-09FFFFh

080000h-08FFFFh

070000h-07FFFFh

060000h-06FFFFh

050000h-05FFFFh

040000h-04FFFFh

030000h-03FFFFh

020000h-02FFFFh

010000h-01FFFFh

000000h-00FFFFh

48000h-4FFFFh

40000h-47FFFh

38000h-3FFFFh

30000h-37FFFh

28000h-2FFFFh

20000h-27FFFh

18000h-1FFFFh

10000h-17FFFh

08000h-0FFFFh

00000h-07FFFh

8

7

6

5

4

3

2

1

8

0

16

31/42

M29W160ET, M29W160EB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

and 27 show the addresses used to retrieve the

data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 27, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by Numonyx. Issue a

Read command to return to Read mode.

When the CFI Query Command is issued the de-

vice enters CFI Query mode and the data structure

is read from the memory. Tables 22, 23, 24, 25, 26

Note: The Common Flash Interface is only avail-

able for Temperature range 6 (–40 to 85°C).

Table 22. Query Structure Overview

Address

Sub-section Name

Description

x16

10h

1Bh

27h

x8

20h

36h

4Eh

CFI Query Identification String

System Interface Information

Device Geometry Definition

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Primary Algorithm-specific Extended

Query table

Additional information specific to the Primary

Algorithm (optional)

40h

80h

61h

C2h

Security Code Area

64 bit unique device number

Note: Query data are always presented on the lowest order data outputs.

Table 23. CFI Query Identification String

Address

Data

Description

Value

x16

10h

11h

12h

13h

14h

15h

16h

17h

18h

19h

1Ah

x8

20h

22h

24h

26h

28h

2Ah

2Ch

2Eh

30h

32h

34h

0051h

0052h

0059h

0002h

0000h

0040h

0000h

"Q"

"R"

"Y"

Query Unique ASCII String "QRY"

Primary Algorithm Command Set and Control Interface ID code 16 bit

ID code defining a specific algorithm

AMD

Compatible

Address for Primary Algorithm extended Query table (see Table 25)

P = 40h

NA

Alternate Vendor Command Set and Control Interface ID Code second

vendor - specified algorithm supported

Address for Alternate Algorithm extended Query table

NA

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

32/42

M29W160ET, M29W160EB

Table 24. CFI Query System Interface Information

Address

Data

Description

Value

x16

x8

V

_CCLogic Supply Minimum Program/Erase voltage

bit 7 to 4BCD value in volts

bit 3 to 0BCD value in 100 mV

1Bh

36h

0027h

0036h

2.7V

3.6V

_CCLogic Supply Maximum Program/Erase voltage

bit 7 to 4BCD value in volts

1Ch

38h

bit 3 to 0BCD value in 100 mV

V_PP[Programming] Supply Minimum Program/Erase voltage

_PP[Programming] Supply Maximum Program/Erase voltage

1Dh

1Eh

1Fh

3Ah

3Ch

3Eh

0000h

0004h

NA

V

Typical timeout per single Byte/Word program = 2ⁿμs

Typical timeout for minimum size write buffer program = 2ⁿμs

Typical timeout per individual block erase = 2ⁿms

16μs

20h

21h

22h

23h

24h

25h

26h

40h

42h

44h

46h

48h

4Ah

4Ch

0000h

000Ah

0000h

0004h

0000h

0003h

0000h

NA

1s

Typical timeout for full chip erase = 2ⁿms

NA

Maximum timeout for Byte/Word program = 2ⁿtimes typical

Maximum timeout for write buffer program = 2ⁿtimes typical

Maximum timeout per individual block erase = 2ⁿtimes typical

Maximum timeout for chip erase = 2ⁿtimes typical

256μs

NA

8s

NA

33/42

M29W160ET, M29W160EB

Table 25. Device Geometry Definition

Address

Data

Description

Device Size = 2ⁿin number of Bytes

Value

x16

x8

27h

4Eh

0015h

2 MByte

28h

29h

50h

52h

0002h

0000h

x8, x16

Async.

Flash Device Interface Code description

2Ah

2Bh

54h

56h

0000h

Maximum number of Bytes in multi-Byte program or page = 2ⁿ

NA

4

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing

contiguous Erase Blocks of the same size.

2Ch

58h

0004h

2Dh

2Eh

5Ah

5Ch

0000h

Region 1 Information

Number of identical size erase block = 0000h+1

1

16 KByte

2

2Fh

30h

5Eh

60h

0040h

0000h

Region 1 Information

Block size in Region 1 = 0040h * 256 Byte

31h

32h

62h

64h

0001h

0000h

Region 2 Information

Number of identical size erase block = 0001h+1

33h

34h

66h

68h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 Byte

8 KByte

1

35h

36h

6Ah

6Ch

0000h

Region 3 Information

Number of identical size erase block = 0000h+1

37h

38h

6Eh

70h

0080h

0000h

Region 3 Information

Block size in Region 3 = 0080h * 256 Byte

32 KByte

31

39h

3Ah

72h

74h

001Eh

0000h

Region 4 Information

Number of identical-size erase block = 001Eh+1

3Bh

3Ch

76h

78h

0000h

0001h

Region 4 Information

Block size in Region 4 = 0100h * 256 Byte

64 KByte

34/42

M29W160ET, M29W160EB

Table 26. Primary Algorithm-Specific Extended Query Table

Address

Data

Description

Value

x16

40h

41h

42h

43h

44h

45h

x8

80h

82h

84h

86h

88h

8Ah

0050h

0052h

0049h

0031h

0030h

0000h

"P"

Primary Algorithm extended Query table unique ASCII string “PRI”

"R"

"I"

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Yes

Address Sensitive Unlock (bits 1 to 0)

00 = required, 01= not required

Silicon Revision Number (bits 7 to 2)

46h

47h

48h

49h

8Ch

8Eh

90h

92h

0002h

0001h

0004h

Erase Suspend

00 = not supported, 01 = Read only, 02 = Read and Write

2

1

Block Protection

00 = not supported, x = number of blocks in per group

Temporary Block Unprotect

00 = not supported, 01 = supported

Yes

4

Block Protect /Unprotect

04 = M29W400B

4Ah

4Bh

4Ch

94h

96h

98h

0000h

Simultaneous Operations, 00 = not supported

No

Burst Mode, 00 = not supported, 01 = supported

Page Mode, 00 = not supported, 01 = 4 page Word, 02 = 8 page Word

Table 27. Security Code Area

Address

Data

Description

x16

61h

62h

63h

64h

x8

C3h, C2h

C5h, C4h

C7h, C6h

C9h, C8h

XXXX

64 bit: unique device number

35/42

M29W160ET, M29W160EB

APPENDIX C. BLOCK PROTECTION

Block protection can be used to prevent any oper-

ation from modifying the data stored in the Flash

memory. Each Block can be protected individually.

Once protected, Program and Erase operations

on the block fail to change the data.

Programmer Equipment Chip Unprotect Flow-

chart. Table 28, Programmer Technique Bus Op-

erations, gives a summary of each operation.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not abort the procedure before reaching the end.

Chip Unprotect can take several seconds and a

user message should be provided to show that the

operation is progressing.

There are three techniques that can be used to

control Block Protection, these are the Program-

mer technique, the In-System technique and Tem-

porary Unprotection. Temporary Unprotection is

controlled by the Reset/Block Temporary Unpro-

tection pin, RP; this is described in the Signal De-

scriptions section.

Unlike the Command Interface of the Program/

Erase Controller, the techniques for protecting and

unprotecting blocks could change between differ-

ent Flash memory suppliers.

In-System Technique

The In-System technique requires a high voltage

level on the Reset/Blocks Temporary Unprotect

pin, RP. This can be achieved without violating the

maximum ratings of the components on the micro-

processor bus, therefore this technique is suitable

for use after the Flash memory has been fitted to

the system.

Programmer Technique

The Programmer technique uses high (V_ID) volt-

age levels on some of the bus pins. These cannot

be achieved using a standard microprocessor bus,

therefore the technique is recommended only for

use in Programming Equipment.

To protect a block follow the flowchart in Figure 19,

Programmer Equipment Block Protect Flowchart.

During the Block Protect algorithm, the A19-A12

Address Inputs indicate the address of the block to

be protected. The block will be correctly protected

only if A19-A12 remain valid and stable, and if

Chip Enable is kept Low, V_IL, all along the Protect

and Verify phases.

To protect a block follow the flowchart in Figure 21,

In-System Block Protect Flowchart. To unprotect

the whole chip it is necessary to protect all of the

blocks first, then all the blocks can be unprotected

at the same time. To unprotect the chip follow Fig-

ure 22, In-System Chip Unprotect Flowchart.

The timing on these flowcharts is critical. Care

should be taken to ensure that, where a pause is

specified, it is followed as closely as possible. Do

not allow the microprocessor to service interrupts

that will upset the timing and do not abort the pro-

cedure before reaching the end. Chip Unprotect

can take several seconds and a user message

should be provided to show that the operation is

progressing.

The Chip Unprotect algorithm is used to unprotect

all the memory blocks at the same time. This algo-

rithm can only be used if all of the blocks are pro-

tected first. To unprotect the chip follow Figure 20,

Table 28. Programmer Technique Bus Operations, BYTE = V_IHor V_IL

Address Inputs

Data Inputs/Outputs

DQ15A–1, DQ14-DQ0

Operation

E

G

W

A0-A19

A9 = V_ID, A12-A19 Block Address

Others = X

V_IL

V_ID

V_IDV_ILPulse

Block Protect

X

A9 = V_ID, A12 = V_IH, A15 = V_IH

Others = X

Chip Unprotect

A0 = V_IL, A1 = V_IH, A6 = V_IL, A9 = V_ID,

A12-A19 Block Address

Others = X

Block Protection

Verify

Pass = XX01h

Retry = XX00h

V_IL

V_IH

A0 = V_IL, A1 = V_IH, A6 = V_IH, A9 = V_ID,

A12-A19 Block Address

Others = X

Block Unprotection

Verify

Retry = XX01h

Pass = XX00h

V_IH

36/42

M29W160ET, M29W160EB

Figure 19. Programmer Equipment Block Protect Flowchart

START

ADDRESS = BLOCK ADDRESS

W = V

IH

n = 0

G, A9 = V

E = V

,

ID

IL

Wait 4µs

(1)

W = V

IL

Wait 100µs

W = V

IH

E, G = V

,

IH

A0, A6 = V

A1 = V

,

IL

IH

(1)

E = V

IL

Wait 4µs

G = V

IL

Wait 60ns

Read DATA

DATA

=

01h

NO

YES

++n

= 25

NO

A9 = V

IH

E, G = V

IH

YES

PASS

A9 = V

E, G = V

IH

AI03469b

FAIL

Note: 1. Address Inputs A19-A12 give the address of the block that is to be protected. It is imperative that they remain stable during the

operation.

2. During the Protect and Verify phases of the algorithm, Chip Enable E must be kept Low, V

.

IL

37/42

M29W160ET, M29W160EB

Figure 20. Programmer Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

(1)

A6, A12, A15 = V

IH

E, G, A9 = V

ID

Wait 4µs

W = V

IL

Wait 10ms

W = V

IH

E, G = V

IH

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1, A6 = V

IL

IH

E = V

IL

Wait 4µs

G = V

IL

INCREMENT

CURRENT BLOCK

Wait 60ns

Read DATA

NO

YES

DATA

=

00h

LAST

BLOCK

NO

++n

= 1000

YES

A9 = V

E, G = V

IH

E, G = V

IH

FAIL

PASS

AI03470

38/42

M29W160ET, M29W160EB

Figure 21. In-System Equipment Block Protect Flowchart

START

n = 0

RP = V

ID

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

WRITE 60h

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 100µs

WRITE 40h

IL

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

Wait 4µs

READ DATA

ADDRESS = BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

IL

DATA

NO

=

01h

YES

RP = V

++n

= 25

NO

IH

YES

RP = V

ISSUE READ/RESET

COMMAND

IH

PASS

ISSUE READ/RESET

COMMAND

FAIL

AI03471

39/42

M29W160ET, M29W160EB

Figure 22. In-System Equipment Chip Unprotect Flowchart

START

PROTECT ALL BLOCKS

n = 0

CURRENT BLOCK = 0

RP = V

ID

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

WRITE 60h

ANY ADDRESS WITH

A0 = V , A1 = V , A6 = V

IL

IH

Wait 10ms

WRITE 40h

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

Wait 4µs

INCREMENT

CURRENT BLOCK

READ DATA

ADDRESS = CURRENT BLOCK ADDRESS

A0 = V , A1 = V , A6 = V

IL

IH

DATA

NO

YES

=

00h

++n

= 1000

NO

LAST

BLOCK

YES

RP = V

YES

RP = V

IH

ISSUE READ/RESET

COMMAND

ISSUE READ/RESET

COMMAND

PASS

FAIL

AI03472

40/42

M29W160ET, M29W160EB

REVISION HISTORY

Table 29. Document Revision History

Date

Version

Revision Details

06-Aug-2002

-01

First Issue: originates from M29W160D datasheet dated 24-Jun-2002

9x8mm FBGA48 package replaced by 6x8mm. VDD(min) reduced for -70ns

speed class.

Erase Suspend Latency Time (typical and maximum) added to Program, Erase

Times and Program, Erase Endurance Cycles table. Logic Diagram corrected.

27-Nov-2002

1.1

03-Dec-2002

21-Mar-2003

1.2

2.0

Package information corrected in ordering information table.

Document promoted to full Datasheet status. Block Protect and Chip Unprotect

algorithms specified in Appendix C, BLOCK PROTECTION.

27-Jun-2003

26-Jan-2004

27-Mar-2008

12-March-2009

2.1

3.0

4.0

5.0

TSOP48 package information updated (see Figure 16 and Table 16).

Block Erase Command clarified.

Applied Numonyx branding.

Added FBGA (ZS) package and ballout information.

Revised Chip Erase signal value (maximum) in Table 6., Program/Erase Times

and Program/Erase Endurance Cycles from 120 to 60 seconds

Revised Block Erase (64-Kbytes) signal value (maximum) in Table 6., Program/

Erase Times and Program/Erase Endurance Cycles from 6 to 1.6 seconds.

Revised tGLQV (70 ns speed) value in Table 12., Read AC Characteristics from

30 to 25 ns.

7-April-2009

6.0

Added 7A and 80 ns columns to Table 9., Operating and AC Measurement

Conditions;

Added note 2 to tables: 12, 13, and 14.

Updated the order information table as follows:

Added 7A, 70, 80, and 90 ns speed class options

Added temperature range = 3 Automotive

Added Voltage extension option S.

7-May-2009

7.0

8.0

Corrected VCC supply voltage typographical errors in Table 9., Operating and AC

Measurement Conditions

18-June-2009

41/42

M29W160ET, M29W160EB

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX

DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR

WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT

OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented

subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or

otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting

Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

42/42


型号：	M29W160ET70ZA3E
厂家：	NUMONYX B.V
描述：	Flash, 1MX16, 70ns, PBGA48, 6 X 8 MM, 0.80 MM PITCH, ROHS COMPLIANT, TFBGA-48 内存集成电路
文件：	总42页 (文件大小：1209K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M29W160ET70ZA3E [NUMONYX]

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