M28W160CT90N6F_技术文档

M28W160CT

M28W160CB

16 Mbit (1Mb x16, Boot Block)

3V Supply Flash Memory

FEATURES SUMMARY

■ SUPPLY VOLTAGE

Figure 1. Packages

– V = 2.7V to 3.6V Core Power Supply

DD

– V

= 1.65V to 3.6V for Input/Output

DDQ

FBGA

– V = 12V for fast Program (optional)

PP

■ ACCESS TIME: 70, 85, 90,100ns

■ PROGRAMMING TIME:

TFBGA46 (ZB)

6.39 x 6.37mm

– 10µs typical

– Double Word Programming Option

■ COMMON FLASH INTERFACE

– 64 bit Security Code

■ MEMORY BLOCKS

– Parameter Blocks (Top or Bottom location)

– Main Blocks

■ BLOCK LOCKING

TSOP48 (N)

12 x 20mm

– All blocks locked at Power Up

– Any combination of blocks can be locked

– WP for Block Lock-Down

■ SECURITY

– 64 bit user Programmable OTP cells

– 64 bit unique device identifier

– One Parameter Block Permanently Lockable

■ AUTOMATIC STAND-BY MODE

■ PROGRAM and ERASE SUSPEND

■ ELECTRONIC SIGNATURE

– Manufacturer Code: 20h

Table 1. Device Codes

Root Part Number

M28W160CT

M28W160CB

Device Code

88CEh

■ 100,000 PROGRAM/ERASE CYCLES per

BLOCK

88CFh

®

■ ECOPACK PACKAGES AVAILABLE

December 2007

1/50

M28W160CT, M28W160CB

TABLE OF CONTENTS

SUMMARY DESCRIPTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 3. TSOP Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

Figure 4. TFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

Figure 5. Block Addresses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Figure 6. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Address Inputs (A0-A19). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

V

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DD

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

DDQ

Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

PP

SS

BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Automatic Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Memory Array Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Read CFI Query Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Clear Status Register Command. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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M28W160CT, M28W160CB

Table 4. Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 5. Read Electronic Signature. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

Table 6. Read Block Lock Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 7. Read Protection Register and Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

Table 8. Program, Erase Times and Program/Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . . 15

BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

Table 9. Block Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

Table 10. Protection Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program/Erase Controller Status (Bit 7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Suspend Status (Bit 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Erase Status (Bit 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Program Status (Bit 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

V

Status (Bit 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

PP

Program Suspend Status (Bit 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

Block Protection Status (Bit 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Reserved (Bit 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

Table 11. Status Register Bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

Table 12. Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

DC and AC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 13. Operating and AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 7. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Figure 8. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 14. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Table 15. DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

Figure 9. Read Mode AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Table 16. Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Figure 10. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

Table 17. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Figure 11. Write AC Waveforms, Chip Enable Controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

Table 18. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Figure 12. Power-Up and Reset AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

Table 19. Power-Up and Reset AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

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M28W160CT, M28W160CB

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline . . . . . . . . 29

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data . 29

Figure 14. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline30

Table 21. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data . . . 30

Figure 15. TFBGA46 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 31

Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package) . . . . 31

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 22. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

Table 23. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 24. Top Boot Block Addresses, M28W160CT. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

Table 25. Bottom Boot Block Addresses, M28W160CB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

APPENDIX B. COMMON FLASH INTERFACE (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 26. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 27. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

Table 28. CFI Query System Interface Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Table 29. Device Geometry Definition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

Table 30. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

Table 31. Security Code Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 17. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

Figure 18. Double Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Figure 19. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 42

Figure 20. Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 44

Figure 22. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Figure 23. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 46

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE . . . . . . . 47

Table 32. Write State Machine Current/Next, sheet 1 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

Table 33. Write State Machine Current/Next, sheet 2 of 2.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

REVISION HISTORY. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

Table 34. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49

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M28W160CT, M28W160CB

SUMMARY DESCRIPTION

The M28W160C is a 16 Mbit (1 Mbit x 16) non-vol-

atile Flash memory that can be erased electrically

at the block level and programmed in-system on a

Word-by-Word basis. These operations can be

performed using a single low voltage (2.7 to 3.6V)

The device includes a 128 bit Protection Register

and a Security Block to increase the protection of

a system design. The Protection Register is divid-

ed into two 64 bit segments, the first one contains

a unique device number written by Numonyx,

while the second one is one-time-programmable

by the user. The user programmable segment can

be permanently protected. The Security Block, pa-

rameter block 0, can be permanently protected by

the user. Figure 6, shows the Security Block and

Protection Register Memory Map.

Program and Erase commands are written to the

Command Interface of the memory. An on-chip

Program/Erase Controller takes care of the tim-

ings necessary for program and erase operations.

The end of a program or erase operation can be

detected and any error conditions identified. The

command set required to control the memory is

consistent with JEDEC standards.

supply. V

allows to drive the I/O pin down to

DDQ

1.65V. An optional 12V V power supply is pro-

PP

vided to speed up customer programming.

The device features an asymmetrical blocked ar-

chitecture. The M28W160C has an array of 39

blocks: 8 Parameter Blocks of 4 KWord and 31

Main Blocks of 32 KWord. M28W160CT has the

Parameter Blocks at the top of the memory ad-

dress space while the M28W160CB locates the

Parameter Blocks starting from the bottom. The

memory maps are shown in Figure 5, Block Ad-

dresses.

The M28W160C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency, enabling in-

stant code and data protection. All blocks have

three levels of protection. They can be locked and

locked-down individually preventing any acciden-

tal programming or erasure. There is an additional

hardware protection against program and erase.

The memory is offered in TSOP48 (10 X 20mm)

and TFBGA46 (6.39 x 6.37mm, 0.75mm pitch)

packages and is supplied with all the bits erased

(set to ’1’).

In order to meet environmental requirements, Nu-

®

monyx offers the M28W160C in ECOPACK

packages.

When V ≤V

all blocks are protected against

PPLK

PP

program or erase. All blocks are locked at power-

ECOPACK packages are Lead-free. The category

of second Level Interconnect is marked on the

package and on the inner box label, in compliance

with JEDEC Standard JESD97. The maximum rat-

ings related to soldering conditions are also

marked on the inner box label.

up.

Each block can be erased separately. Erase can

be suspended in order to perform either read or

program in any other block and then resumed.

Program can be suspended to read data in any

other block and then resumed. Each block can be

programmed and erased over 100,000 cycles.

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M28W160CT, M28W160CB

Figure 2. Logic Diagram

Table 2. Signal Names

A0-A19

Address Inputs

V

DD DDQ PP

DQ0-DQ15

Data Input/Output

Chip Enable

20

16

E

A0-A19

DQ0-DQ15

G

Output Enable

Write Enable

W

E

W

M28W160CT

M28W160CB

RP

WP

Reset

G

Write Protect

RP

WP

V

Core Power Supply

Power Supply for Input/Output

DD

V

DDQ

Optional Supply Voltage for Fast

Program & Erase

V

PP

SS

V

SS

Ground

AI03811

NC

Not Connected Internally

Figure 3. TSOP Connections

A15

A14

A13

A12

A11

A10

A9

1

48

A16

V

DDQ

SS

DQ15

DQ7

DQ14

DQ6

A8

DQ13

DQ5

NC

W

DQ12

DQ4

RP

12

13

37

36

V

M28W160CT

M28W160CB

DD

V

DQ11

DQ3

DQ10

DQ2

DQ9

DQ1

DQ8

DQ0

G

PP

WP

A19

A18

A17

A7

A6

A5

A4

A3

V

E

SS

A2

A1

24

25

A0

AI03812

6/50

M28W160CT, M28W160CB

Figure 4. TFBGA Connections (Top view through package)

1

2

3

4

5

6

7

8

WP

A18

A19

A17

A

B

C

D

E

F

A13

A14

A15

A16

A11

A10

A8

W

V

A7

A5

A4

A2

A1

A0

PP

RP

A12

A9

A6

A3

DQ11

DQ12

DQ4

DQ2

DQ3

DQ14

DQ15

DQ7

DQ5

DQ6

DQ13

DQ8

DQ9

DQ10

E

V

DQ0

DQ1

V

DDQ

SS

V

SS

DD

G

AI03804

7/50

M28W160CT, M28W160CB

Figure 5. Block Addresses

M28W160CT

M28W160CB

Top Boot Block Addresses

Bottom Boot Block Addresses

FFFFF

4 KWords

FF000

32 KWords

F8000

F7FFF

Total of 8

4 KWord Blocks

F0000

Total of 31

32 KWord Blocks

F8FFF

4 KWords

F8000

F7FFF

32 KWords

F0000

0FFFF

32 KWords

4 KWords

08000

07FFF

Total of 31

07000

32 KWord Blocks

Total of 8

0FFFF

4 KWord Blocks

32 KWords

08000

07FFF

00FFF

00000

32 KWords

4 KWords

00000

AI04311

Note: Also see Appendix A, Tables 24 and 25 for a full listing of the Block Addresses.

Figure 6. Security Block and Protection Register Memory Map

PROTECTION REGISTER

User Programmable OTP

88h

SECURITY BLOCK

Parameter Block # 0

85h

84h

Unique device number

81h

80h

Protection Register Lock

2

1

0

AI03523

8/50

M28W160CT, M28W160CB

SIGNAL DESCRIPTIONS

See Figure 2 Logic Diagram and Table 2,Signal

Names, for a brief overview of the signals connect-

ed to this device.

Address Inputs (A0-A19). The Address Inputs

select the cells in the memory array to access dur-

ing Bus Read operations. During Bus Write opera-

tions they control the commands sent to the

Command Interface of the internal state machine.

Data Input/Output (DQ0-DQ15). The Data I/O

outputs the data stored at the selected address

during a Bus Read operation or inputs a command

or the data to be programmed during a Write Bus

operation.

state. When Reset is at V , the device is in normal

IH

operation. Exiting reset mode the device enters

read array mode, but a negative transition of Chip

Enable or a change of the address is required to

ensure valid data outputs.

V

Supply Voltage. V

provides the power

DD

supply to the internal core of the memory device.

It is the main power supply for all operations

(Read, Program and Erase).

V

Supply Voltage. V

provides the

power supply to the I/O pins and enables all Out-

puts to be powered independently from V . V

DDQ

DD DDQ

can be tied to V or can use a separate supply.

DD

Chip Enable (E). The Chip Enable input acti-

vates the memory control logic, input buffers, de-

coders and sense amplifiers. When Chip Enable is

V

Program Supply Voltage. V

is both a

PP

control input and a power supply pin. The two

functions are selected by the voltage range ap-

plied to the pin. The Supply Voltage V and the

DD

Program Supply Voltage V

any order.

at V and Reset is at V the device is in active

IL

IH

mode. When Chip Enable is at V the memory is

can be applied in

PP

IH

deselected, the outputs are high impedance and

the power consumption is reduced to the stand-by

level.

If V is kept in a low voltage range (0V to 3.6V)

PP

V

is seen as a control input. In this case a volt-

PP

Output Enable (G). The Output Enable controls

data outputs during the Bus Read operation of the

memory.

Write Enable (W). The Write Enable controls the

Bus Write operation of the memory’s Command

Interface. The data and address inputs are latched

on the rising edge of Chip Enable, E, or Write En-

able, W, whichever occurs first.

age lower than V

gives an absolute protection

PPLK

against program or erase, while V > V

en-

PP1

PP

ables these functions (see Table 15, DC Charac-

teristics for the relevant values). V is only

PP

sampled at the beginning of a program or erase; a

change in its value after the operation has started

does not have any effect and program or erase op-

erations continue.

If V is in the range 11.4V to 12.6V it acts as a

PP

Write Protect (WP). Write Protect is an input

power supply pin. In this condition V must be

PP

that gives an additional hardware protection for

stable until the Program/Erase algorithm is com-

each block. When Write Protect is at V , the Lock-

IL

pleted (see Table 17 and 18).

Down is enabled and the protection status of the

block cannot be changed. When Write Protect is at

V

Ground. V is the reference for all voltage

SS

V , the Lock-Down is disabled and the block can

measurements.

IH

be locked or unlocked. (refer to Table 7, Read Pro-

Note: Each device in a system should have

tection Register and Protection Register Lock).

V

, V

and V decoupled with a 0.1µF ca-

DD DDQ PP

Reset (RP). The Reset input provides a hard-

pacitor close to the pin. See Figure 8, AC Mea-

surement Load Circuit. The PCB trace widths

ware reset of the memory. When Reset is at V ,

IL

the memory is in reset mode: the outputs are high

impedance and the current consumption is mini-

mized. After Reset all blocks are in the Locked

should be sufficient to carry the required V

program and erase currents.

PP

9/50

M28W160CT, M28W160CB

BUS OPERATIONS

There are six standard bus operations that control

the device. These are Bus Read, Bus Write, Out-

put Disable, Standby, Automatic Standby and Re-

set. See Table 3, Bus Operations, for a summary.

Typically glitches of less than 5ns on Chip Enable

or Write Enable are ignored by the memory and do

not affect bus operations.

See Figures 10 and 11, Write AC Waveforms, and

Tables 17 and 18, Write AC Characteristics, for

details of the timing requirements.

Output Disable. The data outputs are high im-

pedance when the Output Enable is at V .

IH

Standby. Standby disables most of the internal

circuitry allowing a substantial reduction of the cur-

rent consumption. The memory is in stand-by

Read. Read Bus operations are used to output

the contents of the Memory Array, the Electronic

Signature, the Status Register and the Common

Flash Interface. Both Chip Enable and Output En-

when Chip Enable is at V and the device is in

IH

read mode. The power consumption is reduced to

the stand-by level and the outputs are set to high

impedance, independently from the Output Enable

or Write Enable inputs. If Chip Enable switches to

able must be at V in order to perform a read op-

IL

eration. The Chip Enable input should be used to

enable the device. Output Enable should be used

to gate data onto the output. The data read de-

pends on the previous command written to the

memory (see Command Interface section). See

Figure 9, Read Mode AC Waveforms, and Table

16, Read AC Characteristics, for details of when

the output becomes valid.

V

during a program or erase operation, the de-

IH

vice enters Standby mode when finished.

Automatic Standby. Automatic Standby pro-

vides a low power consumption state during Read

mode. Following a read operation, the device en-

ters Automatic Standby after 150ns of bus inactiv-

ity even if Chip Enable is Low, V , and the supply

IL

Read mode is the default state of the device when

exiting Reset or after power-up.

current is reduced to I

. The data Inputs/Out-

DD1

puts will still output data if a bus Read operation is

in progress.

Write. Bus Write operations write Commands to

the memory or latch Input Data to be programmed.

A write operation is initiated when Chip Enable

Reset. During Reset mode when Output Enable

is Low, V , the memory is deselected and the out-

IL

and Write Enable are at V with Output Enable at

puts are high impedance. The memory is in Reset

IL

V . Commands, Input Data and Addresses are

mode when Reset is at V . The power consump-

IH

IL

latched on the rising edge of Write Enable or Chip

tion is reduced to the Standby level, independently

Enable, whichever occurs first.

from the Chip Enable, Output Enable or Write En-

able inputs. If Reset is pulled to V during a Pro-

SS

gram or Erase, this operation is aborted and the

memory content is no longer valid.

Table 3. Bus Operations

V

Operation

Bus Read

E

G

W

RP

WP

X

DQ0-DQ15

Data Output

Data Input

Hi-Z

PP

V

Don't Care

V or V

DD

IL

IH

V

Bus Write

Output Disable

Standby

X

IL

IH

PPH

V

X

Don't Care

IH

V

X

Hi-Z

IH

V

Reset

X

Hi-Z

IL

Note: X = V or V , V = 12V 5%.

PPH

IL

IH

10/50

M28W160CT, M28W160CB

COMMAND INTERFACE

All Bus Write operations to the memory are inter-

preted by the Command Interface. Commands

consist of one or more sequential Bus Write oper-

ations. An internal Program/Erase Controller han-

dles all timings and verifies the correct execution

of the Program and Erase commands. The Pro-

gram/Erase Controller provides a Status Register

whose output may be read at any time during, to

monitor the progress of the operation, or the Pro-

gram/Erase states. See Appendix 21, Table 32,

Write State Machine Current/Next, for a summary

of the Command Interface.

cations to automatically match their interface to

the characteristics of the device. One Bus Write

cycle is required to issue the Read Query Com-

mand. Once the command is issued subsequent

Bus Read operations read from the Common

Flash Interface Memory Area. See Appendix B,

Common Flash Interface, Tables 26, 27, 28, 29,

30 and 31 for details on the information contained

in the Common Flash Interface memory area.

Block Erase Command

The Block Erase command can be used to erase

a block. It sets all the bits within the selected block

to ’1’. All previous data in the block is lost. If the

block is protected then the Erase operation will

abort, the data in the block will not be changed and

the Status Register will output the error.

Two Bus Write cycles are required to issue the

command.

■ The first bus cycle sets up the Erase command.

■ The second latches the block address in the

internal state machine and starts the Program/

Erase Controller.

If the second bus cycle is not Write Erase Confirm

(D0h), Status Register bits b4 and b5 are set and

the command aborts.

The Command Interface is reset to Read mode

when power is first applied, when exiting from Re-

set or whenever V

is lower than V

. Com-

LKO

DD

mand sequences must be followed exactly. Any

invalid combination of commands will reset the de-

vice to Read mode. Refer to Table 4, Commands,

in conjunction with the text descriptions below.

Read Memory Array Command

The Read command returns the memory to its

Read mode. One Bus Write cycle is required to is-

sue the Read Memory Array command and return

the memory to Read mode. Subsequent read op-

erations will read the addressed location and out-

put the data. When a device Reset occurs, the

memory defaults to Read mode.

Erase aborts if Reset turns to V . As data integrity

IL

cannot be guaranteed when the Erase operation is

Read Status Register Command

aborted, the block must be erased again.

The Status Register indicates when a program or

erase operation is complete and the success or

failure of the operation itself. Issue a Read Status

Register command to read the Status Register’s

contents. Subsequent Bus Read operations read

the Status Register at any address, until another

command is issued. See Table 11, Status Register

Bits, for details on the definitions of the bits.

The Read Status Register command may be is-

sued at any time, even during a Program/Erase

operation. Any Read attempt during a Program/

Erase operation will automatically output the con-

tent of the Status Register.

During Erase operations the memory will accept

the Read Status Register command and the Pro-

gram/Erase Suspend command, all other com-

mands will be ignored. Typical Erase times are

given in Table 8, Program, Erase Times and Pro-

gram/Erase Endurance Cycles.

See Appendix C, Figure 20, Erase Flowchart and

Pseudo Code, for a suggested flowchart for using

the Erase command.

Program Command

The memory array can be programmed word-by-

word. Two bus write cycles are required to issue

the Program Command.

Read Electronic Signature Command

The Read Electronic Signature command reads

the Manufacturer and Device Codes and the Block

Locking Status, or the Protection Register.

The Read Electronic Signature command consists

of one write cycle, a subsequent read will output

the Manufacturer Code, the Device Code, the

Block Lock and Lock-Down Status, or the Protec-

tion and Lock Register. See Tables 5, 6 and 7 for

the valid address.

■ The first bus cycle sets up the Program

command.

■ The second latches the Address and the Data to

be written and starts the Program/Erase

Controller.

During Program operations the memory will ac-

cept the Read Status Register command and the

Program/Erase Suspend command. Typical Pro-

gram times are given in Table 8, Program, Erase

Times and Program/Erase Endurance Cycles.

Read CFI Query Command

The Read Query Command is used to read data

from the Common Flash Interface (CFI) Memory

Area, allowing programming equipment or appli-

Programming aborts if Reset goes to V . As data

IL

integrity cannot be guaranteed when the program

operation is aborted, the block containing the

11/50

M28W160CT, M28W160CB

memory location must be erased and repro-

grammed.

See Appendix C, Figure 17, Program Flowchart

and Pseudo Code, for the flowchart for using the

Program command.

cepted. The block being erased may be protected

by issuing the Block Protect, Block Lock or Protec-

tion Program commands. When the Program/

Erase Resume command is issued the operation

will complete. Only the blocks not being erased

may be read or programmed correctly.

Double Word Program Command

During a Program/Erase Suspend, the device can

be placed in a pseudo-standby mode by taking

This feature is offered to improve the programming

throughput, writing a page of two adjacent words

in parallel.The two words must differ only for the

address A0. Programming should not be attempt-

Chip Enable to V . Program/Erase is aborted if

IH

Reset turns to V .

IL

See Appendix C, Figure 19, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

21, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Suspend command.

ed when V is not at V

. The command can be

PPH

PP

executed if V is below V

but the result is not

PPH

PP

guaranteed.

Three bus write cycles are necessary to issue the

Double Word Program command.

Program/Erase Resume Command

■ The first bus cycle sets up the Double Word

The Program/Erase Resume command can be

used to restart the Program/Erase Controller after

a Program/Erase Suspend operation has paused

it. One Bus Write cycle is required to issue the

command. Once the command is issued subse-

quent Bus Read operations read the Status Reg-

ister.

Program Command.

■ The second bus cycle latches the Address and

the Data of the first word to be written.

■ The third bus cycle latches the Address and the

Data of the second word to be written and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started. Program-

See Appendix C, Figure 19, Program Suspend &

Resume Flowchart and Pseudo Code, and Figure

21, Erase Suspend & Resume Flowchart and

Pseudo Code for flowcharts for using the Program/

Erase Resume command.

ming aborts if Reset goes to V . As data integrity

IL

cannot be guaranteed when the program opera-

tion is aborted, the block containing the memory

location must be erased and reprogrammed.

See Appendix C, Figure 18, Double Word Pro-

gram Flowchart and Pseudo Code, for the flow-

chart for using the Double Word Program

command.

Protection Register Program Command

The Protection Register Program command is

used to Program the 64 bit user One-Time-Pro-

grammable (OTP) segment of the Protection Reg-

ister. The segment is programmed 16 bits at a

time. When shipped all bits in the segment are set

to ‘1’. The user can only program the bits to ‘0’.

Clear Status Register Command

The Clear Status Register command can be used

to reset bits 1, 3, 4 and 5 in the Status Register to

‘0’. One bus write cycle is required to issue the

Clear Status Register command.

The bits in the Status Register do not automatical-

ly return to ‘0’ when a new Program or Erase com-

mand is issued. The error bits in the Status

Register should be cleared before attempting a

new Program or Erase command.

Two write cycles are required to issue the Protec-

tion Register Program command.

■ The first bus cycle sets up the Protection

Register Program command.

■ The second latches the Address and the Data to

be written to the Protection Register and starts

the Program/Erase Controller.

Read operations output the Status Register con-

tent after the programming has started.

The segment can be protected by programming bit

1 of the Protection Lock Register. Bit 1 of the Pro-

tection Lock Register protects bit 2 of the Protec-

tion Lock Register. Programming bit 2 of the

Protection Lock Register will result in a permanent

protection of the Security Block (see Figure 6, Se-

curity Block and Protection Register Memory

Map). Attempting to program a previously protect-

ed Protection Register will result in a Status Reg-

ister error. The protection of the Protection

Register and/or the Security Block is not revers-

ible.

Program/Erase Suspend Command

The Program/Erase Suspend command is used to

pause a Program or Erase operation. One bus

write cycle is required to issue the Program/Erase

command and pause the Program/Erase control-

ler.

During Program/Erase Suspend the Command In-

terface will accept the Program/Erase Resume,

Read Array, Read Status Register, Read Electron-

ic Signature and Read CFI Query commands. Ad-

ditionally, if the suspend operation was Erase then

the Program, Block Lock, Block Lock-Down or

Protection Program commands will also be ac-

12/50

M28W160CT, M28W160CB

The Protection Register Program cannot be sus-

pended. See Appendix C, Figure 23, Protection

Register Program Flowchart and Pseudo Code,

for the flowchart for using the Protection Register

Program command.

■ The first bus cycle sets up the Block Unlock

command.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Unlock command. Refer to the section,

Block Locking, for a detailed explanation.

Block Lock Command

The Block Lock command is used to lock a block

and prevent Program or Erase operations from

changing the data in it. All blocks are locked at

power-up or reset.

Two Bus Write cycles are required to issue the

Block Lock command.

Block Lock-Down Command

A locked block cannot be Programmed or Erased,

or have its protection status changed when WP is

low, V . When WP is high, V the Lock-Down

IL IH,

function is disabled and the locked blocks can be

individually unlocked by the Block Unlock com-

mand.

■ The first bus cycle sets up the Block Lock

command.

■ The second Bus Write cycle latches the block

address.

Two Bus Write cycles are required to issue the

Block Lock-Down command.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Table. 10 shows the protection status after issuing

a Block Lock command.

■ The first bus cycle sets up the Block Lock

command.

The Block Lock bits are volatile, once set they re-

main set until a hardware reset or power-down/

power-up. They are cleared by a Blocks Unlock

command. Refer to the section, Block Locking, for

a detailed explanation.

■ The second Bus Write cycle latches the block

address.

The lock status can be monitored for each block

using the Read Electronic Signature command.

Locked-Down blocks revert to the locked (and not

locked-down) state when the device is reset on

power-down. Table. 10 shows the protection sta-

tus after issuing a Block Lock-Down command.

Refer to the section, Block Locking, for a detailed

explanation.

Block Unlock Command

The Blocks Unlock command is used to unlock a

block, allowing the block to be programmed or

erased. Two Bus Write cycles are required to is-

sue the Blocks Unlock command.

13/50

M28W160CT, M28W160CB

Table 4. Commands

Bus Write Operations

2nd Cycle

No. of

Commands

1st Cycle

3nd Cycle

Addr

Cycles

Bus

Op.

Bus

Op.

Bus

Op.

Addr Data

Addr

Data

Read

Addr

Read Memory Array

Read Status Register

1+

Write

X

FFh

70h

Data

Read

Status

Register

X

Signature

Addr ⁽²⁾

Read Electronic Signature

Read CFI Query

Erase

1+

2

Write

X

90h

98h

20h

Signature

Query

D0h

Read

Write

CFI Addr

Block

Addr

40h or

10h

Data

Input

Program

2

3

Write

X

Write

Addr

Data

Input

Data

Input

Double Word Program⁽³⁾

30h

Addr 1

Write

Addr 2

Clear Status Register

Program/Erase Suspend

Program/Erase Resume

1

Write

X

50h

B0h

D0h

Block

Address

Block Lock

2

Write

X

60h

C0h

Write

01h

D0h

2Fh

Block

Address

Block Unlock

Block Lock-Down

Block

Address

Protection Register

Program

Data

Input

Address

Note: 1. X = Don't Care.

2. The signature addresses are listed in Tables 5, 6 and 7.

3. Addr 1 and Addr 2 must be consecutive Addresses differing only for A0.

Table 5. Read Electronic Signature

Code

Device

E

G

W

A0

A1

A2-A7

A8-A19

DQ0-DQ7

DQ8-DQ15

Manufacture.

Code

V

0

Don't Care

20h

00h

IL

IH

IL

V

M28W160CT

M28W160CB

0

Don't Care

CEh

CFh

88h

IL

IH

IL

Device Code

V

IH

IL

Note:

RP = V .

IH

14/50

M28W160CT, M28W160CB

Table 6. Read Block Lock Signature

Block Status

E

G

W

A0

A1 A2-A7

A8-A11

A12-A19

DQ0 DQ1 DQ2-DQ15

V

Locked Block

0

Don't Care Block Address

1

0

00h

IL

IH

IL

IH

V

Unlocked Block

IL

Locked-Down

Block

(1)

V

0

Don't Care Block Address

1

00h

IL

IH

IL

IH

X

Note: 1. A Locked-Down Block can be locked "DQ0 = 1" or unlocked "DQ0 = 0"; see Block Locking section.

Table 7. Read Protection Register and Lock Register

Word

E

G

W

A0-A7

A8-A19

DQ0

DQ1

DQ2

DQ3-DQ7 DQ8-DQ15

OTP Prot.

data

Security

prot. data

V

Lock

80h Don't Care

0

00h

IL

IH

V

Unique ID 0

Unique ID 1

Unique ID 2

Unique ID 3

OTP 0

81h Don't Care

82h Don't Care

83h Don't Care

84h Don't Care

ID data

IL

IH

ID data

85h Don't Care OTP data

86h Don't Care OTP data

87h Don't Care OTP data

88h Don't Care OTP data

OTP data

OTP data OTP data OTP data

OTP 1

OTP 2

OTP 3

Table 8. Program, Erase Times and Program/Erase Endurance Cycles

M28W160C

Parameter

Test Conditions

Unit

Min

Typ

10

Max

200

5

V

= V

DD

Word Program

µs

PP

V

= 12V 5%

= V

Double Word Program

Main Block Program

10

µs

PP

0.16

0.32

0.02

0.04

1

s

PP

V

5

s

PP

DD

V

= 12V 5%

= V

4

s

PP

Parameter Block Program

Main Block Erase

V

4

s

PP

DD

= 12V 5%

= V

10

s

PP

V

1

s

PP

DD

= 12V 5%

= V

0.8

PP

Parameter Block Erase

V

s

PP

DD

Program/Erase Cycles (per Block)

Data Retention

100,000

20

cycles

years

15/50

M28W160CT, M28W160CB

BLOCK LOCKING

The M28W160C features an instant, individual

block locking scheme that allows any block to be

locked or unlocked with no latency. This locking

scheme has three levels of protection.

software commands. A locked block can be un-

locked by issuing the Unlock command.

Lock-Down State

Blocks that are Locked-Down (state (0,1,x))are

protected from program and erase operations (as

for Locked blocks) but their lock status cannot be

changed using software commands alone. A

Locked or Unlocked block can be Locked-Down by

issuing the Lock-Down command. Locked-Down

blocks revert to the Locked state when the device

is reset or powered-down.

■ Lock/Unlock - this first level allows software-

only control of block locking.

■ Lock-Down - this second level requires

hardware interaction before locking can be

changed.

■ V ≤V

- the third level offers a complete

PPLK

PP

The Lock-Down function is dependent on the WP

hardware protection against program and erase

on all blocks.

input pin. When WP=0 (V ), the blocks in the

IL

Lock-Down state (0,1,x) are protected from pro-

gram, erase and protection status changes. When

The lock status of each block can be set to

Locked, Unlocked, and Lock-Down. Table 10, de-

fines all of the possible protection states (WP,

DQ1, DQ0), and Appendix C, Figure 22, shows a

flowchart for the locking operations.

WP=1 (V ) the Lock-Down function is disabled

IH

(1,1,1) and Locked-Down blocks can be individu-

ally unlocked to the (1,1,0) state by issuing the

software command, where they can be erased and

programmed. These blocks can then be relocked

(1,1,1) and unlocked (1,1,0) as desired while WP

remains high. When WP is low , blocks that were

previously Locked-Down return to the Lock-Down

state (0,1,x) regardless of any changes made

while WP was high. Device reset or power-down

resets all blocks , including those in Lock-Down, to

the Locked state.

Reading a Block’s Lock Status

The lock status of every block can be read in the

Read Electronic Signature mode of the device. To

enter this mode write 90h to the device. Subse-

quent reads at the address specified in Table 6,

will output the lock status of that block. The lock

status is represented by DQ0 and DQ1. DQ0 indi-

cates the Block Lock/Unlock status and is set by

the Lock command and cleared by the Unlock

command. It is also automatically set when enter-

ing Lock-Down. DQ1 indicates the Lock-Down sta-

tus and is set by the Lock-Down command. It

cannot be cleared by software, only by a hardware

reset or power-down.

Locking Operations During Erase Suspend

Changes to block lock status can be performed

during an erase suspend by using the standard

locking command sequences to unlock, lock or

lock-down a block. This is useful in the case when

another block needs to be updated while an erase

operation is in progress.

To change block locking during an erase opera-

tion, first write the Erase Suspend command, then

check the status register until it indicates that the

erase operation has been suspended. Next write

the desired Lock command sequence to a block

and the protection status will be changed. After

completing any desired lock, read, or program op-

erations, resume the erase operation with the

Erase Resume command.

The following sections explain the operation of the

locking system.

Locked State

The default status of all blocks on power-up or af-

ter a hardware reset is Locked (states (0,0,1) or

(1,0,1)). Locked blocks are fully protected from

any program or erase. Any program or erase oper-

ations attempted on a locked block will return an

error in the Status Register. The Status of a

Locked block can be changed to Unlocked or

Lock-Down using the appropriate software com-

mands. An Unlocked block can be Locked by issu-

ing the Lock command.

If a block is locked or locked-down during an erase

suspend of the same block, the locking status bits

will be changed immediately, but when the erase

is resumed, the erase operation will complete.

Unlocked State

Locking operations cannot be performed during a

program suspend. Refer to Appendix D, Com-

mand Interface and Program/Erase Controller

State, for detailed information on which com-

mands are valid during erase suspend.

Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)),

can be programmed or erased. All unlocked

blocks return to the Locked state after a hardware

reset or when the device is powered-down. The

status of an unlocked block can be changed to

Locked or Locked-Down using the appropriate

16/50

M28W160CT, M28W160CB

Table 9. Block Lock Status

Item

Address

Data

Block Lock Configuration

LOCK

Block is Unlocked

Block is Locked

DQ0=0

DQ0=1

DQ1=1

xx002

Block is Locked-Down

Table 10. Protection Status

Current

Protection Status

(WP, DQ1, DQ0)

(1)

Next Protection Status

(WP, DQ1, DQ0)

(1)

After

Block Lock

Command

After

Block Unlock

Command

After Block

Lock-Down

Command

Program/Erase

After

WP transition

Current State

Allowed

1,0,0

yes

no

1,0,1

1,1,1

0,0,1

1,0,0

1,1,0

0,0,0

1,1,1

0,1,1

0,0,0

0,0,1

0,1,1

1,0,0

1,0,1

(2)

1,0,1

1,1,0

1,1,1

0,0,0

yes

no

yes

no

(2)

0,0,1

(3)

0,1,1

no

0,1,1

1,1,1 or 1,1,0

Note: 1. The protection status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block)

as read in the Read Electronic Signature command with A1 = V and A0 = V .

IH

IL

2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status.

3. A WP transition to V on a locked block will restore the previous DQ0 value, giving a 111 or 110.

IH

17/50

M28W160CT, M28W160CB

STATUS REGISTER

The Status Register provides information on the

current or previous Program or Erase operation.

The various bits convey information and errors on

the operation. To read the Status register the

Read Status Register command can be issued, re-

fer to Read Status Register Command section. To

output the contents, the Status Register is latched

on the falling edge of the Chip Enable or Output

Enable signals, and can be read until Chip Enable

When a Program/Erase Resume command is is-

sued the Erase Suspend Status bit returns Low.

Erase Status (Bit 5). The Erase Status bit can be

used to identify if the memory has failed to verify

that the block has erased correctly. When the

Erase Status bit is High (set to ‘1’), the Program/

Erase Controller has applied the maximum num-

ber of pulses to the block and still failed to verify

that the block has erased correctly. The Erase Sta-

tus bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

or Output Enable returns to V . Either Chip En-

IH

able or Output Enable must be toggled to update

the latched data.

Bus Read operations from any address always

read the Status Register during Program and

Erase operations.

The bits in the Status Register are summarized in

Table 11, Status Register Bits. Refer to Table 11

in conjunction with the following text descriptions.

Program/Erase Controller Status (Bit 7). The Pro-

gram/Erase Controller Status bit indicates whether

the Program/Erase Controller is active or inactive.

When the Program/Erase Controller Status bit is

Low (set to ‘0’), the Program/Erase Controller is

active; when the bit is High (set to ‘1’), the Pro-

gram/Erase Controller is inactive, and the device

is ready to process a new command.

Once set High, the Erase Status bit can only be re-

set Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

Program Status (Bit 4). The Program Status bit

is used to identify a Program failure. When the

Program Status bit is High (set to ‘1’), the Pro-

gram/Erase Controller has applied the maximum

number of pulses to the byte and still failed to ver-

ify that it has programmed correctly. The Program

Status bit should be read once the Program/Erase

Controller Status bit is High (Program/Erase Con-

troller inactive).

The Program/Erase Controller Status is Low im-

mediately after a Program/Erase Suspend com-

mand is issued until the Program/Erase Controller

pauses. After the Program/Erase Controller paus-

es the bit is High .

Once set High, the Program Status bit can only be

reset Low by a Clear Status Register command or

a hardware reset. If set High it should be reset be-

fore a new command is issued, otherwise the new

command will appear to fail.

During Program, Erase, operations the Program/

Erase Controller Status bit can be polled to find the

end of the operation. Other bits in the Status Reg-

ister should not be tested until the Program/Erase

Controller completes the operation and the bit is

High.

V

Status (Bit 3). The V

Status bit can be

PP

used to identify an invalid voltage on the V pin

PP

during Program and Erase operations. The V

PP

pin is only sampled at the beginning of a Program

or Erase operation. Indeterminate results can oc-

cur if V becomes invalid during an operation.

PP

After the Program/Erase Controller completes its

When the V Status bit is Low (set to ‘0’), the volt-

PP

operation the Erase Status, Program Status, V

age on the V pin was sampled at a valid voltage;

PP

Status and Block Lock Status bits should be tested

for errors.

when the V Status bit is High (set to ‘1’), the V

PP PP

pin has a voltage that is below the V Lockout

PP

Voltage, V

, the memory is protected and Pro-

gram and Erase operations cannot be performed.

PPLK

Erase Suspend Status (Bit 6). The Erase Sus-

pend Status bit indicates that an Erase operation

has been suspended or is going to be suspended.

When the Erase Suspend Status bit is High (set to

‘1’), a Program/Erase Suspend command has

been issued and the memory is waiting for a Pro-

gram/Erase Resume command.

Once set High, the V Status bit can only be reset

PP

Low by a Clear Status Register command or a

hardware reset. If set High it should be reset be-

fore a new Program or Erase command is issued,

otherwise the new command will appear to fail.

The Erase Suspend Status should only be consid-

ered valid when the Program/Erase Controller Sta-

tus bit is High (Program/Erase Controller inactive).

Bit 7 is set within 30µs of the Program/Erase Sus-

pend command being issued therefore the memo-

ry may still complete the operation rather than

entering the Suspend mode.

Program Suspend Status (Bit 2). The Program

Suspend Status bit indicates that a Program oper-

ation has been suspended. When the Program

Suspend Status bit is High (set to ‘1’), a Program/

Erase Suspend command has been issued and

the memory is waiting for a Program/Erase Re-

sume command. The Program Suspend Status

should only be considered valid when the Pro-

18/50

M28W160CT, M28W160CB

gram/Erase Controller Status bit is High (Program/

Erase Controller inactive). Bit 2 is set within 5µs of

the Program/Erase Suspend command being is-

sued therefore the memory may still complete the

operation rather than entering the Suspend mode.

When a Program/Erase Resume command is is-

sued the Program Suspend Status bit returns Low.

Block Protection Status (Bit 1). The Block Pro-

tection Status bit can be used to identify if a Pro-

gram or Erase operation has tried to modify the

contents of a locked block.

When the Block Protection Status bit is High (set

to ‘1’), a Program or Erase operation has been at-

tempted on a locked block.

Once set High, the Block Protection Status bit can

only be reset Low by a Clear Status Register com-

mand or a hardware reset. If set High it should be

reset before a new command is issued, otherwise

the new command will appear to fail.

Reserved (Bit 0). Bit 0 of the Status Register is

reserved. Its value must be masked.

Note: Refer to Appendix C, Flowcharts and

Pseudo Codes, for using the Status Register.

Table 11. Status Register Bits

Bit

Name

Logic Level

Definition

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

'1'

'0'

Ready

7

P/E.C. Status

Busy

Suspended

6

5

4

3

2

Erase Suspend Status

Erase Status

In progress or Completed

Erase Error

Erase Success

Program Error

Program Status

Program Success

V

Invalid, Abort

OK

PP

V

Status

PP

Suspended

Program Suspend Status

In Progress or Completed

Program/Erase on protected Block, Abort

No operation to protected blocks

1

0

Block Protection Status

Reserved

Note: Logic level '1' is High, '0' is Low.

19/50

M28W160CT, M28W160CB

MAXIMUM RATING

Stressing the device above the rating listed in the

Absolute Maximum Ratings table may cause per-

manent damage to the device. These are stress

ratings only and operation of the device at these or

any other conditions above those indicated in the

Operating sections of this specification is not im-

plied. Exposure to Absolute Maximum Rating con-

ditions for extended periods may affect device

reliability. Refer also to the Numonyx SURE Pro-

gram and other relevant quality documents.

Table 12. Absolute Maximum Ratings

Value

Symbol

Parameter

Unit

Min

−40

−55

−0.6

Max

85

(1)

T

A

°C

V

Ambient Operating Temperature

Temperature Under Bias

Storage Temperature

T

125

155

BIAS

T

STG

(2,3)

V

+0.6

DDQ

Input or Output Voltage

Supply Voltage

V

IO

−0.6

4.1

13

V

, V

DD DDQ

Program Voltage

V

PP

Note: 1. T depends on the temperature range.

A

2. The minimum voltage may undershoot to −2V during transition and for less than 20ns during transitions.

3. The maximum voltage may overshoot to Vcc + 2V during transition and for less than 20ns during transitions.

20/50

M28W160CT, M28W160CB

DC AND AC PARAMETERS

This section summarizes the operating and mea-

surement conditions, and the DC and AC charac-

teristics of the device. The parameters in the DC

and AC characteristics Tables that follow, are de-

rived from tests performed under the Measure-

ment Conditions summarized in Table 13,

Operating and AC Measurement Conditions. De-

signers should check that the operating conditions

in their circuit match the measurement conditions

when relying on the quoted parameters.

Table 13. Operating and AC Measurement Conditions

M28W160CT, M28W160CB

70

85

90

100

Parameter

Supply Voltage

Units

Min

Max

Min

Max

Min

Max

Min

Max

V

2.7

3.6

2.7

3.6

2.7

3.6

2.7

3.6

V

DD

2.7

3.6

85

2.7

3.6

85

2.7

3.6

85

1.65

– 40

3.6

85

Supply Voltage (V

≤V

)

DD

DDQ

Ambient Operating Temperature

– 40

°C

pF

ns

V

Load Capacitance (C )

50

L

Input Rise and Fall Times

Input Pulse Voltages

5

0 to V

DDQ

Input and Output Timing Ref.

Voltages

V

/2

DDQ

V

/2

V

/2

DDQ

V

/2

DDQ

V

DDQ

Figure 7. AC Measurement I/O Waveform

Figure 8. AC Measurement Load Circuit

V

DDQ

V

DDQ

V

/2

DDQ

V

DDQ

V

0V

DD

25kΩ

AI00610

DEVICE

UNDER

TEST

C

L

25kΩ

0.1µF

C

includes JIG capacitance

AI00609C

L

Table 14. Capacitance

Symbol

Parameter

Input Capacitance

Output Capacitance

Test Condition

Min

Max

6

Unit

pF

C

V

= 0V

IN

C

V

OUT

12

pF

OUT

Note: Sampled only, not 100% tested.

21/50

M28W160CT, M28W160CB

Table 15. DC Characteristics

Symbol

Parameter

Input Leakage Current

Output Leakage Current

Supply Current (Read)

Test Condition

Min

Typ

Max

1

Unit

µA

I

0V≤V ≤V

DDQ

LI

IN

I

0V≤V

≤V

10

20

µA

LO

OUT DDQ

I

E = V , G = V , f = 5MHz

SS IH

10

15

mA

DD

E = V

RP = V

0.2V,

0.2V

Supply Current (Stand-by or

Automatic Stand-by)

DDQ

I

50

20

50

400

µA

DD1

DDQ

Supply Current

(Reset)

I

RP = V

0.2V

15

10

5

DD2

SS

Program in progress

= 12V 5%

mA

µA

V

PP

I

Supply Current (Program)

Supply Current (Erase)

DD3

Program in progress

= V

V

PP

DD

Erase in progress

= 12V 5%

V

PP

I

DD4

Erase in progress

= V

5

V

PP

DD

E = V

0.2V,

Supply Current

(Program/Erase Suspend)

DDQ

I

DD5

Erase suspended

Program Current

(Read or Stand-by)

I

V

> V

DD

µA

PP

Program Current

(Read or Stand-by)

I

V

≤V

5

µA

PP1

PP

DD

I

RP = V

0.2V

Program in progress

= 12V 5%

Program Current (Reset)

PP2

SS

10

mA

V

PP

I

Program Current (Program)

PP3

Program in progress

= V

5

10

5

µA

mA

µA

V

PP

DD

Erase in progress

= 12V 5%

V

PP

I

Program Current (Erase)

PP4

Erase in progress

= V

V

PP

DD

–0.5

0.4

0.8

V

Input Low Voltage

Input High Voltage

IL

V

≥ 2.7V

DDQ

V

–0.4

V

+0.4

DDQ

V

IH

0.7 V

+0.4

DDQ

I

= 100µA, V = V min,

DD DD

OL

V

Output Low Voltage

Output High Voltage

0.1

V

OL

V

= V

min

DDQ

I

= –100µA, V = V min,

DD DD

OH

V

OH

V

–0.1

DDQ

V

= V

min

DDQ

Program Voltage (Program or

Erase operations)

V

1.65

3.6

PP1

Program Voltage

(Program or Erase

operations)

V

11.4

12.6

V

PPH

Program Voltage

(Program and Erase lock-out)

V

1

2

V

PPLK

V

Supply Voltage (Program

DD

V

LKO

and Erase lock-out)

22/50

M28W160CT, M28W160CB

Figure 9. Read Mode AC Waveforms

tAVAV

VALID

A0-A19

tAVQV

tAXQX

E

tELQV

tELQX

tEHQX

tEHQZ

G

tGLQV

tGHQX

tGHQZ

tGLQX

VALID

DQ0-DQ15

ADDR. VALID

CHIP ENABLE

OUTPUTS

ENABLED

DATA VALID

STANDBY

AI03813b

Table 16. Read AC Characteristics

M28W160C

Unit

Symbol

Alt

Parameter

70

85

90

100

t

Address Valid to Next Address Valid

Address Valid to Output Valid

Min

ns

AVAV

RC

t

ACC

Max

Min

Max

Min

Max

Min

AVQV

(1)

t

Address Transition to Output Transition

0

t

OH

AXQX

(1)

t

Chip Enable High to Output Transition

Chip Enable High to Output Hi-Z

ns

t

OH

EHQX

(1)

t

20

70

0

20

85

0

25

90

0

30

100

0

t

HZ

EHQZ

(2)

(1)

(2)

(1)

t

Chip Enable Low to Output Valid

t

CE

ELQV

ELQX

t

Chip Enable Low to Output Transition

Output Enable High to Output Transition

Output Enable High to Output Hi-Z

Output Enable Low to Output Valid

Output Enable Low to Output Transition

LZ

t

0

t

OH

GHQX

t

20

0

20

0

25

30

0

30

35

0

t

DF

GHQZ

t

OE

GLQV

t

OLZ

GLQX

Note: 1. Sampled only, not 100% tested.

2. G may be delayed by up to t

- t

after the falling edge of E without increasing t

.

ELQV GLQV

ELQV

23/50

M28W160CT, M28W160CB

Figure 10. Write AC Waveforms, Write Enable Controlled

24/50

M28W160CT, M28W160CB

Table 17. Write AC Characteristics, Write Enable Controlled

M28W160C

Unit

Symbol

Alt

Parameter

70

45

0

85

45

0

90

50

0

100

50

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Write Enable High

Data Valid to Write Enable High

Chip Enable Low to Write Enable Low

Chip Enable Low to Output Valid

AVWH

AS

DS

CS

t

50

DVWH

t

0

ELWL

t

70

85

90

100

ELQV

(1,2)

Output Valid to V Low

0

t

PP

QVVPL

t

Output Valid to Write Protect Low

QVWPL

(1)

t

V

High to Write Enable High

PP

200

0

200

0

200

0

200

0

t

VPS

VPHWH

t

Write Enable High to Address Transition

Write Enable High to Data Transition

Write Enable High to Chip Enable High

Write Enable High to Chip Enable Low

Write Enable High to Output Enable Low

Write Enable High to Write Enable Low

Write Enable Low to Write Enable High

Write Protect High to Write Enable High

WHAX

WHDX

WHEH

AH

t

0

DH

CH

t

0

t

25

20

25

45

25

20

25

45

30

50

30

50

WHEL

WHGL

WHWL

t

WPH

t

WLWH

WP

t

WPHWH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

25/50

M28W160CT, M28W160CB

Figure 11. Write AC Waveforms, Chip Enable Controlled

26/50

M28W160CT, M28W160CB

Table 18. Write AC Characteristics, Chip Enable Controlled

M28W160C

Unit

Symbol

Alt

Parameter

70

45

0

85

45

0

90

50

0

100

50

0

t

WC

Write Cycle Time

Min

ns

AVAV

t

Address Valid to Chip Enable High

Data Valid to Chip Enable High

AVEH

AS

DS

AH

t

DVEH

t

Chip Enable High to Address Transition Min

EHAX

t

Chip Enable High to Data Transition

Chip Enable High to Chip Enable Low

Min

0

EHDX

DH

t

CPH

25

30

EHEL

Chip Enable High to Output Enable

Low

t

Min

25

30

ns

EHGL

t

WH

Chip Enable High to Write Enable High Min

0

45

70

0

45

85

0

50

90

0

50

100

0

ns

EHWH

t

CP

Chip Enable Low to Chip Enable High

Chip Enable Low to Output Valid

Min

ELEH

t

ELQV

(1,2)

Output Valid to V Low

t

PP

QVVPL

t

Data Valid to Write Protect Low

0

QVWPL

(1)

t

V

High to Chip Enable High

PP

200

0

200

0

200

0

200

0

t

VPS

VPHEH

t

CS

Write Enable Low to Chip Enable Low

WLEL

t

Write Protect High to Chip Enable High Min

45

50

WPHEH

Note: 1. Sampled only, not 100% tested.

2. Applicable if V is seen as a logic input (V < 3.6V).

PP

27/50

M28W160CT, M28W160CB

Figure 12. Power-Up and Reset AC Waveforms

W, E, G

tPHWL

tPHEL

tPHGL

tPHWL

tPHEL

tPHGL

RP

tVDHPH

tPLPH

Reset

VDD, VDDQ

Power-Up

AI03537b

Table 19. Power-Up and Reset AC Characteristics

M28W160C

Symbol

Parameter

Test Condition

Unit

70

85

90

100

During

Program

and Erase

t

PHWL

Min

50

µs

Reset High to Write Enable Low, Chip

Enable Low, Output Enable Low

t

PHEL

PHGL

others

Min

30

ns

(1,2)

(3)

Reset Low to Reset High

100

t

PLPH

Supply Voltages High to Reset High

Min

50

µs

t

VDHPH

Note: 1. The device Reset is possible but not guaranteed if t

2. Sampled only, not 100% tested.

< 100ns.

PLPH

3. It is important to assert RP in order to allow proper CPU initialization during power up or reset.

28/50

M28W160CT, M28W160CB

PACKAGE MECHANICAL

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Outline

1

48

e

D1

B

L1

24

25

A2

A

E1

E

A1

α

L

DIE

C

CP

TSOP-G

Note: Drawing is not to scale.

Table 20. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

1.200

0.150

1.050

0.270

0.210

0.080

12.100

20.200

18.500

–

Typ

Max

A

A1

A2

B

0.0472

0.0059

0.0413

0.0106

0.0083

0.0031

0.4764

0.7953

0.7283

–

0.100

1.000

0.220

0.050

0.950

0.170

0.100

0.0039

0.0394

0.0087

0.0020

0.0374

0.0067

0.0039

C

CP

D1

E

12.000

20.000

18.400

0.500

0.600

0.800

3

11.900

19.800

18.300

–

0.4724

0.7874

0.7244

0.0197

0.0236

0.0315

3

0.4685

0.7795

0.7205

–

E1

e

L

0.500

0.700

0.0197

0.0276

L1

alpha

0

5

0

5

Note: Drawing is not to scale

29/50

M28W160CT, M28W160CB

Figure 14. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Bottom View Package Outline

D

D1

FD

SD

FE

E1

SE

E

e

ddd

BALL "A1"

e

b

A

A2

A1

BGA-Z13

Drawing is not to scale.

Table 21. TFBGA46 6.39x6.37mm - 8x6 ball array, 0.75mm pitch, Package Mechanical Data

millimeters

Min

inches

Min

Symbol

Typ

Max

Typ

Max

A

A1

A2

b

1.200

0.0472

0.200

0.0079

1.000

0.0394

0.400

6.390

5.250

0.350

6.290

–

0.450

0.0157

0.2516

0.2067

0.0138

0.2476

–

0.0177

D

6.490

0.2555

D1

ddd

E

–

0.100

0.0039

6.370

0.750

3.750

0.570

1.310

0.375

6.270

6.470

0.2508

0.0295

0.1476

0.0224

0.0516

0.0148

0.2469

0.2547

e

–

E1

FD

FE

SD

SE

30/50

M28W160CT, M28W160CB

Figure 15. TFBGA46 Daisy Chain - Package Connections (Top view through package)

1

2

3

4

5

6

7

8

A

B

C

D

E

F

AI03298

Figure 16. TFBGA46 Daisy Chain - PCB Connections proposal (Top view through package)

1

2

3

4

5

6

7

8

START

POINT

A

B

C

D

E

F

END

POINT

AI3299

31/50

M28W160CT, M28W160CB

PART NUMBERING

Table 22. Ordering Information Scheme

Example:

M28W160CT

90

N

6

T

Device Type

M28

Operating Voltage

W = V = 2.7V to 3.6V; V

= 1.65V to 3.6V

DDQ

DD

Device Function

160C = 16 Mbit (1 Mb x16), Boot Block

Array Matrix

T = Top Boot

B = Bottom Boot

Speed

70 = 70 ns

85 = 85 ns

90 = 90 ns

100 = 100 ns

Package

N = TSOP48: 12 x 20 mm

ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Temperature Range

1 = 0 to 70 °C

6 = –40 to 85 °C

Option

Blank = Standard Packing

(1)

T = Tape & Reel Packing

(2)

S = Tape & Reel Packing

E = ECOPACK Package, Standard Packing

(1)

F = ECOPACK Package, Tape & Reel Packing

(2)

U = ECOPACK Package, Tape & Reel Packing

Note: 1. TSOP48 package only.

2. TFBGA46 package only.

32/50

M28W160CT, M28W160CB

Table 23. Daisy Chain Ordering Scheme

Example:

M28W160C

-ZB

T

Device Type

M28W160C

Daisy Chain

-ZB = TFBGA46: 6.39 x 6.37mm, 0.75 mm pitch

Option

S = Tape & Reel Packing

U = ECOPACK Package, Tape & Reel Packing

Note:Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available

options (Speed, Package, etc.) or for further information on any aspect of this device, please contact

the Numonyx Sales Office nearest to you.

33/50

M28W160CT, M28W160CB

APPENDIX A. BLOCK ADDRESS TABLES

Table 24. Top Boot Block Addresses,

M28W160CT

Table 25. Bottom Boot Block Addresses,

M28W160CB

Size

(KWord)

Size

#

Address Range

#

Address Range

(KWord)

32

4

0

4

FF000-FFFFF

FE000-FEFFF

FD000-FDFFF

FC000-FCFFF

FB000-FBFFF

FA000-FAFFF

F9000-F9FFF

F8000-F8FFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

00000-07FFF

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

16

15

14

13

12

11

10

9

F8000-FFFFF

F0000-F7FFF

E8000-EFFFF

E0000-E7FFF

D8000-DFFFF

D0000-D7FFF

C8000-CFFFF

C0000-C7FFF

B8000-BFFFF

B0000-B7FFF

A8000-AFFFF

A0000-A7FFF

98000-9FFFF

90000-97FFF

88000-8FFFF

80000-87FFF

78000-7FFFF

70000-77FFF

68000-6FFFF

60000-67FFF

58000-5FFFF

50000-57FFF

48000-4FFFF

40000-47FFF

38000-3FFFF

30000-37FFF

28000-2FFFF

20000-27FFF

18000-1FFFF

10000-17FFF

08000-0FFFF

07000-07FFF

06000-06FFF

05000-05FFF

04000-04FFF

03000-03FFF

02000-02FFF

01000-01FFF

00000-00FFF

1

4

2

4

3

4

5

4

6

4

7

4

8

32

99

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

8

7

6

4

5

4

3

4

2

4

1

4

0

4

34/50

M28W160CT, M28W160CB

APPENDIX B. COMMON FLASH INTERFACE (CFI)

The Common Flash Interface is a JEDEC ap-

proved, standardized data structure that can be

read from the Flash memory device. It allows a

system software to query the device to determine

various electrical and timing parameters, density

information and functions supported by the mem-

ory. The system can interface easily with the de-

vice, enabling the software to upgrade itself when

necessary.

structure is read from the memory. Tables 26, 27,

28, 29, 30 and 31 show the addresses used to re-

trieve the data.

The CFI data structure also contains a security

area where a 64 bit unique security number is writ-

ten (see Table 31, Security Code area). This area

can be accessed only in Read mode by the final

user. It is impossible to change the security num-

ber after it has been written by Numonyx. Issue a

Read command to return to Read mode.

When the CFI Query Command (RCFI) is issued

the device enters CFI Query mode and the data

Table 26. Query Structure Overview

Offset

00h

Sub-section Name

Description

Reserved for algorithm-specific information

Command set ID and algorithm data offset

Device timing & voltage information

Flash device layout

Reserved

10h

CFI Query Identification String

System Interface Information

Device Geometry Definition

1Bh

27h

Additional information specific to the Primary

Algorithm (optional)

P

A

Primary Algorithm-specific Extended Query table

Alternate Algorithm-specific Extended Query table

Additional information specific to the Alternate

Algorithm (optional)

Note: Query data are always presented on the lowest order data outputs.

Table 27. CFI Query Identification String

Offset

Data

Description

Value

00h

0020h

Manufacturer Code

Device Code

Numonyx

88CEh

88CFh

Top

Bottom

01h

02h-0Fh

10h

reserved Reserved

0051h

"Q"

"R"

"Y"

11h

0052h

0059h

0003h

0000h

0035h

0000h

Query Unique ASCII String "QRY"

12h

13h

Primary Algorithm Command Set and Control Interface ID code 16 bit ID code

defining a specific algorithm

Intel

compatible

14h

15h

Address for Primary Algorithm extended Query table (see Table 29)

P = 35h

NA

16h

17h

Alternate Vendor Command Set and Control Interface ID Code second vendor -

specified algorithm supported (0000h means none exists)

18h

19h

Address for Alternate Algorithm extended Query table

(0000h means none exists)

NA

1Ah

Note: Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.

35/50

M28W160CT, M28W160CB

Table 28. CFI Query System Interface Information

Offset

Data

Description

Value

V

Logic Supply Minimum Program/Erase or Write voltage

DD

PP

1Bh

0027h

2.7V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

Logic Supply Maximum Program/Erase or Write voltage

1Ch

1Dh

1Eh

0036h

00B4h

00C6h

3.6V

11.4V

12.6V

bit 7 to 4

bit 3 to 0

BCD value in volts

BCD value in 100 mV

[Programming] Supply Minimum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

[Programming] Supply Maximum Program/Erase voltage

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

n

1Fh

20h

21h

22h

23h

24h

25h

26h

0004h

000Ah

0000h

0005h

0003h

0000h

16µs

1s

Typical time-out per single word program = 2 µs

n

Typical time-out for Double Word Program = 2 µs

n

Typical time-out per individual block erase = 2 ms

n

NA

Typical time-out for full chip erase = 2 ms

n

512µs

8s

Maximum time-out for word program = 2 times typical

n

Maximum time-out for Double Word Program = 2 times typical

n

Maximum time-out per individual block erase = 2 times typical

n

NA

Maximum time-out for chip erase = 2 times typical

36/50

M28W160CT, M28W160CB

Table 29. Device Geometry Definition

Offset Word

Data

Description

Value

Mode

n

27h

0015h

2 MByte

Device Size = 2 in number of bytes

28h

29h

0001h

0000h

x16

Async.

Flash Device Interface Code description

2Ah

2Bh

0002h

0000h

n

4

2

Maximum number of bytes in multi-byte program or page = 2

Number of Erase Block Regions within the device.

It specifies the number of regions within the device containing contiguous

Erase Blocks of the same size.

2Ch

0002h

2Dh

2Eh

001Eh

0000h

Region 1 Information

Number of identical-size erase block = 001Eh+1

31

64 KByte

8

2Fh

30h

0000h

0001h

Region 1 Information

Block size in Region 1 = 0100h * 256 byte

31h

32h

0007h

0000h

Region 2 Information

Number of identical-size erase block = 0007h+1

33h

34h

0020h

0000h

Region 2 Information

Block size in Region 2 = 0020h * 256 byte

8 KByte

8

2Dh

2Eh

0007h

0000h

Region 1 Information

Number of identical-size erase block = 0007h+1

2Fh

30h

0020h

0000h

Region 1 Information

Block size in Region 1 = 0020h * 256 byte

8 KByte

31

31h

32h

001Eh

0000h

Region 2 Information

Number of identical-size erase block = 001Eh+1

33h

34h

0000h

0001h

Region 2 Information

Block size in Region 2 = 0100h * 256 byte

64 KByte

37/50

M28W160CT, M28W160CB

Table 30. Primary Algorithm-Specific Extended Query Table

Offset

Data

Description

Value

(1)

P = 35h

(P+0)h = 35h

(P+1)h = 36h

(P+2)h = 37h

(P+3)h = 38h

(P+4)h = 39h

(P+5)h = 3Ah

(P+6)h = 3Bh

(P+7)h = 3Ch

(P+8)h = 3Dh

0050h

0052h

0049h

0031h

0030h

0066h

0000h

"P"

"R"

"I"

Primary Algorithm extended Query table unique ASCII string “PRI”

Major version number, ASCII

Minor version number, ASCII

"1"

"0"

Extended Query table contents for Primary Algorithm. Address (P+5)h

contains less significant byte.

bit 0

bit 1

bit 2

bit 3

bit 4

bit 5

bit 6

bit 7

bit 8

Chip Erase supported

(1 = Yes, 0 = No)

Suspend Erase supported

Suspend Program supported

Legacy Lock/Unlock supported

Queued Erase supported

No

Yes

No

Instant individual block locking supported (1 = Yes, 0 = No)

No

Protection bits supported

Page mode read supported

Synchronous read supported

(1 = Yes, 0 = No)

Yes

No

bit 31 to 9 Reserved; undefined bits are ‘0’

No

(P+9)h = 3Eh

0001h

Supported Functions after Suspend

Read Array, Read Status Register and CFI Query are always supported

during Erase or Program operation

bit 0

bit 7 to 1

Program supported after Erase Suspend (1 = Yes, 0 = No)

Reserved; undefined bits are ‘0’

Yes

(P+A)h = 3Fh

(P+B)h = 40h

0003h

0000h

Block Lock Status

Defines which bits in the Block Status Register section of the Query are

implemented.

Address (P+A)h contains less significant byte

bit 0 Block Lock Status Register Lock/Unlock bit active(1 = Yes, 0 = No)

bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No)

bit 15 to 2 Reserved for future use; undefined bits are ‘0’

Yes

(P+C)h = 41h

(P+D)h = 42h

(P+E)h = 43h

0030h

00C0h

0001h

V

Logic Supply Optimum Program/Erase voltage (highest performance)

3V

12V

01

DD

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Supply Optimum Program/Erase voltage

PP

bit 7 to 4

bit 3 to 0

HEX value in volts

BCD value in 100 mV

Number of Protection register fields in JEDEC ID space.

"00h," indicates that 256 protection bytes are available

(P+F)h = 44h

(P+10)h = 45h

(P+11)h = 46h

(P+12)h = 47h

0080h

0000h

0003h

Protection Field 1: Protection Description

80h

00h

This field describes user-available. One Time Programmable (OTP)

Protection register bytes. Some are pre-programmed with device unique

serial numbers. Others are user programmable. Bits 0–15 point to the

Protection register Lock byte, the section’s first byte.

8 Byte

The following bytes are factory pre-programmed and user-programmable.

bit 0 to 7

Lock/bytes JEDEC-plane physical low address

bit 8 to 15

Lock/bytes JEDEC-plane physical high address

n

bit 16 to 23 "n" such that 2 = factory pre-programmed bytes

n

bit 24 to 31 "n" such that 2 = user programmable bytes

(P+13)h = 48h

Reserved

Note: 1. See Table 27, offset 15 for P pointer definition.

38/50

M28W160CT, M28W160CB

Table 31. Security Code Area

Offset

80h

81h

82h

83h

84h

85h

86h

87h

88h

Data

00XX

XXXX

Description

Protection Register Lock

64 bits: unique device number

64 bits: User Programmable OTP

39/50

M28W160CT, M28W160CB

APPENDIX C. FLOWCHARTS AND PSEUDO CODES

Figure 17. Program Flowchart and Pseudo Code

Start

program_command (addressToProgram, dataToProgram) {:

Write 40h or 10h

writeToFlash (any_address, 0x40) ;

/*or writeToFlash (any_address, 0x10) ; */

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03538b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

40/50

M28W160CT, M28W160CB

Figure 18. Double Word Program Flowchart and Pseudo Code

Start

Write 30h

double_word_program_command (addressToProgram1, dataToProgram1,

addressToProgram2, dataToProgram2)

{

writeToFlash (any_address, 0x30) ;

writeToFlash (addressToProgram1, dataToProgram1) ;

/*see note (3) */

Write Address 1

& Data 1 (3)

writeToFlash (addressToProgram2, dataToProgram2) ;

/*see note (3) */

/*Memory enters read status state after

the Program command*/

Write Address 2

& Data 2 (3)

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

Program

b4 = 0

YES

Error (1, 2)

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03539b

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase operations.

3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0.

41/50

M28W160CT, M28W160CB

Figure 19. Program Suspend & Resume Flowchart and Pseudo Code

Start

program_suspend_command ( ) {

writeToFlash (any_address, 0xB0) ;

Write B0h

Write 70h

writeToFlash (any_address, 0x70) ;

/* read status register to check if

program has already completed */

do {

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

Read Status

Register

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

b2 = 1

YES

Program Complete

if (status_register.b2==0) /*program completed */

{ writeToFlash (any_address, 0xFF) ;

read_data ( ) ; /*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

}

Read data from

another address

else

{ writeToFlash (any_address, 0xFF) ;

read_data ( ); /*read data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume program*/

Write D0h

Write FFh

Read Data

}

Program Continues

AI03540b

42/50

M28W160CT, M28W160CB

Figure 20. Erase Flowchart and Pseudo Code

Start

erase_command ( blockToErase ) {

writeToFlash (any_address, 0x20) ;

Write 20h

writeToFlash (blockToErase, 0xD0) ;

/* only A12-A20 are significannt */

/* Memory enters read status state after

the Erase Command */

Write Block

Address & D0h

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

} while (status_register.b7== 0) ;

YES

NO

YES

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

Error (1)

b3 = 0

YES

if ( (status_register.b4==1) && (status_register.b5==1) )

/* command sequence error */

Command

Sequence Error (1)

b4, b5 = 1

NO

error_handler ( ) ;

if ( (status_register.b5==1) )

/* erase error */

b5 = 0

YES

Erase Error (1)

error_handler ( ) ;

Erase to Protected

Block Error (1)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI03541b

Note: If an error is found, the Status Register must be cleared before further Program/Erase operations.

43/50

M28W160CT, M28W160CB

Figure 21. Erase Suspend & Resume Flowchart and Pseudo Code

Start

erase_suspend_command ( ) {

Write B0h

Write 70h

writeToFlash (any_address, 0xB0) ;

writeToFlash (any_address, 0x70) ;

/* read status register to check if

erase has already completed */

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

} while (status_register.b7== 0) ;

b7 = 1

YES

if (status_register.b6==0) /*erase completed */

{ writeToFlash (any_address, 0xFF) ;

b6 = 1

YES

Erase Complete

read_data ( ) ;

/*read data from another block*/

/*The device returns to Read Array

(as if program/erase suspend was not issued).*/

Write FFh

Read data from

another block

or

Program/Protection Program

or

Block Protect/Unprotect/Lock

}

else

{ writeToFlash (any_address, 0xFF) ;

read_program_data ( );

/*read or program data from another address*/

writeToFlash (any_address, 0xD0) ;

/*write 0xD0 to resume erase*/

Write D0h

Write FFh

Read Data

}

Erase Continues

AI03542b

44/50

M28W160CT, M28W160CB

Figure 22. Locking Operations Flowchart and Pseudo Code

Start

locking_operation_command (address, lock_operation) {

writeToFlash (any_address, 0x60) ; /*configuration setup*/

Write 60h

if (lock_operation==LOCK) /*to protect the block*/

writeToFlash (address, 0x01) ;

else if (lock_operation==UNLOCK) /*to unprotect the block*/

writeToFlash (address, 0xD0) ;

Write

01h, D0h or 2Fh

else if (lock_operation==LOCK-DOWN) /*to lock the block*/

writeToFlash (address, 0x2F) ;

writeToFlash (any_address, 0x90) ;

Write 90h

Read Block

Lock States

if (readFlash (address) ! = locking_state_expected)

error_handler () ;

NO

Locking

change

/*Check the locking state (see Read Block Signature table )*/

confirmed?

YES

writeToFlash (any_address, 0xFF) ; /*Reset to Read Array mode*/

Write FFh

}

End

AI04364

45/50

M28W160CT, M28W160CB

Figure 23. Protection Register Program Flowchart and Pseudo Code

Start

protection_register_program_command (addressToProgram, dataToProgram) {:

Write C0h

writeToFlash (any_address, 0xC0) ;

writeToFlash (addressToProgram, dataToProgram) ;

/*Memory enters read status state after

the Program Command*/

Write Address

& Data

do {

Read Status

Register

status_register=readFlash (any_address) ;

/* E or G must be toggled*/

NO

b7 = 1

YES

} while (status_register.b7== 0) ;

NO

V

Invalid

if (status_register.b3==1) /*VPP invalid error */

error_handler ( ) ;

PP

b3 = 0

YES

Error (1, 2)

NO

Program

Error (1, 2)

if (status_register.b4==1) /*program error */

error_handler ( ) ;

b4 = 0

YES

Program to Protected

Block Error (1, 2)

if (status_register.b1==1) /*program to protect block error */

error_handler ( ) ;

b1 = 0

YES

End

}

AI04381

Note: 1. Status check of b1 (Protected Block), b3 (V Invalid) and b4 (Program Error) can be made after each program operation or after

PP

a sequence.

2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations.

46/50

M28W160CT, M28W160CB

APPENDIX D. COMMAND INTERFACE AND PROGRAM/ERASE CONTROLLER STATE

Table 32. Write State Machine Current/Next, sheet 1 of 2.

Command Input (and Next State)

Data

When

Read

Current

State

SR

bit 7

Read

Array

(FFh)

Program

Setup

(10/40h)

Erase

Setup

(20h)

Erase

Confirm

(D0h)

Prog/Ers

Suspend

(B0h)

Prog/Ers

Resume

(D0h)

Read

Status

(70h)

Clear

Status

(50h)

Read Array “1”

Array

Read Array Prog.Setup Ers. Setup

Read Array

Read Sts. Read Array

Read

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Read

“1”

Electronic

Signature

Program

Setup

Erase

Setup

Read

Read Array

Status

Elect.Sg.

Read CFI

“1”

Program

Setup

Erase

Setup

Read

CFI

Read Array

Status

Query

Lock

(complete)

Lock Cmd

Error

Lock

(complete)

Lock Setup “1”

Status

Lock Command Error

Lock Cmd

“1”

Program

Setup

Erase

Setup

Read

Read Array

Status

Error

Lock

“1”

Program

Setup

Erase

Setup

Read

Read Array

Status

(complete)

Prot. Prog.

“1”

Protection Register Program

Protection Register Program continue

Setup

Prot. Prog.

“0”

(continue)

Prot. Prog.

“1”

Program

Setup

Erase

Setup

Read

Status

Read Array

Program

Read Array

Status

(complete)

Prog. Setup “1”

Program

“0”

Prog. Sus

Read Sts

Program (continue)

(continue)

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

Status

Array

Status

(continue) Read Array (continue) Read Sts Read Array

Program Prog. Sus Program Prog. Sus Prog. Sus

(continue) Read Array (continue) Read Sts Read Array

Prog. Sus

“1”

Prog. Sus

Read Array

Program Suspend to

Read Array

Prog. Sus

Read

Elect.Sg.

Electronic Prog. Sus

Signature Read Array

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

“1”

(continue) Read Array (continue) Read Sts Read Array

Prog. Sus

Read CFI

Prog. Sus

CFI

Program Suspend to

Read Array

Program

Prog. Sus

Program

Prog. Sus Prog. Sus

“1”

“0”

“1”

Read Array

(continue) Read Array (continue) Read Sts Read Array

Program

(complete)

Program

Setup

Erase

Setup

Read

Status

Array

Read Array

Erase

Read Array

Erase

Setup

Erase

Erase Command Error

(continue) CmdError (continue)

Erase

Cmd.Error

Program

Setup

Erase

Setup

Read

Read Array

Status

Erase

(continue)

Erase Sus

Read Sts

Erase (continue)

Erase Sus

Read Sts

Erase Sus

Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

Read Array (continue) Read Array (continue) Read Sts Read Array

Erase Sus Erase Erase Sus Erase Erase Sus Erase Sus

Read Array (continue) Read Array (continue) Read Sts Read Array

Erase Sus

Read Array

Erase Sus

Read Array

Program

Setup

Erase Sus

Read

Elect.Sg.

Electronic Erase Sus

Signature Read Array

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

“1”

Read Array (continue) Read Array (continue) Read Sts Read Array

Erase Sus

Read CFI

Erase Sus

CFI

Program

Setup

Erase Sus

Erase

Erase Sus

Erase

Erase Sus Erase Sus

“1”

Read Array

Read Array (continue) Read Array (continue) Read Sts Read Array

Erase

(complete)

Program

Setup

Erase

Setup

Read

Status

Read Array

Status

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Ers = Erase, Prog. = Program, Prot = Protection, Sus = Suspend.

47/50

M28W160CT, M28W160CB

Table 33. Write State Machine Current/Next, sheet 2 of 2.

Command Input (and Next State)

Read CFI

Query

(98h)

Unlock

Confirm

(D0h)

Current State

Read Elect.Sg.

(90h)

Lock Setup

(60h)

Prot. Prog.

Setup (C0h)

Lock Confirm

(01h)

Lock Down

Confirm (2Fh)

Prot. Prog.

Setup

Read Array

Read Status

Read Elect.Sg. Read CFI Query

Lock Setup

Read Array

Prot. Prog.

Setup

Prot. Prog.

Setup

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Read CFI Query Read Elect.Sg. Read CFI Query

Prot. Prog.

Setup

Read Array

Lock (complete)

Read Array

Lock Setup

Lock Command Error

Prot. Prog.

Setup

Lock Cmd Error Read Elect.Sg. Read CFI Query

Lock Setup

Prot. Prog.

Setup

Lock (complete) Read Elect.Sg. Read CFI Query

Read Array

Prot. Prog.

Setup

Protection Register Program

Prot. Prog.

(continue)

Protection Register Program (continue)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Setup

Prog. Setup

Program

(continue)

Program (continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Program Suspend Read Array

Read Status

Prog. Suspend Prog. Suspend Prog. Suspend

Read Array Read Elect.Sg. Read CFI Query

Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Program

(continue)

Prog. Suspend Prog. Suspend Prog. Suspend

Program

(continue)

Read CFI

Read Elect.Sg. Read CFI Query

Program

(complete)

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFIQuery

Read Array

Setup

Erase

(continue)

Erase Setup

Erase Command Error

Erase

Cmd.Error

Prot. Prog.

Lock Setup

Read Elect.Sg. Read CFI Query

Setup

Erase (continue)

Erase Suspend Erase Suspend Erase Suspend

Read Status Read Elect.Sg. Read CFI Query

Erase

(continue)

Lock Setup

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read Array Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Erase Suspend Erase Suspend

Read Elect.Sg. Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase Suspend Read Array

Erase Suspend Erase Suspend Erase Suspend

Read CFI Query Read Elect.Sg. Read CFI Query

Erase

(continue)

Erase

Prot. Prog.

Setup

Read Elect.Sg. Read CFI Query

(complete)

Read Array

Note: Cmd = Command, Elect.Sg. = Electronic Signature, Prog. = Program, Prot = Protection.

48/50

M28W160CT, M28W160CB

REVISION HISTORY

Table 34. Document Revision History

Date

January 2001

3/06/01

Version

-01

Revision Details

First Issue

-02

Document type: from Preliminary Data to Data Sheet

70ns Speed Class added

24-Apr-2001

29-May-2001

31-May-2001

02-Jul-2001

-03

-04

-05

-06

Completely rewritten and restructured, 85ns speed class added.

Corrections made to CFI data.

Corrections to TFBGA46 package dimensions.

Corrections to Table 3. Commands (Lock, Unlock, Lock-Down)

V

Maximum changed to 3.3V

DDQ

31-Oct-2001

16-May-2002

-07

-08

Commands Table, Read CFI Query Address on 1st cycle changed to ‘X’ (Table 4)

t

description clarified (Table 17)

WHEL

V

Maximum changed to 3.6V, TFBGA package dimensions added to description.

DDQ

Revision numbering modified: a minor revision will be indicated by incrementing the

digit after the dot, and a major revision, by incrementing the digit before the dot

(revision version 08 equals 8.0). Revision History moved to end of document.

Data Retention parameter added to Table 8, Program, Erase Times and Program/

Erase Endurance Cycles. S option added to Table 22, Ordering Information Scheme,

and T option specified.

19-Feb-2003

04-Oct-2005

8.1

9.0

ECOPACK Package option added.

TSOP48 Mechanical Data updated.

Note 1 updated and notes 2 and 3 added belowTable 12.Absolute Maximum Ratings.

Figure 13. TSOP48 - 48 lead Plastic Thin Small Outline, 12 x 20mm, Package

Outline corrected.

20-Jan-2006

10-Dec-2007

10.0

11.0

Applied Numonyx branding.

49/50

M28W160CT, M28W160CB

Please Read Carefully:

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR

IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT

AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY

WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF

NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,

MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.

Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility

applications.

Numonyx may make changes to specifications and product descriptions at any time, without notice.

Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to

the presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or

implied, by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves

these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.

Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by

visiting Numonyx's website at http://www.numonyx.com.

Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

50/50


型号：	M28W160CT90N6F
厂家：	NUMONYX B.V
描述：	16 Mbit (1Mb x16, Boot Block) 3V Supply Flash Memory 16兆位（ 1Mb的X16 ，引导块） 3V供应闪存闪存存储内存集成电路光电二极管
文件：	总50页 (文件大小：1298K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

M28W160CT90N6F [NUMONYX]

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