M25P40-VMN3TP/X [NUMONYX]
4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface; 4兆位，低电压，串行闪存，具有50 MHz SPI总线接口
| 型号： | M25P40-VMN3TP/X |
| 厂家： | 
NUMONYX B.V |
| 描述： | 4 Mbit, low voltage, serial Flash memory with 50 MHz SPI bus interface |
| 文件： | 总53页 (文件大小：1017K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
M25P40
4 Mbit, low voltage, serial Flash memory
with 50 MHz SPI bus interface
Features
■ 4 Mbit of Flash memory
■ 2.3 V to 3.6 V single supply voltage
■ SPI bus compatible serial interface
■ 50 MHz clock rate (maximum)
SO8 (MN)
150 mil width
■ Page Program (up to 256 bytes) in 1.5 ms
(typical)
■ Sector Erase (512 Kbit) in 1 s (typical)
■ Bulk Erase (4 Mbit) in 4.5 s (typical)
■ Deep Power-down mode 1 µA (typical)
■ Hardware Write Protection: protected area size
defined by three non-volatile bits (BP0, BP1
and BP2)
VFQFPN8 (MP)
(MLP8)
■ Electronic signatures
– JEDEC standard two-byte signature
(2013h)
– RES instruction, one-byte, signature (12h),
for backward compatibility
■ Packages
– ECOPACK® (RoHS compliant)
December 2007
Rev 15
1/53
www.numonyx.com
1
Contents
M25P40
Contents
1
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
Serial Data output (Q) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Data input (D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial Clock (C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Chip Select (S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Hold (HOLD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Protect (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
VCC supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3
4
SPI modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Operating features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.1
4.2
4.3
4.4
4.5
4.6
4.7
Page Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Sector Erase and Bulk Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Polling during a Write, Program or Erase cycle . . . . . . . . . . . . . . . . . . . . 12
Active Power, Standby Power and Deep Power-down modes . . . . . . . . . 12
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Hold condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5
6
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
6.1
6.2
6.3
6.4
Write Enable (WREN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Disable (WRDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Identification (RDID) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Read Status Register (RDSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.4.1
6.4.2
6.4.3
WIP bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
WEL bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
BP2, BP1, BP0 bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
2/53
M25P40
Contents
6.4.4
SRWD bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.5
6.6
6.7
6.8
6.9
Write Status Register (WRSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Read Data Bytes (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Read Data Bytes at Higher Speed (FAST_READ) . . . . . . . . . . . . . . . . . . 27
Page Program (PP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Sector Erase (SE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
6.10 Bulk Erase (BE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6.11 Deep Power-down (DP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.12 Release from Deep Power-down and Read Electronic Signature (RES) . 33
7
Power-up and Power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Initial delivery state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
8
9
10
11
12
13
3/53
List of tables
M25P40
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Protected area sizes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Instruction set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Read Identification (RDID) data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Status Register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Protection modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Power-up timing and V threshold . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
WI
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Data retention and endurance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
DC characteristics (device grade 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
DC characteristics (device grade 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Instruction times (device grade 6). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Instruction times (device grade 3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC measurement conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Which AC characteristics to use? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
AC characteristics (25 MHz operation, device grade 3, V min = 2.7 V) . . . . . . . . . . . . . 42
CC
AC characteristics (50 MHz operation, device grade 6, V min = 2.7 V) . . . . . . . . . . . . . 43
CC
AC characteristics (40 MHz operation, device grade 6, V min = 2.3 V) . . . . . . . . . . . . . 44
CC
SO8 narrow – 8 lead plastic Small Outline, 150 mils body width,
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
Table 23.
6 × 5 mm, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 24.
Table 25.
4/53
M25P40
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SO and VFQFPN connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Bus Master and memory devices on the SPI bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SPI modes supported . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Hold condition activation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Write Enable (WREN) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Write Disable (WRDI) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Read Identification (RDID) instruction sequence and data-out sequence . . . . . . . . . . . . . 21
Figure 10. Read Status Register (RDSR) instruction sequence and data-out sequence . . . . . . . . . . 23
Figure 11. Write Status Register (WRSR) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence . . . . . . . . . . . . . . 26
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 14. Page Program (PP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Sector Erase (SE) instruction sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Bulk Erase (BE) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure 17. Deep Power-down (DP) instruction sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 19. Release from Deep Power-down (RES) instruction sequence . . . . . . . . . . . . . . . . . . . . . . 34
Figure 20. Power-up timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 22. Serial input timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1 . . . . . . . . . . . . . . . . . 45
Figure 24. Hold timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 25. Output timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package outline. . . . . . . 47
Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
5/53
Description
M25P40
1
Description
The M25P40 is a 4 Mbit (512 K × 8) Serial Flash memory, with advanced write protection
mechanisms, accessed by a high speed SPI-compatible bus.
The memory can be programmed 1 to 256 bytes at a time, using the Page Program
instruction.
The memory is organized as 8 sectors, each containing 256 pages. Each page is 256 bytes
wide. Thus, the whole memory can be viewed as consisting of 2048 pages, or 524,288
bytes.
The whole memory can be erased using the Bulk Erase instruction, or a sector at a time,
using the Sector Erase instruction.
In order to meet environmental requirements, Numonyx offers the M25P40 in ECOPACK®
packages. ECOPACK® packages are Lead-free and RoHS compliant.
Figure 1.
Logic diagram
V
CC
D
C
S
Q
M25P40
W
HOLD
V
SS
AI04090
Table 1.
Signal names
Signal name
Function
Direction
C
Serial Clock
Input
D
Serial Data input
Input
Output
Input
Input
Input
Q
Serial Data output
Chip Select
Write Protect
Hold
S
W
HOLD
VCC
VSS
Supply voltage
Ground
6/53
M25P40
Description
Figure 2.
SO and VFQFPN connections
M25P40
S
Q
1
8
V
CC
HOLD
2
3
4
7
W
6
5
C
D
V
SS
AI04091B
1. There is an exposed central pad on the underside of the VFQFPN package. This is pulled, internally, to
VSS, and must not be allowed to be connected to any other voltage or signal line on the PCB.
2. See Section 11: Package mechanical for package dimensions, and how to identify pin-1.
7/53
Signal description
M25P40
2
Signal description
2.1
Serial Data output (Q)
This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of Serial Clock (C).
2.2
2.3
2.4
Serial Data input (D)
This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and the data to be programmed. Values are latched on the rising edge of Serial
Clock (C).
Serial Clock (C)
This input signal provides the timing of the serial interface. Instructions, addresses, or data
present at Serial Data input (D) are latched on the rising edge of Serial Clock (C). Data on
Serial Data output (Q) changes after the falling edge of Serial Clock (C).
Chip Select (S)
When this input signal is High, the device is deselected and Serial Data output (Q) is at high
impedance. Unless an internal Program, Erase or Write Status Register cycle is in progress,
the device will be in the Standby Power mode (this is not the Deep Power-down mode).
Driving Chip Select (S) Low selects the device, placing it in the Active Power mode.
After Power-up, a falling edge on Chip Select (S) is required prior to the start of any
instruction.
2.5
2.6
Hold (HOLD)
The Hold (HOLD) signal is used to pause any serial communications with the device without
deselecting the device.
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
Write Protect (W)
The main purpose of this input signal is to freeze the size of the area of memory that is
protected against program or erase instructions (as specified by the values in the BP2, BP1
and BP0 bits of the Status Register).
8/53
M25P40
Signal description
2.7
VCC supply voltage
V
is the supply voltage.
CC
2.8
VSS ground
V
is the reference for the V supply voltage.
CC
SS
9/53
SPI modes
M25P40
3
SPI modes
These devices can be driven by a microcontroller with its SPI peripheral running in either of
the two following modes:
●
CPOL=0, CPHA=0
CPOL=1, CPHA=1
●
For these two modes, input data is latched in on the rising edge of Serial Clock (C), and
output data is available from the falling edge of Serial Clock (C).
The difference between the two modes, as shown in Figure 4, is the clock polarity when the
bus master is in Stand-by mode and not transferring data:
●
C remains at 0 for (CPOL=0, CPHA=0)
C remains at 1 for (CPOL=1, CPHA=1)
●
Figure 3.
Bus Master and memory devices on the SPI bus
V
V
SS
CC
R
SDO
SPI Interface with
(CPOL, CPHA) =
(0, 0) or (1, 1)
SDI
SCK
V
V
V
CC
C
Q
D
C
Q
D
C Q D
CC
CC
V
V
V
SS
SS
SS
SPI Bus Master
SPI Memory
Device
SPI Memory
Device
SPI Memory
Device
R
R
R
CS3 CS2 CS1
S
S
S
W
HOLD
W
HOLD
HOLD
W
AI12836b
1. The Write Protect (W) and Hold (HOLD) signals should be driven, High or Low as appropriate.
Figure 3 shows an example of three devices connected to an MCU, on an SPI bus. Only one
device is selected at a time, so only one device drives the Serial Data output (Q) line at a
time, the other devices are high impedance. Resistors R (represented in Figure 3) ensure
that the M25P40 is not selected if the Bus Master leaves the S line in the high impedance
state. As the Bus Master may enter a state where all inputs/outputs are in high impedance
at the same time (for example, when the Bus Master is reset), the clock line (C) must be
connected to an external pull-down resistor so that, when all inputs/outputs become high
impedance, the S line is pulled High while the C line is pulled Low (thus ensuring that S and
C do not become High at the same time, and so, that the t
requirement is met). The
SHCH
typical value of R is 100 kΩ, assuming that the time constant R*C (C = parasitic
p
p
capacitance of the bus line) is shorter than the time during which the Bus Master leaves the
SPI bus in high impedance.
10/53
M25P40
SPI modes
Example: C = 50 pF, that is R*C = 5 µs <=> the application must ensure that the Bus
p
p
Master never leaves the SPI bus in the high impedance state for a time period shorter than
5 µs.
Figure 4.
SPI modes supported
CPOL CPHA
C
0
1
0
1
C
D
MSB
Q
MSB
AI01438B
11/53
Operating features
M25P40
4
Operating features
4.1
Page Programming
To program one data byte, two instructions are required: Write Enable (WREN), which is one
byte, and a Page Program (PP) sequence, which consists of four bytes plus data. This is
followed by the internal Program cycle (of duration t ).
PP
To spread this overhead, the Page Program (PP) instruction allows up to 256 bytes to be
programmed at a time (changing bits from 1 to 0), provided that they lie in consecutive
addresses on the same page of memory.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Page Program (PP),
Instruction times (device grade 6) and Table 16: Instruction times (device grade 3)).
4.2
Sector Erase and Bulk Erase
The Page Program (PP) instruction allows bits to be reset from 1 to 0. Before this can be
applied, the bytes of memory need to have been erased to all 1s (FFh). This can be
achieved either a sector at a time, using the Sector Erase (SE) instruction, or throughout the
entire memory, using the Bulk Erase (BE) instruction. This starts an internal Erase cycle (of
duration t or t ).
SE
BE
The Erase instruction must be preceded by a Write Enable (WREN) instruction.
4.3
4.4
Polling during a Write, Program or Erase cycle
A further improvement in the time to Write Status Register (WRSR), Program (PP) or Erase
(SE or BE) can be achieved by not waiting for the worst case delay (t , t , t , or t ). The
W
PP SE
BE
Write In Progress (WIP) bit is provided in the Status Register so that the application program
can monitor its value, polling it to establish when the previous Write cycle, Program cycle or
Erase cycle is complete.
Active Power, Standby Power and Deep Power-down modes
When Chip Select (S) is Low, the device is selected, and in the Active Power mode.
When Chip Select (S) is High, the device is deselected, but could remain in the Active Power
mode until all internal cycles have completed (Program, Erase, Write Status Register). The
device then goes in to the Standby Power mode. The device consumption drops to I
.
CC1
The Deep Power-down mode is entered when the specific instruction (the Deep Power-
down (DP) instruction) is executed. The device consumption drops further to I . The
CC2
device remains in this mode until another specific instruction (the Release from Deep
Power-down and Read Electronic Signature (RES) instruction) is executed.
All other instructions are ignored while the device is in the Deep Power-down mode. This
can be used as an extra software protection mechanism, when the device is not in active
use, to protect the device from inadvertent Write, Program or Erase instructions.
12/53
M25P40
Operating features
4.5
Status Register
The Status Register contains a number of status and control bits that can be read or set (as
appropriate) by specific instructions. For a detailed description of the Status Register bits,
see Section 6.4: Read Status Register (RDSR).
4.6
Protection modes
The environments where non-volatile memory devices are used can be very noisy. No SPI
device can operate correctly in the presence of excessive noise. To help combat this, the
M25P40 features the following data protection mechanisms:
●
Power On Reset and an internal timer (t
) can provide protection against inadvertent
PUW
changes while the power supply is outside the operating specification.
●
Program, Erase and Write Status Register instructions are checked that they consist of
a number of clock pulses that is a multiple of eight, before they are accepted for
execution.
●
All instructions that modify data must be preceded by a Write Enable (WREN)
instruction to set the Write Enable Latch (WEL) bit. This bit is returned to its reset state
by the following events:
–
–
–
–
–
–
Power-up
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
●
●
The Block Protect (BP2, BP1, BP0) bits allow part of the memory to be configured as
read-only. This is the Software Protected Mode (SPM).
The Write Protect (W) signal allows the Block Protect (BP2, BP1, BP0) bits and Status
Register Write Disable (SRWD) bit to be protected. This is the Hardware Protected
Mode (HPM).
●
In addition to the low power consumption feature, the Deep Power-down mode offers
extra software protection from inadvertent Write, Program and Erase instructions, as all
instructions are ignored except one particular instruction (the Release from Deep
Power-down instruction).
13/53
Operating features
Table 2.
M25P40
Protected area sizes
Status Register
Memory content
content
BP2 BP1 BP0
Protected area
Unprotected area
bit
bit
bit
0
0
0
none
Upper eighth (Sector 7)
All sectors(1) (eight sectors: 0 to 7)
Lower seven-eighths (seven sectors: 0 to
6)
0
0
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
Upper quarter (two sectors: 6 and 7) Lower three-quarters (six sectors: 0 to 5)
Upper half (four sectors: 4 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
All sectors (eight sectors: 0 to 7)
Lower half (four sectors: 0 to 3)
none
none
none
none
1. The device is ready to accept a Bulk Erase instruction if, and only if, all Block Protect (BP2, BP1, BP0) are
0.
4.7
Hold condition
The Hold (HOLD) signal is used to pause any serial communications with the device without
resetting the clocking sequence. However, taking this signal Low does not terminate any
Write Status Register, Program or Erase cycle that is currently in progress.
To enter the Hold condition, the device must be selected, with Chip Select (S) Low.
The Hold condition starts on the falling edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low (as shown in Figure 5).
The Hold condition ends on the rising edge of the Hold (HOLD) signal, provided that this
coincides with Serial Clock (C) being Low.
If the falling edge does not coincide with Serial Clock (C) being Low, the Hold condition
starts after Serial Clock (C) next goes Low. Similarly, if the rising edge does not coincide
with Serial Clock (C) being Low, the Hold condition ends after Serial Clock (C) next goes
Low. (This is shown in Figure 5).
During the Hold condition, the Serial Data output (Q) is high impedance, and Serial Data
input (D) and Serial Clock (C) are Don’t Care.
Normally, the device is kept selected, with Chip Select (S) driven Low, for the whole duration
of the Hold condition. This is to ensure that the state of the internal logic remains unchanged
from the moment of entering the Hold condition.
If Chip Select (S) goes High while the device is in the Hold condition, this has the effect of
resetting the internal logic of the device. To restart communication with the device, it is
necessary to drive Hold (HOLD) High, and then to drive Chip Select (S) Low. This prevents
the device from going back to the Hold condition.
14/53
M25P40
Operating features
Figure 5.
Hold condition activation
C
HOLD
Hold
Hold
Condition
Condition
(standard use)
(non-standard use)
AI02029D
15/53
Memory organization
M25P40
5
Memory organization
The memory is organized as:
●
●
●
524,288 bytes (8 bits each)
8 sectors (512 Kbits, 65536 bytes each)
2048 pages (256 bytes each).
Each page can be individually programmed (bits are programmed from 1 to 0). The device is
Sector or Bulk Erasable (bits are erased from 0 to 1) but not Page Erasable.
Table 3.
Memory organization
Sector
Address range
7
6
5
4
3
2
1
0
70000h
60000h
50000h
40000h
30000h
20000h
10000h
00000h
7FFFFh
6FFFFh
5FFFFh
4FFFFh
3FFFFh
2FFFFh
1FFFFh
0FFFFh
16/53
M25P40
Memory organization
Figure 6.
Block diagram
HOLD
W
High Voltage
Generator
Control Logic
S
C
D
Q
I/O Shift Register
Status
Register
Address Register
and Counter
256 Byte
Data Buffer
7FFFFh
Size of the
read-only
memory area
00000h
000FFh
256 Bytes (Page Size)
X Decoder
AI04986
17/53
Instructions
M25P40
6
Instructions
All instructions, addresses and data are shifted in and out of the device, most significant bit
first.
Serial Data input (D) is sampled on the first rising edge of Serial Clock (C) after Chip Select
(S) is driven Low. Then, the one-byte instruction code must be shifted in to the device, most
significant bit first, on Serial Data input (D), each bit being latched on the rising edges of
Serial Clock (C).
The instruction set is listed in Table 4.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or none.
Chip Select (S) must be driven High after the last bit of the instruction sequence has been
shifted in.
In the case of a Read Data Bytes (READ), Read Data Bytes at Higher Speed (Fast_Read),
Read Identification (RDID), Read Status Register (RDSR) or Release from Deep Power-
down, and Read Electronic Signature (RES) instruction, the shifted-in instruction sequence
is followed by a data-out sequence. Chip Select (S) can be driven High after any bit of the
data-out sequence is being shifted out.
In the case of a Page Program (PP), Sector Erase (SE), Bulk Erase (BE), Write Status
Register (WRSR), Write Enable (WREN), Write Disable (WRDI) or Deep Power-down (DP)
instruction, Chip Select (S) must be driven High exactly at a byte boundary, otherwise the
instruction is rejected, and is not executed. That is, Chip Select (S) must driven High when
the number of clock pulses after Chip Select (S) being driven Low is an exact multiple of
eight.
All attempts to access the memory array during a Write Status Register cycle, Program
cycle or Erase cycle are ignored, and the internal Write Status Register cycle, Program
cycle or Erase cycle continues unaffected.
18/53
M25P40
Instructions
Table 4.
Instruction set
Description
One-byte instruction Address Dummy
Data
Instruction
code
bytes
bytes
bytes
WREN
WRDI
Write Enable
0000 0110
0000 0100
1001 1111
0000 0101
0000 0001
0000 0011
06h
04h
9Fh
05h
01h
03h
0
0
0
0
0
3
0
0
0
0
0
0
0
Write Disable
0
RDID(1)
RDSR
WRSR
READ
Read Identification
Read Status Register
Write Status Register
Read Data Bytes
1 to 3
1 to ∞
1
1 to ∞
Read Data Bytes at Higher
Speed
FAST_READ
0000 1011
0Bh
3
1
1 to ∞
PP
SE
BE
DP
Page Program
Sector Erase
Bulk Erase
0000 0010
1101 1000
1100 0111
1011 1001
02h
D8h
C7h
B9h
3
3
0
0
0
0
0
0
1 to 256
0
0
0
Deep Power-down
Release from Deep Power-
down, and Read Electronic
Signature
0
0
3
0
1 to ∞
RES
1010 1011
ABh
Release from Deep Power-
down
0
1. The Read Identification (RDID) instruction is available only in products with Process Technology code X
(see Application Note AN1995).
6.1
Write Enable (WREN)
The Write Enable (WREN) instruction (Figure 7) sets the Write Enable Latch (WEL) bit.
The Write Enable Latch (WEL) bit must be set prior to every Page Program (PP), Sector
Erase (SE), Bulk Erase (BE) and Write Status Register (WRSR) instruction.
The Write Enable (WREN) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
Figure 7.
Write Enable (WREN) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI02281E
19/53
Instructions
M25P40
6.2
Write Disable (WRDI)
The Write Disable (WRDI) instruction (Figure 8) resets the Write Enable Latch (WEL) bit.
The Write Disable (WRDI) instruction is entered by driving Chip Select (S) Low, sending the
instruction code, and then driving Chip Select (S) High.
The Write Enable Latch (WEL) bit is reset under the following conditions:
●
Power-up
●
●
●
●
●
Write Disable (WRDI) instruction completion
Write Status Register (WRSR) instruction completion
Page Program (PP) instruction completion
Sector Erase (SE) instruction completion
Bulk Erase (BE) instruction completion
Figure 8.
Write Disable (WRDI) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Q
Instruction
High Impedance
AI03750D
20/53
M25P40
Instructions
6.3
Read Identification (RDID)
The Read Identification (RDID) instruction is available in products with Process Technology
code X only.
The Read Identification (RDID) instruction allows the 8-bit manufacturer identification to be
read, followed by two bytes of device identification. The manufacturer identification is
assigned by JEDEC, and has the value 20h for Numonyx. The device identification is
assigned by the device manufacturer, and indicates the memory type in the first byte (20h),
and the memory capacity of the device in the second byte (13h).
Any Read Identification (RDID) instruction while an Erase or Program cycle is in progress, is
not decoded, and has no effect on the cycle that is in progress.
The Read Identification (RDID) instruction should not be issued while the device is in Deep
Power-down mode.
The device is first selected by driving Chip Select (S) Low. Then, the 8-bit instruction code
for the instruction is shifted in. This is followed by the 24-bit device identification, stored in
the memory, being shifted out on Serial Data output (Q), each bit being shifted out during
the falling edge of Serial Clock (C).
The instruction sequence is shown in Figure 9.
The Read Identification (RDID) instruction is terminated by driving Chip Select (S) High at
any time during data output.
When Chip Select (S) is driven High, the device is put in the Stand-by Power mode. Once in
the Stand-by Power mode, the device waits to be selected, so that it can receive, decode
and execute instructions.
Table 5.
Read Identification (RDID) data-out sequence
Device identification
Manufacturer identification
Memory type
Memory capacity
20h
20h
13h
Figure 9.
Read Identification (RDID) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18
28 29 30 31
C
D
Instruction
Manufacturer Identification
Device Identification
High Impedance
Q
15 14 13
MSB
3
2
1
0
MSB
AI06809b
21/53
Instructions
M25P40
6.4
Read Status Register (RDSR)
The Read Status Register (RDSR) instruction allows the Status Register to be read. The
Status Register may be read at any time, even while a Program, Erase or Write Status
Register cycle is in progress. When one of these cycles is in progress, it is recommended to
check the Write In Progress (WIP) bit before sending a new instruction to the device. It is
also possible to read the Status Register continuously, as shown in Figure 10.
Table 6.
Status Register format
b7
b0
SRWD
0
0
BP2
BP1
BP0
WEL
WIP
Status Register Write Protect
Block Protect bits
Write Enable Latch bit
Write In Progress bit
The status and control bits of the Status Register are as follows:
6.4.1
6.4.2
6.4.3
WIP bit
The Write In Progress (WIP) bit indicates whether the memory is busy with a Write Status
Register, Program or Erase cycle. When set to 1, such a cycle is in progress, when reset to
0 no such cycle is in progress.
WEL bit
The Write Enable Latch (WEL) bit indicates the status of the internal Write Enable Latch.
When set to 1 the internal Write Enable Latch is set, when set to 0 the internal Write Enable
Latch is reset and no Write Status Register, Program or Erase instruction is accepted.
BP2, BP1, BP0 bits
The Block Protect (BP2, BP1, BP0) bits are non-volatile. They define the size of the area to
be software protected against Program and Erase instructions. These bits are written with
the Write Status Register (WRSR) instruction. When one or more of the Block Protect (BP2,
BP1, BP0) bits is set to 1, the relevant memory area (as defined in Table 2) becomes
protected against Page Program (PP) and Sector Erase (SE) instructions. The Block Protect
(BP2, BP1, BP0) bits can be written provided that the Hardware Protected mode has not
been set. The Bulk Erase (BE) instruction is executed if, and only if, all Block Protect (BP2,
BP1, BP0) bits are 0.
6.4.4
SRWD bit
The Status Register Write Disable (SRWD) bit is operated in conjunction with the Write
Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect (W)
signal allow the device to be put in the Hardware Protected mode (when the Status Register
Write Disable (SRWD) bit is set to 1, and Write Protect (W) is driven Low). In this mode, the
non-volatile bits of the Status Register (SRWD, BP2, BP1, BP0) become read-only bits and
the Write Status Register (WRSR) instruction is no longer accepted for execution.
22/53
M25P40
Instructions
Figure 10. Read Status Register (RDSR) instruction sequence and data-out
sequence
S
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
C
D
Instruction
Status Register Out
Status Register Out
High Impedance
Q
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
MSB
MSB
AI02031E
23/53
Instructions
M25P40
6.5
Write Status Register (WRSR)
The Write Status Register (WRSR) instruction allows new values to be written to the Status
Register. Before it can be accepted, a Write Enable (WREN) instruction must previously
have been executed. After the Write Enable (WREN) instruction has been decoded and
executed, the device sets the Write Enable Latch (WEL).
The Write Status Register (WRSR) instruction is entered by driving Chip Select (S) Low,
followed by the instruction code and the data byte on Serial Data input (D).
The instruction sequence is shown in Figure 11.
The Write Status Register (WRSR) instruction has no effect on b6, b5, b1 and b0 of the
Status Register. b6 and b5 are always read as 0.
Chip Select (S) must be driven High after the eighth bit of the data byte has been latched in.
If not, the Write Status Register (WRSR) instruction is not executed. As soon as Chip Select
(S) is driven High, the self-timed Write Status Register cycle (whose duration is t ) is
W
initiated. While the Write Status Register cycle is in progress, the Status Register may still
be read to check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP)
bit is 1 during the self-timed Write Status Register cycle, and is 0 when it is completed.
When the cycle is completed, the Write Enable Latch (WEL) is reset.
The Write Status Register (WRSR) instruction allows the user to change the values of the
Block Protect (BP2, BP1, BP0) bits, to define the size of the area that is to be treated as
read-only, as defined in Table 2. The Write Status Register (WRSR) instruction also allows
the user to set or reset the Status Register Write Disable (SRWD) bit in accordance with the
Write Protect (W) signal. The Status Register Write Disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in the Hardware Protected Mode (HPM). The Write
Status Register (WRSR) instruction is not executed once the Hardware Protected Mode
(HPM) is entered.
Figure 11. Write Status Register (WRSR) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
C
Instruction
Status
Register In
7
6
5
4
3
2
0
1
D
Q
High Impedance
MSB
AI02282D
24/53
M25P40
Instructions
Table 7.
Protection modes
Memory content
W
signal
SRWD
bit
Write Protection of the
Mode
Status Register
Protected area(1) Unprotected area(1)
1
0
0
0
Status Register is
Writable (if the WREN
instruction has set the
WEL bit)
Protected against
Ready to accept Page
Page Program,
Software
Protected
(SPM)
Program and Sector
Sector Erase and
Erase instructions
Bulk Erase
The values in the SRWD,
BP2, BP1 and BP0 bits
can be changed
1
0
1
1
Status Register is
Hardware write protected
Protected against
Ready to accept Page
Page Program,
Hardware
Protected
(HPM)
Program and Sector
Sector Erase and
Erase instructions
Bulk Erase
The values in the SRWD,
BP2, BP1 and BP0 bits
cannot be changed
1. As defined by the values in the Block Protect (BP2, BP1, BP0) bits of the Status Register, as shown in
Table 2.
The protection features of the device are summarized in Table 7.
When the Status Register Write Disable (SRWD) bit of the Status Register is 0 (its initial
delivery state), it is possible to write to the Status Register provided that the Write Enable
Latch (WEL) bit has previously been set by a Write Enable (WREN) instruction, regardless
of the whether Write Protect (W) is driven High or Low.
When the Status Register Write Disable (SRWD) bit of the Status Register is set to 1, two
cases need to be considered, depending on the state of Write Protect (W):
●
●
If Write Protect (W) is driven High, it is possible to write to the Status Register provided
that the Write Enable Latch (WEL) bit has previously been set by a Write Enable
(WREN) instruction.
If Write Protect (W) is driven Low, it is not possible to write to the Status Register even
if the Write Enable Latch (WEL) bit has previously been set by a Write Enable (WREN)
instruction. (Attempts to write to the Status Register are rejected, and are not accepted
for execution). As a consequence, all the data bytes in the memory area that are
software protected (SPM) by the Block Protect (BP2, BP1, BP0) bits of the Status
Register, are also hardware protected against data modification.
Regardless of the order of the two events, the Hardware Protected Mode (HPM) can be
entered:
●
by setting the Status Register Write Disable (SRWD) bit after driving Write Protect (W)
Low
●
or by driving Write Protect (W) Low after setting the Status Register Write Disable
(SRWD) bit.
The only way to exit the Hardware Protected Mode (HPM) once entered is to pull Write
Protect (W) High.
If Write Protect (W) is permanently tied High, the Hardware Protected Mode (HPM) can
never be activated, and only the Software Protected Mode (SPM), using the Block Protect
(BP2, BP1, BP0) bits of the Status Register, can be used.
25/53
Instructions
M25P40
6.6
Read Data Bytes (READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes (READ) instruction is followed by a 3-byte address (A23-A0), each bit being
latched-in during the rising edge of Serial Clock (C). Then the memory contents, at that
address, is shifted out on Serial Data output (Q), each bit being shifted out, at a maximum
frequency f , during the falling edge of Serial Clock (C).
R
The instruction sequence is shown in Figure 12.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes (READ) instruction. When the highest
address is reached, the address counter rolls over to 000000h, allowing the read sequence
to be continued indefinitely.
The Read Data Bytes (READ) instruction is terminated by driving Chip Select (S) High. Chip
Select (S) can be driven High at any time during data output. Any Read Data Bytes (READ)
instruction, while an Erase, Program or Write cycle is in progress, is rejected without having
any effects on the cycle that is in progress.
Figure 12. Read Data Bytes (READ) instruction sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
Instruction
24-Bit Address
23 22 21
MSB
3
2
1
0
D
Q
Data Out 1
Data Out 2
High Impedance
2
7
6
5
4
3
1
7
0
MSB
AI03748D
1. Address bits A23 to A19 are Don’t Care.
26/53
M25P40
Instructions
6.7
Read Data Bytes at Higher Speed (FAST_READ)
The device is first selected by driving Chip Select (S) Low. The instruction code for the Read
Data Bytes at Higher Speed (FAST_READ) instruction is followed by a 3-byte address (A23-
A0) and a dummy byte, each bit being latched-in during the rising edge of Serial Clock (C).
Then the memory contents, at that address, is shifted out on Serial Data output (Q), each bit
being shifted out, at a maximum frequency f , during the falling edge of Serial Clock (C).
C
The instruction sequence is shown in Figure 13.
The first byte addressed can be at any location. The address is automatically incremented
to the next higher address after each byte of data is shifted out. The whole memory can,
therefore, be read with a single Read Data Bytes at Higher Speed (FAST_READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The Read Data Bytes at Higher Speed (FAST_READ) instruction is terminated by driving
Chip Select (S) High. Chip Select (S) can be driven High at any time during data output. Any
Read Data Bytes at Higher Speed (FAST_READ) instruction, while an Erase, Program or
Write cycle is in progress, is rejected without having any effects on the cycle that is in
progress.
Figure 13. Read Data Bytes at Higher Speed (FAST_READ) instruction sequence
and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
C
Instruction
24 BIT ADDRESS
23 22 21
3
2
1
0
D
Q
S
C
High Impedance
47
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Dummy Byte
7
6
5
4
3
2
0
1
D
Q
DATA OUT 2
DATA OUT 1
7
6
5
4
3
2
1
0
7
7
6
5
4
3
2
0
1
MSB
MSB
MSB
AI04006
1. Address bits A23 to A19 are Don’t Care.
27/53
Instructions
M25P40
6.8
Page Program (PP)
The Page Program (PP) instruction allows bytes to be programmed in the memory
(changing bits from 1 to 0). Before it can be accepted, a Write Enable (WREN) instruction
must previously have been executed. After the Write Enable (WREN) instruction has been
decoded, the device sets the Write Enable Latch (WEL).
The Page Program (PP) instruction is entered by driving Chip Select (S) Low, followed by
the instruction code, three address bytes and at least one data byte on Serial Data input (D).
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes
beyond the end of the current page are programmed from the start address of the same
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 14.
If more than 256 bytes are sent to the device, previously latched data are discarded and the
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less
than 256 Data bytes are sent to device, they are correctly programmed at the requested
addresses without having any effects on the other bytes of the same page.
For optimized timings, it is recommended to use the Page Program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several Page
Program (PP) sequences with each containing only a few bytes (see Instruction times
(device grade 6) and Table 16: Instruction times (device grade 3)).
Chip Select (S) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the Page Program (PP) instruction is not executed.
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose
duration is t ) is initiated. While the Page Program cycle is in progress, the Status Register
PP
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress
(WIP) bit is 1 during the self-timed Page Program cycle, and is 0 when it is completed. At
some unspecified time before the cycle is completed, the Write Enable Latch (WEL) bit is
reset.
A Page Program (PP) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
28/53
M25P40
Instructions
Figure 14. Page Program (PP) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
C
D
Instruction
24-Bit Address
Data Byte 1
23 22 21
MSB
3
2
1
0
7
6
5
4
3
2
0
1
MSB
S
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
C
D
Data Byte 2
Data Byte 3
Data Byte 256
7
6
5
4
3
2
0
7
6
5
4
3
2
0
7
6
5
4
3
2
0
1
1
1
MSB
MSB
MSB
AI04082B
1. Address bits A23 to A19 are Don’t Care.
29/53
Instructions
M25P40
6.9
Sector Erase (SE)
The Sector Erase (SE) instruction sets to 1 (FFh) all bits inside the chosen sector. Before it
can be accepted, a Write Enable (WREN) instruction must previously have been executed.
After the Write Enable (WREN) instruction has been decoded, the device sets the Write
Enable Latch (WEL).
The Sector Erase (SE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code, and three address bytes on Serial Data input (D). Any address inside the
Sector (see Table 3) is a valid address for the Sector Erase (SE) instruction. Chip Select (S)
must be driven Low for the entire duration of the sequence.
The instruction sequence is shown in Figure 15.
Chip Select (S) must be driven High after the eighth bit of the last address byte has been
latched in, otherwise the Sector Erase (SE) instruction is not executed. As soon as Chip
Select (S) is driven High, the self-timed Sector Erase cycle (whose duration is t ) is
SE
initiated. While the Sector Erase cycle is in progress, the Status Register may be read to
check the value of the Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1
during the self-timed Sector Erase cycle, and is 0 when it is completed. At some unspecified
time before the cycle is completed, the Write Enable Latch (WEL) bit is reset.
A Sector Erase (SE) instruction applied to a page which is protected by the Block Protect
(BP2, BP1, BP0) bits (see Table 3 and Table 2) is not executed.
Figure 15. Sector Erase (SE) instruction sequence
S
0
1
2
3
4
5
6
7
8
9
29 30 31
C
D
Instruction
24 Bit Address
23 22
MSB
2
0
1
AI03751D
1. Address bits A23 to A19 are Don’t Care.
30/53
M25P40
Instructions
6.10
Bulk Erase (BE)
The Bulk Erase (BE) instruction sets all bits to 1 (FFh). Before it can be accepted, a Write
Enable (WREN) instruction must previously have been executed. After the Write Enable
(WREN) instruction has been decoded, the device sets the Write Enable Latch (WEL).
The Bulk Erase (BE) instruction is entered by driving Chip Select (S) Low, followed by the
instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the entire
duration of the sequence.
The instruction sequence is shown in Figure 16.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Bulk Erase instruction is not executed. As soon as Chip Select (S)
is driven High, the self-timed Bulk Erase cycle (whose duration is t ) is initiated. While the
BE
Bulk Erase cycle is in progress, the Status Register may be read to check the value of the
Write In Progress (WIP) bit. The Write In Progress (WIP) bit is 1 during the self-timed Bulk
Erase cycle, and is 0 when it is completed. At some unspecified time before the cycle is
completed, the Write Enable Latch (WEL) bit is reset.
The Bulk Erase (BE) instruction is executed only if all Block Protect (BP2, BP1, BP0) bits are
0. The Bulk Erase (BE) instruction is ignored if one, or more, sectors are protected.
Figure 16. Bulk Erase (BE) instruction sequence
S
0
1
2
3
4
5
6
7
C
D
Instruction
AI03752D
31/53
Instructions
M25P40
6.11
Deep Power-down (DP)
Executing the Deep Power-down (DP) instruction is the only way to put the device in the
lowest consumption mode (the Deep Power-down mode). It can also be used as an extra
software protection mechanism, while the device is not in active use, since in this mode, the
device ignores all Write, Program and Erase instructions.
Driving Chip Select (S) High deselects the device, and puts the device in the Standby Power
mode (if there is no internal cycle currently in progress). But this mode is not the Deep
Power-down mode. The Deep Power-down mode can only be entered by executing the
Deep Power-down (DP) instruction, subsequently reducing the standby current (from I
to
CC1
I
, as specified in Table 13).
CC2
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. This releases the device from this mode. The Release from Deep Power-down
and Read Electronic Signature (RES) instruction and the Read Identification (RDID)
instruction also allow the Electronic Signature of the device to be output on Serial Data
output (Q).
The Deep Power-down mode automatically stops at Power-down, and the device always
Powers-up in the Standby Power mode.
The Deep Power-down (DP) instruction is entered by driving Chip Select (S) Low, followed
by the instruction code on Serial Data input (D). Chip Select (S) must be driven Low for the
entire duration of the sequence.
The instruction sequence is shown in Figure 17.
Chip Select (S) must be driven High after the eighth bit of the instruction code has been
latched in, otherwise the Deep Power-down (DP) instruction is not executed. As soon as
Chip Select (S) is driven High, it requires a delay of t before the supply current is reduced
DP
to I
and the Deep Power-down mode is entered.
CC2
Any Deep Power-down (DP) instruction, while an Erase, Program or Write cycle is in
progress, is rejected without having any effects on the cycle that is in progress.
Figure 17. Deep Power-down (DP) instruction sequence
S
tDP
0
1
2
3
4
5
6
7
C
D
Instruction
Stand-by Mode
Deep Power-down Mode
AI03753D
32/53
M25P40
Instructions
6.12
Release from Deep Power-down and Read Electronic
Signature (RES)
Once the device has entered the Deep Power-down mode, all instructions are ignored
except the Release from Deep Power-down and Read Electronic Signature (RES)
instruction. Executing this instruction takes the device out of the Deep Power-down mode.
The instruction can also be used to read, on Serial Data output (Q), the 8-bit Electronic
Signature, whose value for the M25P40 is 12h.
Except while an Erase, Program or Write Status Register cycle is in progress, the Release
from Deep Power-down and Read Electronic Signature (RES) instruction always provides
access to the 8-bit Electronic Signature of the device, and can be applied even if the Deep
Power-down mode has not been entered.
Any Release from Deep Power-down and Read Electronic Signature (RES) instruction while
an Erase, Program or Write Status Register cycle is in progress, is not decoded, and has no
effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S) Low. The instruction code is followed
by 3 dummy bytes, each bit being latched-in on Serial Data input (D) during the rising edge
of Serial Clock (C). Then, the 8-bit Electronic Signature, stored in the memory, is shifted out
on Serial Data output (Q), each bit being shifted out during the falling edge of Serial Clock
(C).
The instruction sequence is shown in Figure 18.
The Release from Deep Power-down and Read Electronic Signature (RES) instruction is
terminated by driving Chip Select (S) High after the Electronic Signature has been read at
least once. Sending additional clock cycles on Serial Clock (C), while Chip Select (S) is
driven Low, cause the Electronic Signature to be output repeatedly.
When Chip Select (S) is driven High, the device is put in the Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by t
, and Chip Select (S)
RES2
must remain High for at least t
(max), as specified in Table 19. Once in the Standby
RES2
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
Driving Chip Select (S) High after the 8-bit instruction byte has been received by the device,
but before the whole of the 8-bit Electronic Signature has been transmitted for the first time
(as shown in Figure 19), still ensures that the device is put into Standby Power mode. If the
device was not previously in the Deep Power-down mode, the transition to the Standby
Power mode is immediate. If the device was previously in the Deep Power-down mode,
though, the transition to the Standby Power mode is delayed by t
, and Chip Select (S)
RES1
must remain High for at least t
(max), as specified in Table 19. Once in the Standby
RES1
Power mode, the device waits to be selected, so that it can receive, decode and execute
instructions.
33/53
Instructions
M25P40
Figure 18. Release from Deep Power-down and Read Electronic Signature (RES) instruction
sequence and data-out sequence
S
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38
C
tRES2
Instruction
3 Dummy Bytes
23 22 21
MSB
3
2
1
0
D
Q
Electronic Signature Out
High Impedance
7
6
5
4
3
2
0
1
MSB
Deep Power-down Mode
Stand-by Mode
AI04047C
1. The value of the 8-bit Electronic Signature, for the M25P40, is 12h.
Figure 19. Release from Deep Power-down (RES) instruction sequence
S
t
RES1
0
1
2
3
4
5
6
7
C
D
Instruction
High Impedance
Q
Deep Power-down Mode
Stand-by Mode
AI04078B
34/53
M25P40
Power-up and Power-down
7
Power-up and Power-down
At Power-up and Power-down, the device must not be selected (that is Chip Select (S) must
follow the voltage applied on V ) until V reaches the correct value:
CC
CC
●
V
V
(min) at Power-up, and then for a further delay of t
at Power-down
CC
SS
VSL
●
A safe configuration is provided in Section 3: SPI modes.
To avoid data corruption and inadvertent write operations during power-up, a Power On
Reset (POR) circuit is included. The logic inside the device is held reset while V is less
CC
than the Power On Reset (POR) threshold voltage, V – all operations are disabled, and
WI
the device does not respond to any instruction.
Moreover, the device ignores all Write Enable (WREN), Page Program (PP), Sector Erase
(SE), Bulk Erase (BE) and Write Status Register (WRSR) instructions until a time delay of
t
has elapsed after the moment that V rises above the V threshold. However, the
PUW
CC WI
correct operation of the device is not guaranteed if, by this time, V is still below V (min).
CC
CC
No Write Status Register, Program or Erase instructions should be sent until the later of:
●
t
t
after V passed the V threshold
CC WI
PUW
VSL
●
after V passed the V (min) level
CC
CC
These values are specified in Table 9.
If the delay, t
, has elapsed, after V has risen above V (min), the device can be
VSL
CC
CC
selected for READ instructions even if the t
delay is not yet fully elapsed.
PUW
At Power-up, the device is in the following state:
●
●
●
The device is in the Standby Power mode (not the Deep Power-down mode).
The Write Enable Latch (WEL) bit is reset.
The Write In Progress (WIP) bit is reset.
Normal precautions must be taken for supply rail decoupling, to stabilize the V supply.
CC
Each device in a system should have the V rail decoupled by a suitable capacitor close to
CC
the package pins. (Generally, this capacitor is of the order of 100 nF).
At Power-down, when V drops from the operating voltage, to below the Power On Reset
CC
(POR) threshold voltage, V , all operations are disabled and the device does not respond
WI
to any instruction. (The designer needs to be aware that if a Power-down occurs while a
Write, Program or Erase cycle is in progress, some data corruption can result.)
35/53
Power-up and Power-down
Figure 20. Power-up timing
M25P40
V
CC
V
(max)
CC
Program, Erase and Write Commands are Rejected by the Device
Chip Selection Not Allowed
V
(min)
CC
tVSL
Read Access allowed
Device fully
accessible
Reset State
of the
Device
V
WI
tPUW
time
AI04009C
Table 8.
Symbol
Power-up timing and V threshold
WI
Parameter
Min.
Max.
Unit
(1)
tVSL
VCC(min) to S low
10
1
µs
ms
V
(1)
tPUW
Time delay to Write instruction
Write Inhibit voltage (device grade 6)
Write Inhibit voltage (device grade 3)
10
2
1
(1)
VWI
1
2.2
V
1. These parameters are characterized only.
36/53
M25P40
Initial delivery state
8
Initial delivery state
The device is delivered with the memory array erased: all bits are set to 1 (each byte
contains FFh). The Status Register contains 00h (all Status Register bits are 0).
9
Maximum rating
Stressing the device above the rating listed in the Absolute maximum ratings table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the operating sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability. Refer also to the Numonyx SURE Program
and other relevant quality documents.
Table 9.
Symbol
Absolute maximum ratings
Parameter
Min.
Max.
Unit
TSTG
Storage temperature
–65
150
°C
°C
TLEAD
Lead temperature during soldering
see (1)
VCC
0.6
+
VIO
Input and output voltage (with respect to Ground)
–0.6
V
VCC
Supply voltage
–0.6
4.0
V
V
VESD
Electrostatic Discharge voltage (Human Body model)(2)
–2000
2000
1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the Numonyx
ECOPACK® 7191395 specification, and the European directive on Restrictions on Hazardous Substances
(RoHS) 2002/95/EU.
2. JEDEC Std JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
37/53
DC and ac parameters
M25P40
10
DC and ac parameters
This section summarizes the operating and measurement conditions, and the DC and AC
characteristics of the device. The parameters in the DC and AC characteristic tables that
follow are derived from tests performed under the Measurement Conditions summarized in
the relevant tables. Designers should check that the operating conditions in their circuit
match the measurement conditions when relying on the quoted parameters.
Table 10. Operating conditions
Symbol
Parameter
Min.
Max.
Unit
2.7
2.3
3.6
3.6
85
V
V
VCC
Supply voltage
Ambient operating temperature (device grade 6)
Ambient operating temperature (device grade 3)
–40
–40
TA
°C
125
Table 11. Data retention and endurance
Parameter
Condition
Device grade 6
Min.
Max.
Unit
100,000
10,000
20
Erase/Program
cycles
cycles per sector
years
Device grade 3
at 55°C
Data Retention
(1)
Table 12. Capacitance
Symbol
Parameter
Test condition
Min.
Max.
Unit
COUT
CIN
Output capacitance (Q)
VOUT = 0 V
VIN = 0 V
8
6
pF
pF
Input capacitance (other pins)
1. Sampled only, not 100% tested, at TA=25 °C and a frequency of 25 MHz.
38/53
M25P40
DC and ac parameters
Table 13. DC characteristics (device grade 6)
Test condition (in addition to
Symbol
Parameter
Min.
Max.
Unit
those in Table 10)
ILI
Input leakage current
Output leakage current
Standby current
2
2
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
50
10
Deep Power-down current
C = 0.1VCC / 0.9.VCC at
40 MHz and 50 MHz, Q = open
8
4
mA
mA
ICC3
Operating current (READ)
C = 0.1VCC / 0.9.VCC at
25 MHz, Q = open
ICC4
ICC5
ICC6
ICC7
VIL
Operating current (PP)
Operating current (WRSR)
Operating current (SE)
Operating current (BE)
Input low voltage
S = VCC
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
mA
V
15
15
–0.5
0.3VCC
VIH
Input high voltage
0.7VCC VCC+0.4
0.4
V
VOL
VOH
Output low voltage
IOL = 1.6 mA
V
Output high voltage
IOH = –100 µA
VCC–0.2
V
39/53
DC and ac parameters
M25P40
Table 14. DC characteristics (device grade 3)
Test condition (in addition to
Symbol
Parameter
Min(1)
Max(1) Unit
those in Table 10)
ILI
Input leakage current
Output leakage current
Standby current
2
2
µA
µA
µA
µA
ILO
ICC1
ICC2
S = VCC, VIN = VSS or VCC
S = VCC, VIN = VSS or VCC
100
50
Deep Power-down current
C = 0.1VCC / 0.9.VCC at 25 MHz,
Q = open
8
4
mA
mA
ICC3
Operating current (READ)
C = 0.1VCC / 0.9.VCC at 20 MHz,
Q = open
ICC4
ICC5
ICC6
ICC7
VIL
Operating current (PP)
Operating current (WRSR)
Operating current (SE)
Operating current (BE)
Input low voltage
S = VCC
S = VCC
S = VCC
S = VCC
15
15
mA
mA
mA
mA
V
15
15
– 0.5
0.3VCC
VIH
Input high voltage
0.7VCC VCC+0.4
0.4
V
VOL
VOH
Output low voltage
IOL = 1.6 mA
V
Output high voltage
IOH = –100 µA
VCC–0.2
V
1. This is preliminary data.
Table 15. Instruction times (device grade 6)
Test conditions specified in Table 10 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
tW
Write Status Register cycle time
5
15
ms
Page Program cycle time (256 bytes)
1.4
(1)
tPP
5
ms
0.4+
n*1/256
Page Program cycle time (n bytes)
tSE
tBE
Sector Erase cycle time
Bulk Erase cycle time
1
3
s
s
4.5
10
1. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤n ≤
256)
40/53
M25P40
DC and ac parameters
Table 16. Instruction times (device grade 3)
Test conditions specified in Table 10 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.(1) (2) Max.(2) Unit
tW
Write Status Register cycle time
8
15
ms
Page Program cycle time (256 bytes)
1.5
(3)
tPP
5
ms
0.4+
n*1.1/256
Page Program cycle time (n bytes)
tSE
tBE
Sector Erase cycle time
Bulk Erase cycle time
1
3
s
s
4.5
10
1. At 85 °C
2. Preliminary data.
3. When using the Page Program (PP) instruction to program consecutive bytes, optimized timings are
obtained with one sequence including all the bytes versus several sequences of only a few bytes. (1 ≤n ≤
256)
Table 17. AC measurement conditions
Symbol
Parameter
Load capacitance
Min.
Max.
Unit
CL
30
pF
ns
V
Input rise and fall times
5
Input pulse voltages
0.2VCC to 0.8VCC
0.3VCC to 0.7VCC
VCC / 2
Input timing reference voltages
Output timing reference voltages
V
V
1. Output Hi-Z is defined as the point where data out is no longer driven.
Figure 21. AC measurement I/O waveform
Input Levels
Input and Output
Timing Reference Levels
0.8V
CC
0.7V
CC
0.5V
CC
0.3V
CC
0.2V
CC
AI07455
Table 18. Which AC characteristics to use?
Device grade
VCC = 2.3 V to 3.6 V
VCC = 2.7 V to 3.6 V
AC characteristics at 25 MHz (Table 19)
Device grade 3
Device grade 6
1. Not applicable.
N/A(1)
AC characteristics at 40 MHz (Table 21) AC characteristics at 50 MHz (Table 20)
41/53
DC and ac parameters
M25P40
Table 19. AC characteristics (25 MHz operation, device grade 3, V min = 2.7 V)
CC
Test conditions specified in Table 10 and Table 17
Symbol Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock frequency for the following
fC
fR
fC
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, WRDI, RDSR, WRSR
D.C.
25
20
MHz
Clock frequency for READ instructions
D.C.
18
18
0.1
0.1
10
10
5
MHz
ns
(1)
tCH
tCLH Clock High time
tCLL Clock Low time
(1)
tCL
ns
Clock Rise time(3) (peak to peak)
V/ns
V/ns
ns
(2)
(2)
tCLCH
tCHCL
Clock Fall time(3) (peak to peak)
tCSS S Active Setup time (relative to C)
S Not Active Hold time (relative to C)
tDSU Data In Setup time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
ns
ns
tDH Data In Hold time
5
ns
S Active Hold time (relative to C)
S Not Active Setup time (relative to C)
tCSH S Deselect time
10
10
100
ns
ns
ns
(2)
tSHQZ
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
tDIS Output Disable time
15
15
ns
tV
tHO Output Hold time
HOLD Setup time (relative to C)
Clock Low to Output Valid
ns
0
ns
10
10
10
10
ns
HOLD Hold time (relative to C)
HOLD Setup time (relative to C)
HOLD Hold time (relative to C)
tLZ HOLD to Output Low-Z
tHZ HOLD to Output High-Z
Write Protect Setup time
ns
ns
ns
(2)
tHHQX
15
20
ns
(2)
tHLQZ
tWHSL
tSHWL
ns
(4)
(4)
20
ns
Write Protect Hold time
100
ns
(2)
tDP
S High to Deep Power-down mode
3
μs
S High to Standby Power mode without
Electronic Signature Read
(2)
tRES1
3 or 30(5)
μs
μs
S High to Standby Power mode with
Electronic Signature Read
(2)
tRES2
1.8 or 30(5)
1. tCH + tCL must be greater than or equal to 1/ fC
2. Value guaranteed by characterization, not 100% tested in production.
3. Expressed as a slew-rate.
4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
5. It is 30 µs in devices produced with the “X” process technology (grade 3 devices are only produced using
the “X” process technology). Details of how to find the process letter on the device marking are given in the
Application note AN1995.
42/53
M25P40
DC and ac parameters
Table 20. AC characteristics (50 MHz operation, device grade 6, V min = 2.7 V)
CC
50 MHz available only in products with Process Technology code X(1)
Test conditions specified in Table 10 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock frequency for the following
fC
fR
fC
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR
D.C.
50
25
MHz
Clock frequency for READ instructions
Clock High time
D.C.
9
MHz
ns
(2)
tCH
tCLH
tCLL
(2)
tCL
Clock Low time
9
ns
(3)
tCLCH
Clock Rise time(4) (peak to peak)
Clock Fall time(4) (peak to peak)
S Active Setup time (relative to C)
S Not Active Hold time (relative to C)
Data In Setup time
0.1
0.1
5
V/ns
V/ns
ns
(3)
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS
5
ns
tDSU
tDH
2
ns
Data In Hold time
5
ns
S Active Hold time (relative to C)
S Not Active Setup time (relative to C)
S Deselect time
5
ns
5
ns
tCSH
tDIS
tV
100
ns
(3)
tSHQZ
Output Disable time
8
8
ns
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
Clock Low to Output Valid
Output Hold time
ns
tHO
0
5
5
5
5
ns
HOLD Setup time (relative to C)
HOLD Hold time (relative to C)
HOLD Setup time (relative to C)
HOLD Hold time (relative to C)
HOLD to Output Low-Z
ns
ns
ns
ns
(3)
tHHQX
tLZ
8
8
ns
(3)
tHLQZ
tHZ
HOLD to Output High-Z
ns
(5)
tWHSL
Write Protect Setup time
Write Protect Hold time
20
ns
(5)
tSHWL
100
ns
(3)
tDP
S High to Deep Power-down mode
3
µs
S High to Standby Power mode without
Electronic Signature Read
(3)
tRES1
30
µs
µs
S High to Standby Power mode with
Electronic Signature Read
(3)
tRES2
30
1. Details of how to find the date of marking are given in Application Note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
43/53
DC and ac parameters
M25P40
Table 21. AC characteristics (40 MHz operation, device grade 6, V min = 2.3 V)
CC
Extended VCC range available only in products with Process Technology code X(1)
Test conditions specified in Table 10 and Table 17
Symbol
Alt.
Parameter
Min.
Typ.
Max.
Unit
Clock frequency for the following
fC
fR
fC
instructions: FAST_READ, PP, SE, BE, DP,
RES, WREN, RDID, WRDI, RDSR, WRSR
D.C.
40
25
MHz
Clock frequency for READ instructions
Clock High time
D.C.
11
11
0.1
0.1
5
MHz
ns
(2)
tCH
tCLH
tCLL
(2)
tCL
Clock Low time
ns
(3)
tCLCH
Clock Rise time(4) (peak to peak)
Clock Fall time(4) (peak to peak)
S Active Setup time (relative to C)
S Not Active Hold time (relative to C)
Data In Setup time
V/ns
V/ns
ns
(3)
tCHCL
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL
tCSS
5
ns
tDSU
tDH
2
ns
Data In Hold time
5
ns
S Active Hold time (relative to C)
S Not Active Setup time (relative to C)
S Deselect time
5
ns
5
ns
tCSH
tDIS
tV
100
ns
(3)
tSHQZ
Output Disable time
8
8
ns
tCLQV
tCLQX
tHLCH
tCHHH
tHHCH
tCHHL
Clock Low to Output Valid
Output Hold time
ns
tHO
0
5
5
5
5
ns
HOLD Setup time (relative to C)
HOLD Hold time (relative to C)
HOLD Setup time (relative to C)
HOLD Hold time (relative to C)
HOLD to Output Low-Z
ns
ns
ns
ns
(3)
tHHQX
tLZ
8
8
ns
(3)
tHLQZ
tHZ
HOLD to Output High-Z
ns
(5)
tWHSL
Write Protect Setup time
Write Protect Hold time
20
ns
(5)
tSHWL
100
ns
(3)
tDP
S High to Deep Power-down mode
3
µs
S High to Standby Power mode without
Electronic Signature Read
(3)
tRES1
30
µs
µs
S High to Standby Power mode with
Electronic Signature Read
(3)
tRES2
30
1. Details of how to find the date of marking are given in Application Note, AN1995.
2. tCH + tCL must be greater than or equal to 1/ fC
3. Value guaranteed by characterization, not 100% tested in production.
4. Expressed as a slew-rate.
5. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1.
44/53
M25P40
DC and ac parameters
Figure 22. Serial input timing
tSHSL
tSHCH
tCHCL
S
tCHSL
tSLCH
tCHSH
C
tDVCH
tCHDX
tCLCH
MSB IN
LSB IN
D
Q
High Impedance
Figure 23. Write Protect setup and hold timing during WRSR when SRWD = 1
W
tSHWL
tWHSL
S
C
D
High Impedance
Q
AI07439
45/53
DC and ac parameters
Figure 24. Hold timing
M25P40
S
tHLCH
tCHHH
tCHHL
tHLQZ
tHHCH
C
tHHQX
Q
D
HOLD
AI02032
Figure 25. Output timing
S
tCH
C
tCLQV
tCLQV
tCL
tSHQZ
tCLQX
Q
tCLQX
LSB OUT
tQLQH
tQHQL
ADDR.
LSB IN
D
AI01449e
46/53
M25P40
Package mechanical
11
Package mechanical
Figure 26. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width, package
outline
h x 45˚
A2
A
c
ccc
b
e
0.25 mm
D
GAUGE PLANE
k
8
1
E1
E
L
A1
L1
SO-A
1. Drawing is not to scale.
2. The ‘1’ that appears in the top view of the package shows the position of pin 1.
Table 22. SO8 narrow – 8 lead plastic Small Outline, 150 mils body width,
package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
b
1.75
0.25
0.069
0.010
0.10
1.25
0.28
0.17
0.004
0.049
0.011
0.007
0.48
0.23
0.10
5.00
6.20
4.00
–
0.019
0.009
0.004
0.197
0.244
0.157
–
c
ccc
D
4.90
6.00
3.90
1.27
4.80
5.80
3.80
–
0.193
0.236
0.154
0.050
0.189
0.228
0.150
–
E
E1
e
h
0.25
0°
0.50
8°
0.010
0°
0.020
8°
k
L
0.40
1.27
0.016
0.050
L1
1.04
0.041
47/53
Package mechanical
M25P40
Figure 27. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package outline
A
D
aaa C A
R1
D1
B
E
E1
E2
A2
e
b
2x
0.10 C
B
D2
0.10 C
A
θ
L
ddd
C
A
A1 A3
70-ME
1. Drawing is not to scale.
2. The circle in the top view of the package indicates the position of pin 1.
Table 23. VFQFPN8 (MLP8) 8-lead Very thin Fine pitch Quad Flat Package No lead,
6 × 5 mm, package mechanical data
millimeters
Min
inches
Min
Symbol
Typ
Max
Typ
Max
A
A1
A2
A3
b
0.85
0.80
0.00
1.00
0.05
0.0335
0.0315
0.0000
0.0394
0.0020
0.65
0.20
0.40
6.00
5.75
3.40
5.00
4.75
4.00
1.27
0.10
0.60
0.0256
0.0079
0.0157
0.2362
0.2264
0.1339
0.1969
0.1870
0.1575
0.0500
0.0039
0.0236
0.35
3.20
0.48
3.60
0.0138
0.1260
0.0189
0.1417
D
D1
D2
E
E1
E2
e
3.80
–
4.30
–
0.1496
–
0.1693
–
R1
L
0.00
0.50
0.0000
0.0197
0.75
12°
0.0295
12°
Q
aaa
bbb
ddd
0.15
0.10
0.05
0.0059
0.0039
0.0020
48/53
M25P40
Part numbering
12
Part numbering
Table 24. Ordering information scheme
Example:
M25P40
–
V MN
6
T
P
/X
Device Type
M25P = Serial Flash memory for Code Storage
Device Function
40 = 4 Mbit (512 K x 8)
Operating Voltage
V = VCC = 2.3 V to 3.6 V
Package
MN = SO8 (150 mil width)
MP = VFQFPN8 6 x 5 mm (MLP8)
Device grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow
3
(1) = Device tested with High Reliability Certified Flow(2)
.
Automotive temperature range (–40 to 125 °C)
Option
blank = Standard Packing
T = Tape and Reel Packing
Plating technology
P or G = ECOPACK® (RoHS compliant)
Process(3)
/X = T7Y
1. Device grade 3 available in an SO8 ECOPACK® (RoHS compliant) package.
2. Numonyx strongly recommends the use of the Automotive Grade devices for use in an automotive
environment. The High Reliability Certified Flow (HRCF) is described in the quality note QNEE9801.
Please ask your nearest Numonyx sales office for a copy.
3. The process letter (/X) is specified in the ordering information of grade 3 devices only.
For grade 6 devices, the process letter does not appear in the Ordering Information, it only appears on the
device package (marking) and on the shipment box. Please contact your nearest Numonyx Sales Office.
For more information on how to identify products by the Process Identification Letter, please refer to
AN1995: Serial Flash Memory Device Marking.
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest Numonyx Sales Office.
The category of second-Level Interconnect is marked on the package and on the inner box
label, in compliance with JEDEC Standard JESD97. The maximum ratings related to
soldering conditions are also marked on the inner box label.
49/53
Revision history
M25P40
13
Revision history
Table 25. Document revision history
Date
Revision
Changes
12-Apr-2001
25-May-2001
1.0
1.1
Document written.
Serial Paged Flash Memory renamed as Serial Flash Memory.
Changes to text: Signal Description/Chip Select; Hold Condition/1st para;
Protection modes; Release from Power-down and Read Electronic
Signature (RES); Power-up.
Repositioning of several tables and illustrations without changing their
contents.
11-Sep-2001
1.2
Power-up timing illustration; SO8W package removed.
Changes to tables: Abs Max Ratings/VIO; DC Characteristics/VIL.
FAST_READ instruction added. Document revised with new timings, VWI
ICC3 and clock slew rate. Descriptions of Polling, Hold Condition, Page
Programming, Release for Deep Power-down made more precise. Value
of tW(max) modified.
,
16-Jan-2002
12-Sep-2002
1.3
1.4
Clarification of descriptions of entering Standby Power mode from Deep
Power-down mode, and of terminating an instruction sequence or data-
out sequence.
VFQFPN8 package (MLP8) added. Document promoted to Preliminary
Data.
Typical Page Program time improved. Deep Power-down current
changed. Write Protect setup and hold times specified, for applications
that switch Write Protect to exit the Hardware Protection mode
immediately before a WRSR, and to enter the Hardware Protection mode
again immediately after.
13-Dec-2002
12-Jun-2003
24-Nov-2003
1.5
1.6
2.0
Document promoted from Preliminary Data to full Datasheet.
Table of contents, warning about exposed paddle on MLP8, and Pb-free
options added.
40 MHz AC Characteristics table included as well as 25 MHz. ICC3(max),
tSE(typ) and tBE(typ) values improved. Change of naming for VDFPN8
package.
Automotive range added. Soldering temperature information clarified for
RoHS compliant devices.
12-Mar-2004
05-Aug-2004
3.0
4.0
Device grade information clarified. Data-retention measurement
temperature corrected. Details of how to find the date of marking added.
Small text changes. Notes 2 and 3 removed from Table 24: Ordering
information scheme.
03-Jan-2005
01-Aug-2005
5.0
6.0
End timing line of tSHQZ modified in Figure 25: Output timing.
Updated Page Program (PP) instructions in Page Programming, Page
Program (PP), Instruction times (device grade 6) and Instruction times
(device grade 3).
50/53
M25P40
Revision history
Table 25. Document revision history (continued)
Date
Revision
Changes
50 MHz operation added (see Table 20: AC characteristics (50 MHz
operation, device grade 6, VCC min = 2.7 V)). All packages are
ECOPACK®. Blank option removed from under Plating technology in
Table 24: Ordering information scheme. MLP package renamed as
VFQFPN, silhouette and package mechanical drawing updated (see on
page 1 and Figure 27: VFQFPN8 (MLP8) 8-lead Very thin Fine pitch
Quad Flat Package No lead, 6 × 5 mm, package outline.
24-Oct-2005
7.0
Note 2 added below Figure 26 and note 1 added below Figure 27
t
RES1 and tRES2 modified in Table 20: AC characteristics (50 MHz
22-Dec-2005
8.0
operation, device grade 6, VCC min = 2.7 V).
Read Identification (RDID) added. Titles of Figure 27 and Table 23
corrected.
The data contained in Table 11, Table 16 and Table 19 is no longer
preliminary data.
Figure 3: Bus Master and memory devices on the SPI bus modified and
Note 2 added.
40 MHz frequency condition modified for ICC3 in Table 14: DC
characteristics (device grade 3).
Table 16: Instruction times (device grade 3) shows preliminary data.
14-Apr-2006
9
Condition changed for the Data Retention parameter in Table 11: Data
retention and endurance. VWI parameter for device grade 3 added to
Table 8: Power-up timing and VWI threshold.
SO8 package specifications updated (see Figure 26 and Table 22).
/X Process added to Table 24: Ordering information scheme.
t
RES1 and tRES2 parameter timings changed for devices produced with the
“X” process technology in Table 19 and Table 19.
05-Jun-2006
18-Dec-2006
10
11
SO8 Narrow package specifications updated (see Figure 26 and
Table 22).
Hardware Write Protection feature added on page 1. Small text changes.
Section 2.7: VCC supply voltage and Section 2.8: VSS ground added.
Figure 3: Bus Master and memory devices on the SPI bus modified,
note 2 removed and replaced by explanatory paragraph.
WIP bit behavior specified at Power-up in Section 7: Power-up and
Power-down. TLEAD added to Table 9: Absolute maximum ratings and VIO
max modified.
VFQFPN8 package specifications updated (see Table 23 and Figure 27).
VCC voltage range from W17 2007 is extended to 2.3 V to 3.6 V.
Table 21: AC characteristics (33 MHz operation, device grade 6, VCCmin
=2.3 V) added.
Table 18: Which AC characteristics to use? added. AC characteristics at
40 MHz removed.
25-Jan-2007
15-May-2007
12
13
40 MHz operation added (see Table 21: AC characteristics (40 MHz
operation, device grade 6, VCC min = 2.3 V).
Removed the note below Table 10.
Removed “AC characteristics (33 MHz operation, device grade 6,
VCCmin =2.3 V)” Table.
51/53
Revision history
Table 25. Document revision history (continued)
M25P40
Date
Revision
Changes
Modified the note below Table 12.
Changed test condition for ICC3 in Table 13.
26-Jun-2007
10-Dec-2007
14
15
Changed clock frequency, from 20 to 25 MHz, in Table 20 and Table 21.
Applied Numonyx branding.
52/53
M25P40
Please Read Carefully:
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR
IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT
AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY
WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF
NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
Numonyx products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility
applications.
Numonyx may make changes to specifications and product descriptions at any time, without notice.
Numonyx, B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied,
by estoppel or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves
these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by
visiting Numonyx's website at http://www.numonyx.com.
Numonyx StrataFlash is a trademark or registered trademark of Numonyx or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 11/5/7, Numonyx, B.V., All Rights Reserved.
53/53
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