JS28F256P30TF [NUMONYX]
Flash, 16MX16, 110ns, PDSO56, LEAD FREE, TSOP-56;
| 型号： | JS28F256P30TF |
| 厂家： | 
NUMONYX B.V |
| 描述： | Flash, 16MX16, 110ns, PDSO56, LEAD FREE, TSOP-56 时钟 光电二极管 内存集成电路 闪存 |
| 文件： | 总91页 (文件大小：983K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NumonyxTM StrataFlash® Embedded Memory
(P30-65nm)
256-Mbit, 512-Mbit (256M/256M)
Datasheet
Product Features
High performance
Security
— 100 ns initial access for Easy BGA
— 110 ns initial access for TSOP
— 25 ns 16-word asynchronous-page read mode
— 52 MHz with zero WAIT states, 17ns clock-to-
data output synchronous-burst read mode
— 4-, 8-, 16-, and continuous-word options for
burst mode
— One-Time Programmable Register:
• 64 unique factory device identifier bits
• 2112 user-programmable OTP bits
— Absolute write protection: V = V
PP
SS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Buffered Enhanced Factory Programming
(BEFP) at 2.0 MByte/s (Typ) using 512-word
buffer
— Password Access feature
Software
— 20 µs (Typ) program suspend
— 20 µs (Typ) erase suspend
— Numonyx™ Flash Data Integrator optimized
— Basic Command Set and Extended Function
Interface (EFI) Command Set compatible
— Common Flash Interface capable
— 1.8 V buffered programming at 1.5MByte/s
(Typ) using 512-word buffer
Architecture
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
Density and Packaging
— 56-Lead TSOP package (256-Mbit only)
— 64-Ball Easy BGA package (256, 512-Mbit)
— Numonyx™ QUAD+ SCSP (256, 512-Mbit)
— 16-bit wide data bus
— 128-KByte main blocks
— Blank Check to verify an erased block
Voltage and Power
Quality and Reliability
— V (core) voltage: 1.7 V – 2.0 V
CC
CCQ
— Operating temperature: –40 °C to +85 °C
— Minimum 100,000 erase cycles per block
— ETOX™ X process technology
— V
(I/O) voltage: 1.7 V – 3.6 V
— Standby current: 65 µA (Typ) for 256-Mbit;
— 52 MHz continuos synchronous read current:
21mA (Typ)/24mA(Max)
Datasheet
1
Apr 2009
Order Number: 320002-08
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHATSOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the presented
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting
Numonyx's website at http://www.numonyx.com.
Numonyx, the Numonyx logo, and StrataFlash are trademarks or registered trademarks of Numonyx B.V. or its subsidiaries in other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2009, Numonyx, B.V., All Rights Reserved.
Datasheet
2
Apr 2009
Order Number: 320002-08
P30 - 65 nm
Contents
1.0 Functional Description...............................................................................................5
1.1
1.2
1.3
1.4
Introduction .......................................................................................................5
Overview ...........................................................................................................5
Virtual Chip Enable Description..............................................................................6
Memory Maps .....................................................................................................7
2.0 Package Information.................................................................................................8
2.1
2.2
2.3
56-Lead TSOP.....................................................................................................8
64-Ball Easy BGA Package.................................................................................. 10
QUAD+ SCSP Packages...................................................................................... 11
3.0 Ballouts................................................................................................................... 13
4.0 Signals .................................................................................................................... 16
4.1
Dual-Die Configurations ..................................................................................... 18
5.0 Bus Operations........................................................................................................ 19
5.1
5.2
5.3
5.4
5.5
Reads.............................................................................................................. 19
Writes.............................................................................................................. 19
Output Disable.................................................................................................. 19
Standby........................................................................................................... 20
Reset............................................................................................................... 20
6.0 Command Set .......................................................................................................... 21
6.1
6.2
Device Command Codes..................................................................................... 21
Device Command Bus Cycles .............................................................................. 22
7.0 Read Operation........................................................................................................ 25
7.1
7.2
7.3
7.4
Asynchronous Page-Mode Read........................................................................... 25
Synchronous Burst-Mode Read............................................................................ 25
Read Device Identifier........................................................................................ 26
Read CFI.......................................................................................................... 26
8.0 Program Operation.................................................................................................. 27
8.1
8.2
8.3
8.4
8.5
8.6
Word Programming ........................................................................................... 27
Buffered Programming....................................................................................... 27
Buffered Enhanced Factory Programming.............................................................. 28
Program Suspend.............................................................................................. 30
Program Resume............................................................................................... 31
Program Protection............................................................................................ 31
9.0 Erase Operations ..................................................................................................... 32
9.1
9.2
9.3
9.4
9.5
Block Erase ...................................................................................................... 32
Blank Check ..................................................................................................... 32
Erase Suspend.................................................................................................. 33
Erase Resume................................................................................................... 33
Erase Protection................................................................................................ 33
10.0 Security Modes........................................................................................................ 34
10.1 Block Locking.................................................................................................... 34
10.2 Selectable One-Time Programmable Blocks........................................................... 36
10.3 Password Access ............................................................................................... 36
11.0 Registers................................................................................................................. 37
11.1 Read Status Register ......................................................................................... 37
11.2 Read Configuration Register................................................................................ 38
Datasheet
3
Apr 2009
Order Number: 320002-08
P30 - 65 nm
11.3 One-Time-Programmable (OTP) Registers .............................................................44
12.0 Power and Reset Specifications ...............................................................................47
12.1 Power-Up and Power-Down.................................................................................47
12.2 Reset Specifications ...........................................................................................47
12.3 Power Supply Decoupling....................................................................................48
13.0 Maximum Ratings and Operating Conditions ............................................................49
13.1 Absolute Maximum Ratings .................................................................................49
13.2 Operating Conditions..........................................................................................49
14.0 Electrical Specifications ...........................................................................................50
14.1 DC Current Characteristics..................................................................................50
14.2 DC Voltage Characteristics ..................................................................................51
15.0 AC Characteristics....................................................................................................52
15.1 AC Test Conditions.............................................................................................52
15.2 Capacitance ......................................................................................................53
15.3 AC Read Specifications .......................................................................................53
15.4 AC Write Specifications.......................................................................................58
16.0 Program and Erase Characteristics...........................................................................62
17.0 Ordering Information...............................................................................................63
17.1 Discrete Products...............................................................................................63
17.2 SCSP Products...................................................................................................64
A
B
C
Supplemental Reference Information.......................................................................65
A.1
A.2
A.3
Common Flash Interface Tables...........................................................................65
Flowcharts........................................................................................................77
Write State Machine...........................................................................................85
Conventions - Additional Information ......................................................................89
B.1
B.2
B.3
Conventions......................................................................................................89
Acronyms .........................................................................................................89
Nomenclature....................................................................................................90
Revision History.......................................................................................................91
Datasheet
4
Apr 2009
Order Number: 320002-08
P30-65nm
1.0
Functional Description
1.1
Introduction
This document provides information about the NumonyxTM StrataFlash® Embedded
Memory (P30-65nm) product and describes its features, operations, and specifications.
The NumonyxTM StrataFlash® Embedded Memory (P30-65nm) is the latest generation
of Numonyx™ StrataFlash® memory devices. P30-65nm device will be offered in 64-
Mbit up through 2-Gbit densities. This document covers specifically 256-Mbit and 512-
Mbit (256M/256M) product information. Benefits include more density in less space,
high-speed interface device, and support for code and data storage. Features include
high-performance synchronous-burst read mode, fast asynchronous access times, low
power, flexible security options, and three industry-standard package choices. The P30-
65nm product family is manufactured using Numonyx™ 65nm ETOX™ X process
technology.
1.2
Overview
This section provides an overview of the features and capabilities of the P30-65nm.
The P30-65nm family devices provides high performance at low voltage on a 16-bit
data bus. Individually erasable memory blocks are sized for optimum code and data
storage.
Upon initial power up or return from reset, the device defaults to asynchronous page-
mode read. Configuring the Read Configuration Register enables synchronous burst-
mode reads. In synchronous burst mode, output data is synchronized with a user-
supplied clock signal. A WAIT signal provides easy CPU-to-flash memory
synchronization.
In addition to the enhanced architecture and interface, the device incorporates
technology that enables fast factory program and erase operations. Designed for low-
voltage systems, the P30-65nm supports read operations with VCC at 1.8 V, and erase
and program operations with VPP at 1.8 V or 9.0 V. Buffered Enhanced Factory
Programming (BEFP) provides the fastest flash array programming performance with
VPP at 9.0 V, which increases factory throughput. With VPP at 1.8 V, VCC and VPP can be
tied together for a simple, ultra low power design. In addition to voltage flexibility, a
dedicated VPP connection provides complete data protection when VPP ≤ VPPLK
.
A Command User Interface (CUI) is the interface between the system processor and all
internal operations of the device. An internal Write State Machine (WSM) automatically
executes the algorithms and timings necessary for block erase and program. A Status
Register indicates erase or program completion and any errors that may have occurred.
An industry-standard command sequence invokes program and erase automation. Each
erase operation erases one block. The Erase Suspend feature allows system software to
pause an erase cycle to read or program data in another block. Program Suspend
allows system software to pause programming to read other locations. Data is
programmed in word increments (16 bits).
The P30-65nm protection register allows unique flash device identification that can be
used to increase system security. The individual Block Lock feature provides zero-
latency block locking and unlocking. The P30-65nm device adds enhanced protection
via Password Access; this new feature allows write and/or read access protection of
user-defined blocks. In addition, the P30-65nm device also provides backward
compatible One-Time Programmable (OTP) security feature.
Datasheet
5
Apr 2009
Order Number: 320002-08
P30-65nm
1.3
Virtual Chip Enable Description
The P30-65nm 512Mbit devices employ a Virtual Chip Enable which combines two 256-
Mbit die with a common chip enable, F1-CE# for QUAD+ packages or CE# for Easy BGA
packages. (Refer to Figure 9 on page 18 and Figure 10 on page 18). The maximum
address bit is then used to select between the die pair with F1-CE# / CE# asserted
depending upon the package option used. When chip enable is asserted and The
maximum address bit is low (VIL), The lower parameter die is selected; when chip
enable is asserted and the maximum address bit is high (VIH), the upper parameter die
is selected. Refer to Table 1 and Table 2 for additional details.
Table 1:
Virtual Chip Enable Truth Table for 512 Mb (QUAD+ Package)
Die Selected
F1-CE#
A24
Lower Param Die
Upper Param Die
L
L
L
H
Table 2:
Virtual Chip Enable Truth Table for 512 Mb (Easy BGA Packages)
Die Selected
CE#
A25
Lower Param Die
Upper Param Die
L
L
L
H
Datasheet
6
Apr 2009
Order Number: 320002-08
P30-65nm
1.4
Memory Maps
Figure 1: P30-65nm Memory Map
A<24:1 > 256 Mbit
:
A<24:1 > 256 Mbit
16- Kword Block 258
FFC 000– FFFFFF
FF 8000– FFBFFF
FF 4000– FF7FFF
FF 0000– FF3FFF
FF0000- FFFFFF
64- Kword Block
258
16- Kword Block 257
256
16- Kword Block
16- Kword Block 255
FE0000– FEFFFF
64- Kword Block 254
64- Kword Block 130
7F 0000- 7FFFFF
3 F0000- 3FFFFF
64- Kword Block 66
020000– 02 FFFF
64- Kword Block
64- Kword Block
5
010000 – 01 FFFF
00C000– 00 FFFF
4
3
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
008000– 00 BFFF
004000– 007FFF
2
1
64- Kword Block
64- Kword Block
1
0
010000– 01 FFFF
000000– 00 FFFF
0
000000– 003FFF
Bottom Boot
Top Boot 256 Mbit
Word Wide (x16) Mode
Word Wide (x16) Mode
A<25:1> 512 Mbit (256/256)
1FFC000 - 1FFFFFF
1FF8000 - 1FFBFFF
1FF4000 - 1FF7FFF
1FF0000 - 1FF3FFF
16- Kword Block 517
16- Kword Block 516
16- Kword Block 515
16- Kword Block 514
1FE0000 - 1FEFFFF
1FD0000 - 1FDFFFF
64- Kword Block 513
512
64- Kword Block
0020000 - 002FFFF
0010000 - 001FFFF
64- Kword Block
64- Kword Block
5
4
000C000 - 000FFFF
0008000 - 000BFFF
0004000 - 0007FFF
0000000 - 0003FFF
16- Kword Block
16- Kword Block
16- Kword Block
16- Kword Block
3
2
1
0
512 Mbit (256/256)
Word Wide (x16) Mode
Datasheet
7
Apr 2009
Order Number: 320002-08
P30-65nm
2.0
Package Information
2.1
56-Lead TSOP
Figure 2: TSOP Mechanical Specifications(256-Mbit)
Z
A
2
See Note 2
See Notes 1 and 3
Pin 1
e
See Detail B
E
Y
D
1
A
1
D
Seating
Plane
See Detail A
A
Detail A
Detail B
C
0
b
L
Table 3:
TSOP Package Dimensions (Sheet 1 of 2)
Millimeters
Inches
Nom
Product Information
Symbol
Min
Nom
Max
Min
Max
Package Height
Standoff
A
-
-
1.200
-
-
-
0.047
-
A
0.050
0.965
0.100
0.100
18.200
13.800
-
-
0.002
0.038
0.004
0.004
0.717
0.543
-
-
1
2
Package Body Thickness
Lead Width
A
0.995
0.150
0.150
18.400
14.000
0.500
20.00
1.025
0.200
0.200
18.600
14.200
-
0.039
0.006
0.006
0.724
0.551
0.0197
0.787
0.040
0.008
0.008
0.732
0.559
-
b
Lead Thickness
Package Body Length
Package Body Width
Lead Pitch
C
D
1
E
e
Terminal Dimension
D
19.800
20.200
0.780
0.795
Datasheet
8
Apr 2009
Order Number: 320002-08
P30-65nm
Table 3:
TSOP Package Dimensions (Sheet 2 of 2)
Millimeters
Inches
Nom
Product Information
Symbol
Min
Nom
Max
Min
Max
Lead Tip Length
Lead Count
L
N
θ
0.500
0.600
56
0.700
-
0.020
0.024
56
0.028
-
-
0°
-
0°
Lead Tip Angle
3°
5°
3°
5°
Seating Plane Coplanarity
Lead to Package Offset
Notes:
Y
Z
-
-
0.100
0.350
-
-
0.004
0.014
0.150
0.250
0.006
0.010
1.
2.
3.
4.
One dimple on package denotes Pin 1.
If two dimples, then the larger dimple denotes Pin 1.
Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology
http://developer.Numonyx.com/design/flash/packtech.
Datasheet
9
Apr 2009
Order Number: 320002-08
P30-65nm
2.2
64-Ball Easy BGA Package
Figure 3: Easy BGA Mechanical Specifications (256/512-Mbit)
Ball A1
Ball A1
Corner
Corner
D
S1
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
b
e
E
G
H
G
H
Top View - Ball side down
A1
Bottom View - Ball Side Up
A2
A
Seating
Plane
Y
Note: Drawing not to scale
Table 4:
Easy BGA Package Dimensions
Millimeters
Nom
Inches
Product Information
Symbol
Min
Max
Min
Nom
Max
Package Height
A
A1
A2
b
-
0.250
-
-
1.200
-
-
-
0.0472
-
Ball Height
-
0.0098
-
-
Package Body Thickness
Ball (Lead) Width
0.780
0.430
10.000
13.000
1.000
64
-
0.0307
0.0169
0.3937
0.5118
0.0394
64
-
0.330
9.900
12.900
-
0.530
10.100
13.100
-
0.0130
0.3898
0.5079
-
0.0209
0.3976
0.5157
-
Package Body Width
Package Body Length
Pitch
D
E
e
Ball (Lead) Count
N
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along D
Corner to Ball A1 Distance Along E
Y
-
-
0.100
1.600
3.100
-
-
0.0039
0.0630
0.1220
S1
S2
1.400
2.900
1.500
3.000
0.0551
0.1142
0.0591
0.1181
Note: Daisy Chain Evaluation Unit information is at Numonyx™ Flash Memory Packaging Technology
http://developer.Numonyx.com/design/flash/packtech.
Datasheet
10
Apr 2009
Order Number: 320002-08
P30-65nm
2.3
QUAD+ SCSP Packages
Figure 4: 256-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.0 mm)
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
D
e
G
G
H
J
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball Up
A
Top View - Ball Down
A2
A1
Y
Drawing not to scale.
Note: Dimensions A1, A2, and b are preliminary
Millimeters
Inches
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Nom
-
-
0.740
0.350
11.00
8.00
0.80
88
Max
1.000
-
Min
-
Nom
-
-
0.0291
0.0138
0.4331
0.3150
0.0315
88
Max
0.0394
-
A
A1
A2
b
D
E
-
0.117
-
0.300
10.900
7.900
-
0.0046
-
0.0118
0.4291
0.3110
-
-
-
0.400
11.100
8.100
-
0.0157
0.4370
0.3189
-
e
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
-
-
0.100
1.300
1.200
-
-
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
Datasheet
11
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 5: 512-Mbit, 88-ball (80 active) QUAD+ SCSP Specifications (8x11x1.2 mm)
S1
A1 Index
Mark
1
2
3
4
5
6
7
8
8
7
6
5
4
3
2
1
S2
A
B
C
D
E
F
A
B
C
D
E
F
D
e
G
G
H
J
H
J
K
K
L
L
M
M
b
E
Bottom View - Ball Up
A
Top View - Ball Down
A2
A1
Y
Drawing not to scale.
Millimeters
Nom
-
Inches
Nom
-
Dimensions
Package Height
Ball Height
Package Body Thickness
Ball (Lead) Width
Package Body Length
Package Body Width
Pitch
Symbol
Min
Max
1.200
-
Min
-
Max
0.0472
-
A
A1
A2
b
D
E
-
0.200
-
0.325
10.900
7.900
-
-
0.0079
-
0.0128
0.4291
0.3110
-
-
0.860
0.375
11.000
8.000
0.800
88
-
0.0339
0.0148
0.4331
0.3150
0.0315
88
-
0.425
11.100
8.100
-
0.0167
0.4370
0.3189
-
e
N
Ball (Lead) Count
-
-
-
-
Seating Plane Coplanarity
Corner to Ball A1 Distance Along E
Corner to Ball A1 Distance Along D
Y
S1
S2
-
-
0.100
1.300
1.200
-
-
0.0039
0.0512
0.0472
1.100
1.000
1.200
1.100
0.0433
0.0394
0.0472
0.0433
Datasheet
12
Apr 2009
Order Number: 320002-08
P30-65nm
3.0
Ballouts
Figure 6: 56-Lead TSOP Pinout (256-Mbit)
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
WAIT
A17
1
2
3
4
5
6
7
8
A16
A15
DQ15
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
ADV#
CLK
A14
A13
A12
A11
A10
A9
A23
A22
A21
VSS
RFU
WE#
WP#
A20
A19
A18
A8
A7
A6
A5
A4
A3
A2
A24
RFU
VSS
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Numonyx
StrataFlash Embedded Memory(P30)
™
®
RST#
VPP
56-Lead TSOP Pinout
14 mm x 20 mm
DQ11
DQ3
DQ10
DQ2
VCCQ
DQ9
DQ1
DQ8
DQ0
VCC
OE#
VSS
Top View
CE#
A1
Notes:
1.
2.
3.
A1 is the least significant address bit.
A24 is valid for 256-Mbit densities; otherwise, it is a no connect (NC).
No Internal Connection on Pin 13; it may be driven or floated. For legacy designs, it is VCC pin and can be tied to Vcc.
Datasheet
13
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 7: 64-Ball Easy BGA Ballout (256/512-Mbit)
5
8
8
5
1
2
3
4
6
7
7
6
4
3
2
1
A
B
C
D
A
A1
A2
A3
A4
A6
A8
VPP A13 VCC A18 A22
A22 A18 VCC A13 VPP A8
RFU A19 A25 A14 CE# A9
A21 A20 WP# A15 A12 A10
A17 A16 VCCQ VCCQ RST# A11
A6
A1
B
C
VSS A9 CE# A14 A25 A19 RFU
VSS A2
A7
A10 A12 A15 WP# A20 A21
A7
A5
A3
A4
D
E
A5 A11 RST# VCCQ VCCQ A16 A17
E
F
DQ8 DQ1 DQ9 DQ3 DQ4 CLK DQ15 RFU
RFU DQ0 DQ10 DQ11 DQ12 ADV# WAIT OE#
A23 RFU DQ2 VCCQ DQ5 DQ6 DQ14 WE#
RFU DQ15 CLK DQ4 DQ3 DQ9 DQ1 DQ8
OE# WAIT ADV# DQ12 DQ11 DQ10 DQ0 RFU
WE# DQ14 DQ6 DQ5 VCCQ DQ2 RFU A23
F
G
H
G
H
RFU VSS VCC VSS DQ13 VSS DQ7 A24
A24 DQ7 VSS DQ13 VSS VCC VSS RFU
Easy BGA
Easy BGA
Top View- Ball side down
Bottom View- Ball side up
Notes:
1.
2.
3.
A1 is the least significant address bit.
A24 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
A25 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
Datasheet
14
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 8: QUAD+ SCSP Ballout and Signals
Pin 1
1
DU
2
3
4
5
6
7
8
DU
Depop
A19
Depop
VSS
Depop
VCC
RFU
RFU
ADV#
WE#
DQ5
DQ12
DQ4
RFU
VSS
Depop
VCC
CLK
RFU
A20
DU
DU
A
B
C
D
E
F
A
B
C
D
E
F
A4
A18
RFU
A17
A7
A21
A22
A9
A11
A5
A23
VSS
A12
A3
A24
VPP
A13
A2
RFU
RFU
DQ2
DQ1
DQ9
RFU
VCCQ
WP#
RST#
DQ10
DQ3
DQ11
RFU
VCC
A10
A14
WAIT
DQ7
DQ15
VCCQ
VSS
A15
A1
A6
A8
A16
G
H
J
A0
DQ8
DQ0
OE#
RFU
VSS
DQ13
DQ14
DQ6
VCC
VSS
F2-CE#
F2-OE#
VCCQ
RFU
VSS
G
H
J
RFU
RFU
F1-CE#
VSS
K
L
K
L
M
DU
DU
Depop
Depop
Depop
Depop
DU
DU
M
1
2
3
4
5
6
7
8
Top View - Ball Side Down
Control Signals
De-Populated Ball
Reserved for Future Use
Do Not Use
Address
Data
Power/Ground
Legends:
Notes:
1.
2.
3.
4.
A23 is valid for 256-Mbit densities and above; otherwise, it is a no connect (NC).
A24 is valid for 512-Mbit densities; otherwise, it is a no connect (NC).
F2-CE# and F2-OE# are no connect (NC) for all densities.
A0 is LSB for Address.
Datasheet
15
Apr 2009
Order Number: 320002-08
P30-65nm
4.0
Signals
This section has signal descriptions for the various P30-65nm packages.
Table 5:
TSOP and Easy BGA Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Device address inputs. 256-Mbit: A[24:1]; 512-Mbit: A[25:1]. Note: The
A[MAX:1]
DQ[15:0]
Input
virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is
accomplished by setting A[25] high (V ).
IH
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input/
Output
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When asserted,
flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
CE#
CLK
Input
Input
WARNING: Chip enable must be driven high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
OE#
Input
Input
cycles. OE# high places the data outputs and WAIT in High-Z.
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
RST#
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR.10, WT) determines its polarity when asserted. WAIT’s active output is V or
OL
V
when CE# and OE# are V . WAIT is high-Z if CE# or OE# is V .
OH
I
L
I
H
WAIT
Output
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
•
In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
WE#
WP#
Input
Input
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V ≤ V
. Block erase and program at invalid V
PP
PPLK
PP
voltages should not be attempted.
Set V = V
for in-system program and erase operations. To accommodate resistor or diode drops
PP
PPL
Power/
Input
VPP
VCC
from the system supply, the V level of V can be as low as V
min. V must remain above V
IH
PP
PPL PP PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
Power
when V ≤ V
. Operations at invalid V voltages should not be attempted.
CC
LKO
CC
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
Datasheet
16
Apr 2009
Order Number: 320002-08
P30-65nm
Table 5:
TSOP and Easy BGA Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Do Not Use (DU) signal.
RFU
—
DU
NC
—
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
Table 6:
QUAD+ SCSP Signal Descriptions (Sheet 1 of 2)
Symbol
Type
Name and Function
ADDRESS INPUTS: Device address inputs. 256-Mbit: A[23:0]; 512-Mbit: A[24:0]. Note: The
A[MAX:0]
DQ[15:0]
Input
virtual selection of the 256-Mbit “Top parameter” die in the dual-die 512-Mbit configuration is
accomplished by setting A[24] high (V ).
IH
DATA INPUT/OUTPUTS: Inputs data and commands during write cycles; outputs data during
memory, Status Register, Protection Register, and Read Configuration Register reads. Data balls float
when the CE# or OE# are deasserted. Data is internally latched during writes.
Input/
Output
ADDRESS VALID: Active low input. During synchronous read operations, addresses are latched on
the rising edge of ADV#, or on the next valid CLK edge with ADV# low, whichever occurs first.
ADV#
Input
In asynchronous mode, the address is latched when ADV# going high or continuously flows through
if ADV# is held low.
WARNING: Designs not using ADV# must tie it to VSS to allow addresses to flow through.
Flash CHIP ENABLE: Active low input. CE# low selects the associated flash memory die. When
asserted, flash internal control logic, input buffers, decoders, and sense amplifiers are active. When
deasserted, the associated flash die is deselected, power is reduced to standby levels, data and
WAIT outputs are placed in high-Z state.
F1-CE#
CLK
Input
Input
WARNING: Chip enable must be driven high when device is not in use.
CLOCK: Synchronizes the device with the system’s bus frequency in synchronous-read mode.
During synchronous read operations, addresses are latched on the rising edge of ADV#, or on the
next valid CLK edge with ADV# low, whichever occurs first.
WARNING: Designs not using CLK for synchronous read mode must tie it to VCCQ or VSS.
OUTPUT ENABLE: Active low input. OE# low enables the device’s output data buffers during read
cycles. OE# high places the data outputs and WAIT in High-Z.
F1-OE#
RST#
Input
Input
RESET: Active low input. RST# resets internal automation and inhibits write operations. This
provides data protection during power transitions. RST# high enables normal operation. Exit from
reset places the device in asynchronous read array mode.
WAIT: Indicates data valid in synchronous array or non-array burst reads. Read Configuration
Register bit 10 (RCR.10, WT) determines its polarity when asserted. WAIT’s active output is V or
OL
V
when CE# and OE# are V . WAIT is high-Z if CE# or OE# is V .
OH
IL IH
WAIT
Output
•
In synchronous array or non-array read modes, WAIT indicates invalid data when asserted and
valid data when deasserted.
•
In asynchronous page mode, and all write modes, WAIT is deasserted.
WRITE ENABLE: Active low input. WE# controls writes to the device. Address and data are latched
WE#
WP#
Input
Input
on the rising edge of WE#.
WRITE PROTECT: Active low input. WP# low enables the lock-down mechanism. Blocks in lock-
down cannot be unlocked with the Unlock command. WP# high overrides the lock-down function
enabling blocks to be erased or programmed using software commands.
ERASE AND PROGRAM POWER: A valid voltage on this pin allows erasing or programming.
Memory contents cannot be altered when V ≤ V
. Block erase and program at invalid V
PP
PPLK
PP
voltages should not be attempted.
Set V = V
for in-system program and erase operations. To accommodate resistor or diode drops
PPL
PP
Power/
lnput
VPP
from the system supply, the V level of V can be as low as V
min. V must remain above V
IH
PP
PPL PP PPL
min to perform in-system flash modification. VPP may be 0 V during read operations.
V
can be applied to main blocks for 1000 cycles maximum and to parameter blocks for 2500
PPH
cycles. VPP can be connected to 9 V for a cumulative total not to exceed 80 hours. Extended use of
this pin at 9 V may reduce block cycling capability.
Datasheet
17
Apr 2009
Order Number: 320002-08
P30-65nm
Table 6:
QUAD+ SCSP Signal Descriptions (Sheet 2 of 2)
Symbol
Type
Name and Function
DEVICE CORE POWER SUPPLY: Core (logic) source voltage. Writes to the flash array are inhibited
VCC
Power
when V ≤ V
. Operations at invalid V voltages should not be attempted.
CC
LKO
CC
VCCQ
VSS
Power
Power
OUTPUT POWER SUPPLY: Output-driver source voltage.
GROUND: Connect to system ground. Do not float any VSS connection.
RESERVED FOR FUTURE USE: Reserved by Numonyx for future device functionality and
enhancement. These should be treated in the same way as a Do Not Use (DU) signal.
RFU
—
DU
NC
—
—
DO NOT USE: Do not connect to any other signal, or power supply; must be left floating.
NO CONNECT: No internal connection; can be driven or floated.
4.1
Dual-Die Configurations
Figure 9: 512-Mbit Easy BGA Block Diagram
Easy BGA 512-Mbit (Dual-Die) Top or Bottom Parameter
Configuration
CE#
Top Param Die
(256-Mbit)
RST#
VCC
VPP
WP#
OE#
WE#
VCCQ
VSS
CLK
ADV#
Bottom Param Die
(256-Mbit)
DQ[15:0]
WAIT
A[MAX:1]
Figure 10: 512-Mbit QUAD+ SCSP Block Diagram
QUAD+ 512-Mbit (Dual-Die) Top or Bottom Parameter
Configuration
F1-CE#
Top Param Die
(256-Mbit)
RST#
VCC
VPP
WP#
OE#
WE#
VCCQ
VSS
CLK
ADV#
Bottom Param Die
(256-Mbit)
DQ[15:0]
WAIT
A[MAX:0]
Note: Amax = VIH selects the Top parameter Die; Amax = VIL selects the Bottom Parameter Die.
Datasheet
18
Apr 2009
Order Number: 320002-08
P30-65nm
5.0
Bus Operations
CE# low and RST# high enable device read operations. The device internally decodes
upper address inputs to determine the accessed block. ADV# low opens the internal
address latches. OE# low activates the outputs and gates selected data onto the I/O
bus.
In asynchronous mode, the address is latched when ADV# goes high or continuously
flows through if ADV# is held low. In synchronous mode, the address is latched by the
first of either the rising ADV# edge or the next valid CLK edge with ADV# low (WE#
and RST# must be VIH; CE# must be VIL).
Bus cycles to/from the P30-65nm device conform to standard microprocessor bus
operations. Table 7 summarizes the bus operations and the logic levels that must be
applied to the device control signal inputs.
Table 7:
Bus Operations Summary
Bus Operation
RST#
CLK
ADV#
CE#
OE#
WE#
WAIT
DQ[15:0] Notes
Asynchronous
Synchronous
V
V
V
V
V
X
L
L
L
L
L
L
H
H
L
Output
Output
IH
Deasserted
Driven
Read
Write
Running
IH
IH
IH
IH
X
X
X
X
L
L
H
H
X
X
High-Z
High-Z
High-Z
High-Z
Input
High-Z
High-Z
High-Z
1
2
Output Disable
Standby
Reset
X
X
X
L
H
X
X
H
X
2
V
2,3
IL
Notes:
1.
Refer to the Table 9, “Command Bus Cycles” on page 23 for valid DQ[15:0] during a write
operation.
2.
3.
X = Don’t Care (H or L).
RST# must be at V ± 0.2 V to meet the maximum specified power-down current.
SS
5.1
5.2
Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, whichever occurs first. Table 9, “Command Bus Cycles” on page 23
shows the bus cycle sequence for each of the supported device commands, while
Table 8, “Command Codes and Definitions” on page 21 describes each command. See
Section 15.0, “AC Characteristics” on page 52 for signal-timing details.
Note: Write operations with invalid VCC and/or VPP voltages can produce spurious results and should
not be attempted.
5.3
Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and placed in a high-
impedance (High-Z) state, WAIT is also placed in High-Z.
Datasheet
19
Apr 2009
Order Number: 320002-08
P30-65nm
5.4
5.5
Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs after CE# is deasserted.
When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to consume active power until the program or erase operation is
completed.
Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defaults to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note: If RST# is asserted during a program or erase operation, the operation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer
valid, because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 15.0, “AC Characteristics” on page 52 for details
about signal-timing.
Datasheet
20
Apr 2009
Order Number: 320002-08
P30-65nm
6.0
Command Set
6.1
Device Command Codes
The system CPU provides control of all in-system read, write, and erase operations of
the device via the system bus. The on-chip Write State Machine (WSM) manages all
block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
Table 8:
Command Codes and Definitions (Sheet 1 of 2)
Mode
Code
Device Mode
Read Array
Description
0xFF
Places the device in Read Array mode. Array data is output on DQ[15:0].
Places the device in Read Status Register mode. The device enters this mode
after a program or erase command is issued. Status Register data is output
on DQ[7:0].
Read Status
Register
0x70
0x90
Read Device ID
or Read
Configuration
Register(RCR)
Places device in Read Device Identifier mode. Subsequent reads output
manufacturer/device codes, Configuration Register data, Block Lock status,
or Protection Register data on DQ[15:0].
Read
Places the device in Read CFI mode. Subsequent reads output Common Flash
Interface information on DQ[7:0].
0x98
0x50
Read CFI
Clear Status
Register
The WSM can only set Status Register error bits. The Clear Status Register
command is used to clear the SR error bits.
First cycle of a 2-cycle programming command; prepares the CUI for a write
operation. On the next write cycle, the address and data are latched and the
WSM executes the programming algorithm at the addressed location. During
program operations, the device responds only to Read Status Register and
Program Suspend commands. CE# or OE# must be toggled to update the
Status Register in asynchronous read. CE# or ADV# must be toggled to
update the Status Register Data for synchronous Non-array reads. The Read
Array command must be issued to read array data after programming has
finished.
Word Program
Setup
0x40
This command loads a variable number of words up to the buffer size of 512
words onto the program buffer.
0xE8
0xD0
Buffered Program
Write
The confirm command is issued after the data streaming for writing into the
buffer is done. This instructs the WSM to perform the Buffered Program
algorithm, writing the data from the buffer to the flash memory array.
Buffered Program
Confirm
First cycle of a 2-cycle command; initiates Buffered Enhanced Factory
Program mode (BEFP). The CUI then waits for the BEFP Confirm command,
0xD0, that initiates the BEFP algorithm. All other commands are ignored
when BEFP mode begins.
0x80
0xD0
BEFP Setup
If the previous command was BEFP Setup (0x80), the CUI latches the
address and data, and prepares the device for BEFP mode.
BEFP Confirm
First cycle of a 2-cycle command; prepares the CUI for a block-erase
operation. The WSM performs the erase algorithm on the block addressed by
the Erase Confirm command. If the next command is not the Erase Confirm
(0xD0) command, the CUI sets Status Register bits SR.4 and SR.5, and
places the device in read status register mode.
0x20
0xD0
Block Erase Setup
Erase
If the first command was Block Erase Setup (0x20), the CUI latches the
address and data, and the WSM erases the addressed block. During block-
erase operations, the device responds only to Read Status Register and Erase
Suspend commands. CE# or OE# must be toggled to update the Status
Register in asynchronous read. CE# or ADV# must be toggled to update the
Status Register Data for synchronous Non-array reads
Block Erase Confirm
Datasheet
21
Apr 2009
Order Number: 320002-08
P30-65nm
Table 8:
Command Codes and Definitions (Sheet 2 of 2)
Mode
Code
Device Mode
Description
This command issued to any device address initiates a suspend of the
currently-executing program or block erase operation. The Status Register
indicates successful suspend operation by setting either SR.2 (program
suspended) or SR.6 (erase suspended), along with SR.7 (ready). The Write
State Machine remains in the suspend mode regardless of control signal
states (except for RST# asserted).
Program or Erase
Suspend
0xB0
Suspend
This command issued to any device address resumes the suspended program
or block-erase operation.
0xD0
0x60
Suspend Resume
Block lock Setup
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits
SR.5 and SR.4, indicating a command sequence error.
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0x01
0xD0
0x2F
Block lock
Block Locking/
Unlocking
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
Block Unlock
Block Lock-Down
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the CUI for block lock
configuration changes. If the next command is not Block Lock (0x01), Block
Unlock (0xD0), or Block Lock-Down (0x2F), the CUI sets Status Register bits
SR.5 and SR.4, indicating a command sequence error.
0x60
Block lock Setup
If the previous command was Block Lock Setup (0x60), the addressed block
is locked.
0x01
0xD0
0x2F
Block lock
If the previous command was Block Lock Setup (0x60), the addressed block
is unlocked. If the addressed block is in a lock-down state, the operation has
no effect.
Protection
Block Unlock
Block Lock-Down
If the previous command was Block Lock Setup (0x60), the addressed block
is locked down.
First cycle of a 2-cycle command; prepares the device for a OTP register or
Lock Register program operation. The second cycle latches the register
address and data, and starts the programming algorithm to program data the
the OTP array.
OTP Register or
Lock Register
program setup
0xC0
0x60
0x03
First cycle of a 2-cycle command; prepares the CUI for device read
configuration. If the Set Read Configuration Register command (0x03) is not
the next command, the CUI sets Status Register bits SR.4 and SR.5,
indicating a command sequence error.
Read Configuration
Register Setup
Configuration
If the previous command was Read Configuration Register Setup (0x60), the
CUI latches the address and writes A[16:1] to the Read Configuration
Register. Following a Configure Read Configuration Register command,
subsequent read operations access array data.
Read Configuration
Register
First cycle of a 2-cycle command; initiates the Blank Check operation on a
main block.
0xBC
0xD0
Block Blank Check
Blank Check
Block Blank Check
Confirm
Second cycle of blank check command sequence; it latches the block address
and executes blank check on the main array block.
First cycle of a multiple-cycle command; initiate operation using extended
function interface. The second cycle is a Sub-Op-Code, the data written on
third cycle is one less than the word count; the allowable value on this cycle
are 0 through 511. The subsequent cycles load data words into the program
buffer at a specified address until word count is achieved.
Extended Function
Interface command
EFI
0xEB
6.2
Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the Command
User Interface (CUI). Several commands are used to modify array data including Word
Program and Block Erase commands. Writing either command to the CUI initiates a
Datasheet
22
Apr 2009
Order Number: 320002-08
P30-65nm
sequence of internally-timed functions that culminate in the completion of the
requested task. However, the operation can be aborted by either asserting RST# or by
issuing an appropriate suspend command.
Table 9:
Command Bus Cycles (Sheet 1 of 2)
First Bus Cycle
(1)
Second Bus Cycle
(1)
Bus
Cycles
Mode
Command
(2)
(2)
Oper
Addr
Data
Oper
Addr
Data
Read Array
1
Write
Write
DnA
DnA
0xFF
-
-
-
Read Device Identifier
Read CFI
≥ 2
0x90
0x98
Read
DBA + IA
ID
DBA + CFI-
A
Read
≥ 2
Write
DnA
Read
CFI-D
Read Status Register
Clear Status Register
Word Program
2
1
Write
Write
Write
Write
DnA
DnA
WA
0x70
0x50
0x40
0xE8
Read
-
DnA
-
SRD
-
2
Write
Write
WA
WA
WD
N - 1
(3)
Buffered Program
> 2
WA
Program
Buffered Enhanced Factory
Program (BEFP)
> 2
Write
Write
WA
BA
0x80
0x20
Write
Write
WA
BA
0xD0
0xD0
(4)
Erase
Block Erase
2
Program/Erase Suspend
Program/Erase Resume
Block Lock
1
1
2
2
2
2
2
2
2
2
Write
Write
Write
Write
Write
Write
Write
Write
Write
Write
DnA
DnA
BA
0xB0
0xD0
0x60
0x60
0x60
0x60
0x60
0x60
0xC0
0xC0
-
-
-
-
Suspend
-
-
Write
Write
Write
Write
Write
Write
Write
Write
BA
0x01
0xD0
0x2F
0x01
0xD0
0x2F
OTP-D
LRD
Block
Locking/
Unlocking
Block Unlock
BA
BA
Block Lock-down
Block Lock
BA
BA
BA
BA
Block Unlock
BA
BA
Protection
Block Lock-down
Program OTP register
Program Lock Register
BA
BA
PRA
LRA
OTP-RA
LRA
Configure Read Configuration
Register
Configuration
2
Write
RCD
0x60
Write
RCD
0x03
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Table 9:
Command Bus Cycles (Sheet 2 of 2)
First Bus Cycle
(1)
Second Bus Cycle
Bus
Command
Mode
Cycles
(2)
(1)
(2)
Oper
Addr
Data
0xBC
0xEB
Oper
Addr
Data
Blank Check Block Blank Check
Extended Function Interface
2
Write
BA
Write
BA
D0
Sub-Op
code
EFI
>2
Write
WA
Write
WA
(5)
command
Notes:
1.
First command cycle address should be the same as the operation’s target address.
DBA = Device Base Address (NOTE: needed for dual-die 512 Mb device)
DnA = Address within the device.
IA = Identification code address offset.
CFI-A = Read CFI address offset.
WA = Word address of memory location to be written.
BA = Address within the block.
OTP-RA = Protection Register address.
LRA = Lock Register address.
RCD = Read Configuration Register data on A[16:1].
ID = Identifier data.
2.
3.
CFI-D = CFI data on DQ[15:0].
SRD = Status Register data.
WD = Word data.
N = Word count of data to be loaded into the write buffer.
OTP-D = Protection Register data.
LRD = Lock Register data.
The second cycle of the Buffered Program Command is the word count of the data to be loaded into the write buffer. This
is followed by up to 512 words of data. Then the confirm command (0xD0) is issued, triggering the array programming
operation.
4.
5.
The confirm command (0xD0) is followed by the buffer data.
The second cycle is a Sub-Op-Code, the data written on third cycle is N-1; 1≤ N ≤ 512. The subsequent cycles load data
words into the program buffer at a specified address until word count is achieved, after the data words are loaded, the
final cycle is the confirm cycle 0xD0).
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7.0
Read Operation
The device supports two read modes: asynchronous page mode and synchronous burst
mode. Asynchronous page mode is the default read mode after device power-up or a
reset. The Read Configuration Register must be configured to enable synchronous burst
reads of the flash memory array (see Section 11.2, “Read Configuration Register” on
page 38).
The device can be in any of four read states: Read Array, Read Identifier, Read Status
or Read CFI. Upon power-up, or after a reset, the device defaults to Read Array. To
change the read state, the appropriate read command must be written to the device
(see Section 6.0, “Command Set” on page 21).
7.1
Asynchronous Page-Mode Read
Following a device power-up or reset, asynchronous page mode is the default read
mode and the device is set to Read Array. However, to perform array reads after any
other device operation (e.g. write operation), the Read Array command must be issued
in order to read from the flash memory array.
Asynchronous page-mode reads can only be performed when Read Configuration
Register bit RCR.15 is set (see Section 11.2, “Read Configuration Register” on page 38).
To perform an asynchronous page-mode read, an address is driven onto the Address
bus, and CE# and ADV# are asserted. WE# and RST# must already have been
deasserted. WAIT is deasserted during asynchronous page mode. ADV# can be driven
high to latch the address, or it must be held low throughout the read cycle. CLK is not
used for asynchronous page-mode reads, and is ignored. If only asynchronous reads
are to be performed, CLK should be tied to a valid VIH level, WAIT signal can be floated
and ADV# must be tied to ground. Array data is driven onto DQ[15:0] after an initial
access time tAVQV delay. (see Section 15.0, “AC Characteristics” on page 52).
In asynchronous page mode, sixteen data words are “sensed” simultaneously from the
flash memory array and loaded into an internal page buffer. The buffer word
corresponding to the initial address on the Address bus is driven onto DQ[15:0] after
the initial access delay. The lowest four address bits determine which word of the 16-
word page is output from the data buffer at any given time.
7.2
Synchronous Burst-Mode Read
To perform a synchronous burst-read, an initial address is driven onto the Address bus,
and CE# and ADV# are asserted. WE# and RST# must already have been deasserted.
ADV# is asserted, and then deasserted to latch the address. Alternately, ADV# can
remain asserted throughout the burst access, in which case the address is latched on
the next valid CLK edge while ADV# is asserted.
During synchronous array and non-array read modes, the first word is output from the
data buffer on the next valid CLK edge after the initial access latency delay (see Section
11.2.2, “Latency Count” on page 39). Subsequent data is output on valid CLK edges
following a minimum delay. However, for a synchronous non-array read, the same word
of data will be output on successive clock edges until the burst length requirements are
satisfied. Refer to the following waveforms for more detailed information:
• Figure 24, “Synchronous Single-Word Array or Non-array Read Timing” on page 56
• Figure 25, “Continuous Burst Read, Showing An Output Delay Timing” on page 57
• Figure 26, “Synchronous Burst-Mode Four-Word Read Timing” on page 57
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7.3
Read Device Identifier
The Read Device Identifier command instructs the device to output manufacturer code,
device identifier code, block-lock status, protection register data, or configuration
register data.
Table 10: Device Identifier Information
(1)
Item
Address
Data
Manufacturer Code
0x00
0x89h
ID (see Table 11, “Device ID
codes”)
Device ID Code
0x01
Block Lock Configuration:
• Block Is Unlocked
Lock Bit:
DQ = 0b0
0
(1)
• Block Is Locked
BBA
DBA
+ 0x02
DQ = 0b1
0
• Block Is not Locked-Down
• Block Is Locked-Down
Read Configuration Register
DQ = 0b0
1
DQ = 0b1
1
0x05
RCR Contents
GPR Data
(3)
(2)
General Purpose Register
+ 0x07
0x80
Lock Register 0
PR-LK0 data
64-bit Factory-Programmed OTP Register
64-bit User-Programmable OTP Register
Lock Register 1
0x81–0x84
0x85–0x88
0x89
Factory OTP Register Data
User OTP Register Data
PR-LK1 OTP register lock data
OTP Register Data
128-bit User-Programmable Protection Registers
0x8A–0x109
Notes:
1.
2.
3.
BBA = Block Base Address.
DBA = Device base Address, Numonyx reserves other configuration address locations.
The GPR is used as read out register for Extended Function interface command.
Table 11: Device ID codes
Device Identifier Codes
ID Code Type
Device Density
–T
–B
(Top Parameter)
(Bottom Parameter)
Device Code
256-Mbit
8919
891C
Note: The 512-Mbit devices do not have a Device ID associated with them. Each die within the stack can be identified by either
of the 256-Mbit Device ID codes depending on its parameter option.
7.4
Read CFI
The Read CFI command instructs the device to output Common Flash Interface (CFI)
data when read. See Section 6.0, “Command Set” on page 21 for details on issuing the
Read CFI command. Appendix A, “Common Flash Interface Tables” on page 65 shows
CFI information and address offsets within the CFI database.
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8.0
Program Operation
The device supports three programming methods: Word Programming (40h), Buffered
Programming (E8h, D0h), and Buffered Enhanced Factory Programming (80h, D0h).
See Section 5.0, “Bus Operations” on page 19 for details on the various programming
commands issued to the device. The following sections describe device programming in
detail.
Successful programming requires the addressed block to be unlocked. If the block is
locked down, WP# must be deasserted and the block must be unlocked before
attempting to program the block. Attempting to program a locked block causes a
program error (SR.4 and SR.1 set) and termination of the operation. See Section 10.0,
“Security Modes” on page 34 for details on locking and unlocking blocks.
8.1
Word Programming
Word programming operations are initiated by writing the Word Program Setup
command to the device (see Section 5.0, “Bus Operations” on page 19). This is
followed by a second write to the device with the address and data to be programmed.
The device outputs Status Register data when read. See Figure 35, “Word Program
Flowchart” on page 77. VPP must be above VPPLK, and within the specified VPPL min/
max values.
During programming, the Write State Machine (WSM) executes a sequence of
internally-timed events that program the desired data bits at the addressed location,
and verifies that the bits are sufficiently programmed. Programming the flash memory
array changes “ones” to “zeros”. Memory array bits that are zeros can be changed to
ones only by erasing the block (see Section 9.0, “Erase Operations” on page 32).
The Status Register can be examined for programming progress and errors by reading
at any address. The device remains in the Read Status Register state until another
command is written to the device.
Status Register bit SR.7 indicates the programming status while the sequence
executes. Commands that can be issued to the device during programming are
Program Suspend, Read Status Register, Read Device Identifier, Read CFI, and Read
Array (this returns unknown data).
When programming has finished, Status Register bit SR.4 (when set) indicates a
programming failure. If SR.3 is set, the WSM could not perform the word programming
operation because VPP was outside of its acceptable limits. If SR.1 is set, the word
programming operation attempted to program a locked block, causing the operation to
abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow,
when word programming has completed.
8.2
Buffered Programming
The device features a 512-word buffer to enable optimum programming performance.
For Buffered Programming, data is first written to an on-chip write buffer. Then the
buffer data is programmed into the flash memory array in buffer-size increments. This
can improve system programming performance significantly over non-buffered
programming.
When the Buffered Programming Setup command is issued (see Section 6.0,
“Command Set” on page 21), Status Register information is updated and reflects the
availability of the buffer. SR.7 indicates buffer availability: if set, the buffer is available;
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if cleared, the buffer is not available. To retry, issue the Buffered Programming Setup
command again, and re-check SR.7. When SR.7 is set, the buffer is ready for loading.
(see Figure 37, “Buffer Program Flowchart” on page 79).
On the next write, a word count is written to the device at the buffer address. This tells
the device how many data words will be written to the buffer, up to the maximum size
of the buffer.
On the next write, a device start address is given along with the first data to be written
to the flash memory array. Subsequent writes provide additional device addresses and
data. All data addresses must lie within the start address plus the word count.
Optimum programming performance and lower power usage are obtained by aligning
the starting address at the beginning of a 512-word boundary (A[9:1] = 0x00). The
maximum buffer size would be 256-word if the misaligned address range is crossing a
512-word boundary during programming.
After the last data is written to the buffer, the Buffered Programming Confirm command
must be issued to the original block address. The WSM begins to program buffer
contents to the flash memory array. If a command other than the Buffered
Programming Confirm command is written to the device, a command sequence error
occurs and Status Register bits SR[7,5,4] are set. If an error occurs while writing to the
array, the device stops programming, and Status Register bits SR[7,4] are set,
indicating a programming failure.
When Buffered Programming has completed, additional buffer writes can be initiated by
issuing another Buffered Programming Setup command and repeating the buffered
program sequence. Buffered programming may be performed with VPP = VPPL or VPPH
(see Section 13.2, “Operating Conditions” on page 49 for limitations when operating
the device with VPP = VPPH).
If an attempt is made to program past an erase-block boundary using the Buffered
Program command, the device aborts the operation. This generates a command
sequence error, and Status Register bits SR[5,4] are set.
If Buffered programming is attempted while VPP is at or below VPPLK, Status Register
bits SR[4,3] are set. If any errors are detected that have set Status Register bits, the
Status Register should be cleared using the Clear Status Register command.
8.3
Buffered Enhanced Factory Programming
Buffered Enhanced Factory Programing (BEFP) speeds up Multi-Level Cell (MLC) flash
programming. The enhanced programming algorithm used in BEFP eliminates
traditional programming elements that drive up overhead in device programmer
systems.
BEFP consists of three phases: Setup, Program/Verify, and Exit (see Figure 38, “BEFP
Flowchart” on page 80). It uses a write buffer to spread MLC program performance
across 512 data words. Verification occurs in the same phase as programming to
accurately program the flash memory cell to the correct bit state.
A single two-cycle command sequence programs the entire block of data. This
enhancement eliminates three write cycles per buffer: two commands and the word
count for each set of 512 data words. Host programmer bus cycles fill the device’s write
buffer followed by a status check. SR.0 indicates when data from the buffer has been
programmed into sequential flash memory array locations.
Following the buffer-to-flash array programming sequence, the Write State Machine
(WSM) increments internal addressing to automatically select the next 512-word array
boundary. This aspect of BEFP saves host programming equipment the address-bus
setup overhead.
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With adequate continuity testing, programming equipment can rely on the WSM’s
internal verification to ensure that the device has programmed properly. This eliminates
the external post-program verification and its associated overhead.
8.3.1
BEFP Requirements and Considerations
Table 12: BEFP Requirements
Parameter/Issue
Requirement
Notes
Case Temperature
T = 30°C ± 10 °C
C
V
Nominal Vcc
Driven to V
CC
VPP
PPH
Setup and Confirm
Target block must be unlocked before issuing the BEFP Setup and Confirm commands
The first-word address (WA0) of the block to be programmed must be held constant
from the setup phase through all data streaming into the target block, until transition
to the exit phase is desired
Programming
Buffer Alignment
WA0 must align with the start of an array buffer boundary
1
Note: Word buffer boundaries in the array are determined by A[9:1] (0x000 through 0x1FF). The alignment start point is A[9:1]
= 0x000.
Table 13: BEFP Considerations
Parameter/Issue
Cycling
Requirement
Notes
For optimum performance, cycling must be limited below 50 erase cycles per block.
BEFP programs one block at a time; all buffer data must fall within a single block
BEFP cannot be suspended
1
2
Programming blocks
Suspend
Programming the flash
memory array
Programming to the flash memory array can occur only when the buffer is full.
3
Note:
1.
2.
3.
Some degradation in performance may occur if this limit is exceeded, but the internal algorithm continues to work
properly.
If the internal address counter increments beyond the block's maximum address, addressing wraps around to the
beginning of the block.
If the number of words is less than 512, remaining locations must be filled with 0xFFFF.
8.3.2
BEFP Setup Phase
After receiving the BEFP Setup and Confirm command sequence, Status Register bit
SR.7 (Ready) is cleared, indicating that the WSM is busy with BEFP algorithm startup. A
delay before checking SR.7 is required to allow the WSM enough time to perform all of
its setups and checks (Block-Lock status, VPP level, etc.). If an error is detected, SR.4 is
set and BEFP operation terminates. If the block was found to be locked, SR.1 is also
set. SR.3 is set if the error occurred due to an incorrect VPP level.
Note: Reading from the device after the BEFP Setup and Confirm command sequence outputs
Status Register data. Do not issue the Read Status Register command; it will be interpreted
as data to be loaded into the buffer.
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8.3.3
BEFP Program/Verify Phase
After the BEFP Setup Phase has completed, the host programming system must check
SR[7,0] to determine the availability of the write buffer for data streaming. SR.7
cleared indicates the device is busy and the BEFP program/verify phase is activated.
SR[0] indicates the write buffer is available.
Two basic sequences repeat in this phase: loading of the write buffer, followed by buffer
data programming to the array. For BEFP, the count value for buffer loading is always
the maximum buffer size of 512 words. During the buffer-loading sequence, data is
stored to sequential buffer locations starting at address 0x00. Programming of the
buffer contents to the flash memory array starts as soon as the buffer is full. If the
number of words is less than 512, the remaining buffer locations must be filled with
0xFFFF.
Caution:
The buffer must be completely filled for programming to occur. Supplying an
address outside of the current block's range during a buffer-fill sequence
causes the algorithm to exit immediately. Any data previously loaded into the
buffer during the fill cycle is not programmed into the array.
The starting address for data entry must be buffer size aligned, if not the BEFP
algorithm will be aborted and the program fails and (SR.4) flag will be set.
Data words from the write buffer are directed to sequential memory locations in the
flash memory array; programming continues from where the previous buffer sequence
ended. The host programming system must poll SR.0 to determine when the buffer
program sequence completes. SR.0 cleared indicates that all buffer data has been
transferred to the flash array; SR.0 set indicates that the buffer is not available yet for
the next fill cycle. The host system may check full status for errors at any time, but it is
only necessary on a block basis after BEFP exit. After the buffer fill cycle, no write
cycles should be issued to the device until SR.0 = 0 and the device is ready for the next
buffer fill.
Note: Any spurious writes are ignored after a buffer fill operation and when internal program is
proceeding.
The host programming system continues the BEFP algorithm by providing the next
group of data words to be written to the buffer. Alternatively, it can terminate this
phase by changing the block address to one outside of the current block’s range.
The Program/Verify phase concludes when the programmer writes to a different block
address; data supplied must be 0xFFFF. Upon Program/Verify phase completion, the
device enters the BEFP Exit phase.
8.3.4
8.4
BEFP Exit Phase
When SR.7 is set, the device has returned to normal operating conditions. A full status
check should be performed at this time to ensure the entire block programmed
successfully. When exiting the BEFP algorithm with a block address change, the read
mode will not change. After BEFP exit, any valid command can be issued to the device.
Program Suspend
Issuing the Program Suspend command while programming suspends the
programming operation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
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program operation that is running during an erase suspend can be suspended to
perform a read operation (see Figure 36, “Program/Erase Suspend/Resume Flowchart”
on page 78).
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set. Suspend
latency is specified in Section 16.0, “Program and Erase Characteristics” on page 62.
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.5
8.6
Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status Register bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted (see Figure 36, “Program/Erase
Suspend/Resume Flowchart” on page 78).
Program Protection
When VPP = VIL, absolute hardware write protection is provided for all device blocks. If
V
PP is at or below VPPLK, programming operations halt and SR.3 is set indicating a VPP-
level error. Block lock registers are not affected by the voltage level on VPP; they may
still be programmed and read, even if VPP is less than VPPLK
.
Figure 11: Example VPP Supply Connections
VCC
VCC
VPP
VCC
VPP
VCC
VPP
PROT #
≤ 10K Ω
• Low-voltage Programming only
• Logic Control of Device Protection
• Factory Programming with VPP = VPPH
• Complete write/Erase Protection when VPP ≤ VPPLK
VCC
VCC
VCC
VCC
VPP
VPP=VPPH
VPP
• Low Voltage Programming Only
• Full Device Protection Unavailable
• Low Voltage and Factory Programming
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9.0
Erase Operations
Flash erasing is performed on a block basis. An entire block is erased each time an
erase command sequence is issued, and only one block is erased at a time. When a
block is erased, all bits within that block read as logical ones. The following sections
describe block erase operations in detail.
9.1
Block Erase
Block erase operations are initiated by writing the Block Erase Setup command to the
address of the block to be erased (see Section 6.0, “Command Set” on page 21). Next,
the Block Erase Confirm command is written to the address of the block to be erased. If
the device is placed in standby (CE# deasserted) during an erase operation, the device
completes the erase operation before entering standby.VPP must be above VPPLK and
the block must be unlocked (see Figure 39, “Block Erase Flowchart” on page 81).
During a block erase, the Write State Machine (WSM) executes a sequence of
internally-timed events that conditions, erases, and verifies all bits within the block.
Erasing the flash memory array changes “zeros” to “ones”. Memory block array that are
ones can be changed to zeros only by programming the block (see Section 8.0,
“Program Operation” on page 27).
The Status Register can be examined for block erase progress and errors by reading
any address. The device remains in the Read Status Register state until another
command is written. SR.0 indicates whether the addressed block is erasing. Status
Register bit SR.7 is set upon erase completion.
Status Register bit SR.7 indicates block erase status while the sequence executes.
When the erase operation has finished, Status Register bit SR.5 indicates an erase
failure if set. SR.3 set would indicate that the WSM could not perform the erase
operation because VPP was outside of its acceptable limits. SR.1 set indicates that the
erase operation attempted to erase a locked block, causing the operation to abort.
Before issuing a new command, the Status Register contents should be examined and
then cleared using the Clear Status Register command. Any valid command can follow
once the block erase operation has completed.
9.2
Blank Check
The Blank Check operation determines whether a specified main block is blank (i.e.
completely erased). Without Blank Check, Block Erase would be the only other way to
ensure a block is completely erased. Blank Check is especially useful in the case of
erase operation interrupted by a power loss event.
Blank check can apply to only one block at a time, and no operations other than Status
Register Reads are allowed during Blank Check (e.g. reading array data, program,
erase etc). Suspend and resume operations are not supported during Blank Check, nor
is Blank Check supported during any suspended operations.
Blank Check operations are initiated by writing the Blank Check Setup command to the
block address. Next, the Check Confirm command is issued along with the same block
address. When a successful command sequence is entered, the device automatically
enters the Read Status State. The WSM then reads the entire specified block, and
determines whether any bit in the block is programmed or over-erased.
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The status register can be examined for Blank Check progress and errors by reading
any address within the block being accessed. During a blank check operation, the
Status Register indicates a busy status (SR7 = 0). Upon completion, the Status
Register indicates a ready status (SR7 = 1). The Status Register should be checked for
any errors, and then cleared. If the Blank Check operation fails, which means the block
is not completely erased, the Status Register bit SR.5 will be set (“1”). CE# or
OE# toggle (during polling) updates the Status Register.
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register Mode
until another command is written to the device. Any command can follow once the
Blank Check command is complete.
9.3
Erase Suspend
Issuing the Erase Suspend command while erasing suspends the block erase operation.
This allows data to be accessed from memory locations other than the one being
erased. The Erase Suspend command can be issued to any device address. A block
erase operation can be suspended to perform a word or buffer program operation, or a
read operation within any block except the block that is erase suspended (see
Figure 36, “Program/Erase Suspend/Resume Flowchart” on page 78).
When a block erase operation is executing, issuing the Erase Suspend command
requests the WSM to suspend the erase algorithm at predetermined points. The device
continues to output Status Register data after the Erase Suspend command is issued.
Block erase is suspended when Status Register bits SR[7,6] are set. Suspend latency is
specified in Section 16.0, “Program and Erase Characteristics” on page 62.
To read data from the device (other than an erase-suspended block), the Read Array
command must be issued. During Erase Suspend, a Program command can be issued
to any block other than the erase-suspended block. Block erase cannot resume until
program operations initiated during erase suspend complete. Read Array, Read Status
Register, Read Device Identifier, Read CFI, and Erase Resume are valid commands
during Erase Suspend. Additionally, Clear Status Register, Program, Program Suspend,
Block Lock, Block Unlock, and Block Lock-Down are valid commands during Erase
Suspend.
During an erase suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at a valid level, and WP# must remain unchanged
while in erase suspend. If RST# is asserted, the device is reset.
9.4
9.5
Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears status register bits SR[7,6]. This command can be written to any
address. If status register error bits are set, the Status Register should be cleared
before issuing the next instruction. RST# must remain deasserted (see Figure 36,
“Program/Erase Suspend/Resume Flowchart” on page 78).
Erase Protection
When VPP = VIL, absolute hardware erase protection is provided for all device blocks. If
VPP is at or below VPPLK, erase operations halt and SR.3 is set indicating a VPP-level
error.
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10.0
Security Modes
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1
Block Locking
Individual instant block locking is used to protect user code and/or data within the flash
memory array. All blocks power-up in a locked state to protect array data from being
altered during power transitions. Any block can be locked or unlocked with no latency.
Locked blocks cannot be programmed or erased; they can only be read.
Software-controlled security is implemented using the Block Lock and Block Unlock
commands. Hardware-controlled security can be implemented using the Block Lock-
Down command along with asserting WP#. Also, VPP data security can be used to
inhibit program and erase operations (see Section 8.6, “Program Protection” on
page 31 and Section 9.5, “Erase Protection” on page 33).
10.1.1
Lock Block
To lock a block, issue the Block Lock Setup command, followed by the Block Lock
command issued to the desired block’s address. If the Set Read Configuration Register
command is issued after the Block Lock Setup command, the device configures the RCR
instead.
Block lock and unlock operations are not affected by the voltage level on VPP. The block
lock bits may be modified and/or read even if VPP is at or below VPPLK
.
10.1.2
10.1.3
Unlock Block
The Block Unlock command is used to unlock blocks (see Section 6.0, “Command Set”
on page 21). Unlocked blocks can be read, programmed, and erased. Unlocked blocks
return to a locked state when the device is reset or powered down. If a block is in a
lock-down state, WP# must be deasserted before it can be unlocked (see Figure 12,
“Block Locking State Diagram” on page 35).
Lock-Down Block
A locked or unlocked block can be locked-down by writing the Block Lock-Down
command sequence (see Section 6.0, “Command Set” on page 21). Blocks in a lock-
down state cannot be programmed or erased; they can only be read. However, unlike
locked blocks, their locked state cannot be changed by software commands alone. A
locked-down block can only be unlocked by issuing the Block Unlock command with
WP# deasserted. To return an unlocked block to locked-down state, a Block Lock-Down
command must be issued prior to changing WP# to VIL. Locked-down blocks revert to
the locked state upon reset or power up the device (see Figure 12, “Block Locking State
Diagram” on page 35).
10.1.4
Block Lock Status
The Read Device Identifier command is used to determine a block’s lock status (see
Section 12.0, “Power and Reset Specifications” on page 47). Data bits DQ[1:0] display
the addressed block’s lock status; DQ0 is the addressed block’s lock bit, while DQ1 is
the addressed block’s lock-down bit.
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Figure 12: Block Locking State Diagram
P G M /E R A S E
A L L O W E D
P G M /E R A S E
P R E V E N T E D
L K /
D 0 h
L K /
0 1 h
[0 0 0 ]
[0 0 1 ]
P o w e r-U p /
R e s e t D e fa u lt
L K /
2 F h
W P # = V IL = 0
[0 1 1 ]
V irtu a l lo c k -
d o w n
[0 1 0 ]
L o c k e d -d o w n
A n y L o c k
c o m m a n d s
W P # to g g le
L K /
D 0 h
L K /
0 1 h o r 2 F h
L o c k e d -d o w n
is d is a b le d b y
W P # = V IH
[1 1 0 ]
[1 1 1 ]
W P # = V IH = 1
L K /
2 F h
L K /
2 F h
P o w e r-U p /
R e s e t D e fa u lt
L K /
D 0 h
L K /
0 1 h
[1 0 0 ]
[1 0 1 ]
Note: LK: Lock Setup Command, 60h; LK/D0h: Unlock Command; LK/01h: Lock Command; LK/2Fh: Lock-Down Command.
10.1.5
Block Locking During Suspend
Block lock and unlock changes can be performed during an erase suspend. To change
block locking during an erase operation, first issue the Erase Suspend command.
Monitor the Status Register until SR.7 and SR.6 are set, indicating the device is
suspended and ready to accept another command.
Next, write the desired lock command sequence to a block, which changes the lock
state of that block. After completing block lock or unlock operations, resume the erase
operation using the Erase Resume command.
Note: A Lock Block Setup command followed by any command other than Lock Block, Unlock Block,
or Lock-Down Block produces a command sequence error and set Status Register bits SR.4
and SR.5. If a command sequence error occurs during an erase suspend, SR.4 and SR.5
remains set, even after the erase operation is resumed. Unless the Status Register is cleared
using the Clear Status Register command before resuming the erase operation, possible erase
errors may be masked by the command sequence error.
If a block is locked or locked-down during an erase suspend of the same block, the lock
status bits change immediately. However, the erase operation completes when it is
resumed. Block lock operations cannot occur during a program suspend. See Appendix
A, “Write State Machine” on page 85, which shows valid commands during an erase
suspend.
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10.2
10.3
Selectable One-Time Programmable Blocks
The P30-65nm family devices provide backward compatible OTP security feature as
legacy P30-130nm. Please see your local Numonyx representative for details about its
implementation.
Password Access
The Password Access is a security enhancement offered on the P30-65nm device.This
feature protects information stored in array blocks by preventing content alteration or
reads until a valid 64-bit password is received. The Password Access may be combined
with Non-Volatile Protection and/or Volatile Protection to create a multi-tiered solution.
Please contact your Numonyx Sales for further details concerning Password Access.
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11.0
Registers
When non-array reads are performed in asynchronous page mode only the first data is
valid and all subsequent data are undefined. When a non-array read operation occurs
as synchronous burst mode, the same word of data requested will be output on
successive clock edges until the burst length requirements are satisfied.
11.1
Read Status Register
To read the Status Register, issue the Read Status Register command at any address.
Status Register information is available to which the Read Status Register, Word
Program, or Block Erase command was issued. Status Register data is automatically
made available following a Word Program, Block Erase, or Block Lock command
sequence. Reads from the device after any of these command sequences outputs the
device’s status until another valid command is written (e.g. Read Array command).
The Status Register is read using single asynchronous-mode or synchronous burst
mode reads. Status Register data is output on DQ[7:0], while 0x00 is output on
DQ[15:8]. In asynchronous mode the falling edge of OE#, or CE# (whichever occurs
first) updates and latches the Status Register contents. However, reading the Status
Register in synchronous burst mode, CE# or ADV# must be toggled to update status
data.
The Device Write Status bit (SR.7) provides overall status of the device. Status register
bits SR[6:1] present status and error information about the program, erase, suspend,
VPP, and block-locked operations.
Table 14: Status Register Description (Sheet 1 of 2)
Status Register (SR)
Default Value = 0x80
Erase
Suspend
Status
Program
Suspend
Status
Device Write
Status
Program
Status
Block-Locked
BEFP
Status
Erase Status
V
Status
PP
Status
DWS
7
ESS
6
ES
5
PS
4
VPPS
PSS
2
BLS
1
BWS
0
3
Bit
Name
Description
0 = Device is busy; program or erase cycle in progress; SR[0] valid.
1 = Device is ready; SR[6:1] are valid.
7
6
5
4
3
Device Write Status (DWS)
Erase Suspend Status (ESS)
Erase Status (ES)
0 = Erase suspend not in effect.
1 = Erase suspend in effect.
0 = Erase successful.
1 = Erase fail or program sequence error when set with SR[4,7].
0 = Program successful.
1 = Program fail or program sequence error when set with SR[5,7]
Program Status (PS)
0 = VPP within acceptable limits during program or erase operation.
1 = VPP ≤ VPPLK during program or erase operation.
V
Status (VPPS)
PP
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Table 14: Status Register Description (Sheet 2 of 2)
Status Register (SR)
Default Value = 0x80
0 = Program suspend not in effect.
1 = Program suspend in effect.
Program Suspend Status
(PSS)
2
1
0 = Block not locked during program or erase.
1 = Block locked during program or erase; operation aborted.
Block-Locked Status (BLS)
After Buffered Enhanced Factory Programming (BEFP) data is loaded into the
buffer:
0 = BEFP complete.
0
BEFP Status (BWS)
1 = BEFP in-progress.
Note: Always clear the Status Register prior to resuming erase operations. It avoids Status Register
ambiguity when issuing commands during Erase Suspend. If a command sequence error
occurs during an erase-suspend state, the Status Register contains the command sequence
error status (SR[7,5,4] set). When the erase operation resumes and finishes, possible errors
during the erase operation cannot be detected via the Status Register because it contains the
previous error status.
11.1.1
Clear Status Register
The Clear Status Register command clears the status register. It functions independent
of VPP. The Write State Machine (WSM) sets and clears SR[7,6,2], but it sets bits
SR[5:3,1] without clearing them. The Status Register should be cleared before starting
a command sequence to avoid any ambiguity. A device reset also clears the Status
Register.
11.2
Read Configuration Register
The RCR is a 16-bit read/write register used to select bus-read mode (synchronous or
asynchronous), and to configure synchronous burst read characteristics of the device.
To modify RCR settings, use the Configure Read Configuration Register command (see
Section 6.0, “Command Set” on page 21).
RCR contents can be examined using the Read Device Identifier command, and then
reading from offset 0x05 (see Section 12.0, “Power and Reset Specifications” on
page 47).
Upon power-up or exit from reset, the RCR defaults to asynchronous mode.
The following sections describe each RCR bit.
Table 15: Read Configuration Register Description (Sheet 1 of 2)
Read Configuration Register (RCR)
WAIT
Delay
Burst
Wrap
Read
Mode
WAIT
Polarity
Burst
Seq
CLK
Edge
Latency Count
LC[3:0]
RES
RES
RES
Burst Length
RM
15
Bit
WP
10
R
9
WD
8
BS
7
CE
6
R
5
R
4
BW
3
BL[2:0]
1
14
13
12
11
2
0
Name
Description
0 = Synchronous burst-mode read
1 = Asynchronous page-mode read (default)
15
Read Mode (RM)
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Table 15: Read Configuration Register Description (Sheet 2 of 2)
0010 =Code 2
0011 =Code 3
0100 =Code 4
0101 =Code 5
0110 =Code 6
0111 =Code 7
1000 =Code 8
14:11
Latency Count (LC[3:0])
1001 =Code 9
1010 =Code 10
1011 =Code 11
1100 =Code 12
1101 =Code 13
1110 =Code 14
1111 =Code 15 (default)
(Other bit settings are reserved)
0 =WAIT signal is active low (default)
1 =WAIT signal is active high
WAIT Polarity (WP)
10
9
Reserved (R)
Default “0”, Non-changeable
0 =WAIT deasserted with valid data
8
WAIT Delay (WD)
Burst Sequence (BS)
1 =WAIT deasserted one data cycle before valid data (default)
7
Default “0”, Non-changeable
Clock Edge (CE)
0 = Falling edge
1 = Rising edge (default)
6
5:4
3
Reserved (R)
Default “0”, Non-changeable
Burst Wrap (BW)
0 =Wrap; Burst accesses wrap within burst length set by BL[2:0]
1 =No Wrap; Burst accesses do not wrap within burst length (default)
001 =4-word burst
010 =8-word burst
011 =16-word burst
111 =Continuous-word burst (default)
2:0
Burst Length (BL[2:0])
(Other bit settings are reserved)
11.2.1
Read Mode
The Read Mode (RM) bit selects synchronous burst-mode or asynchronous page-mode
operation for the device. When the RM bit is set, asynchronous page mode is selected
(default). When RM is cleared, synchronous burst mode is selected.
11.2.2
Latency Count
The Latency Count (LC) bits tell the device how many clock cycles must elapse from the
rising edge of ADV# (or from the first valid clock edge after ADV# is asserted) until the
first valid data word is to be driven onto DQ[15:0]. The input clock frequency is used to
determine this value and Figure 13 shows the data output latency for the different
settings of LC. The maximum Latency Count for P30-65nm would be Code 4 based on
the Max Clock frequency specification of 52 mhz, and there will be zero WAIT States
when bursting within the word line. Please also refer to Section 11.2.3, “End of Word
Line (EOWL) Considerations” on page 41 for more information on EOWL.
Refer to Table 16, “LC and Frequency Support” on page 41 for Latency Code Settings.
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Figure 13: First-Access Latency Count
CLK [C]
Valid
Address
Address [A]
ADV# [V]
Code 0 (Reserved)
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
DQ15-0 [D/Q]
Code 1
(Reserved
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 2
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Code 3
Code 4
Code 5
Code 6
Code 7
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
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Table 16: LC and Frequency Support
Latency Count Settings
Frequency Support (MHz)
3
4
≤ 40
≤ 52
Figure 14: Example Latency Count Setting using Code 3
tData
0
1
2
3
4
CLK
CE#
ADV#
Address
A[MAX:1]
Code 3
High-Z
Data
D[15:0]
R103
11.2.3
End of Word Line (EOWL) Considerations
End of Wordline (EOWL) WAIT states can result when the starting address of the burst
operation is not aligned to a 16-word boundary; that is, A[3:0] of start address does
not equal 0x0. Figure 15, “End of Wordline Timing Diagram” on page 41 illustrates the
end of wordline WAIT state(s), which occur after the first 16-word boundary is reached.
The number of data words and the number of WAIT states is summarized in Table 17,
“End of Wordline Data and WAIT state Comparison” on page 42for both P30-130nm
and P30-65nm devics.
Figure 15: End of Wordline Timing Diagram
Latency Count
CLK
A[Max:1]
DQ[15:0]
Address
Data
Data
Data
ADV#
OE#
WAIT
EOWL
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Table 17: End of Wordline Data and WAIT state Comparison
P30-130nm
P30-65nm
Latency Count
Data States
WAIT States
Data States
WAIT States
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Not Supported
Not Supported
0 to 1
Not Supported
Not Supported
Not Supported
Not Supported
0 to 2
4
4
4
4
4
4
0 to 2
0 to 3
0 to 4
0 to 5
16
16
16
16
16
16
16
16
16
16
16
16
16
0 to 3
0 to 4
0 to 5
0 to 6
0 to 7
0 to 8
0 to 9
0 to 10
0 to 11
0 to 12
0 to 13
0 to 14
0 to 6
Not Supported
Not Supported
11.2.4
WAIT Polarity
The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.
When WP is set, WAIT is asserted high (default). When WP is cleared, WAIT is asserted
low. WAIT changes state on valid clock edges during active bus cycles (CE# asserted,
OE# asserted, RST# deasserted).
11.2.4.1
WAIT Signal Function
The WAIT signal indicates data valid when the device is operating in synchronous mode
(RCR.15 =0). The WAIT signal is only “deasserted” when data is valid on the bus.
When the device is operating in synchronous non-array read mode, such as read
status, read ID, or read CFI. The WAIT signal is also “deasserted” when data is valid on
the bus.
WAIT behavior during synchronous non-array reads at the end of word line works
correctly only on the first data access.
When the device is operating in asynchronous page mode, asynchronous single word
read mode, and all write operations, WAIT is set to a deasserted state as determined
by RCR.10. See Figure 22, “Asynchronous Single-Word Read (ADV# Latch)” on
page 55, and Figure 23, “Asynchronous Page-Mode Read Timing” on page 56.
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Table 18: WAIT Functionality Table
Condition
WAIT
Notes
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
CE# =’0’, OE# = ‘0’
High-Z
Active
1
1
Synchronous Array Reads
Synchronous Non-Array Reads
All Asynchronous Reads
All Writes
Active
1
Active
1
Deasserted
High-Z
1
1,2
Notes:
1.
2.
Active: WAIT is asserted until data becomes valid, then desserts
When OE# = V during writes, WAIT = High-Z
IH
11.2.5
11.2.6
WAIT Delay
The WAIT Delay (WD) bit controls the WAIT assertion-delay behavior during
synchronous burst reads. WAIT can be asserted either during or one data cycle before
valid data is output on DQ[15:0]. When WD is set, WAIT is deasserted one data cycle
before valid data (default). When WD is cleared, WAIT is deasserted during valid data.
Burst Sequence
The Burst Sequence (BS) bit selects linear-burst sequence (default). Only linear-burst
sequence is supported. Table 19 shows the synchronous burst sequence for all burst
lengths, as well as the effect of the Burst Wrap (BW) setting.
Table 19: Burst Sequence Word Ordering (Sheet 1 of 2)
Burst Addressing Sequence (DEC)
Start
Addr.
(DEC)
Burst
Wrap
(RCR.3)
4-Word Burst
(BL[2:0] = 0b001)
8-Word Burst
16-Word Burst
(BL[2:0] = 0b011)
Continuous Burst
(BL[2:0] = 0b111)
(BL[2:0] = 0b010)
0
1
2
3
4
0
0
0
0
0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
0-1-2-3-4…14-15
1-2-3-4-5…15-0
0-1-2-3-4-5-6-…
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
4-5-6-7-8-9-10…
2-3-4-5-6…15-0-1
3-4-5-6-7…15-0-1-2
4-5-6-7-8…15-0-1-2-3
5-6-7-8-9…15-0-1-2-3-
4
5
6
7
0
0
0
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
6-7-8-9-10…15-0-1-2-
3-4-5
7-8-9-10…15-0-1-2-3-
4-5-6
14
15
0
0
14-15-16-17-18-19-20-
…
14-15-0-1-2…12-13
15-0-1-2-3…13-14
15-16-17-18-19-20-21-
…
0
1
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4…14-15
0-1-2-3-4-5-6-…
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Table 19: Burst Sequence Word Ordering (Sheet 2 of 2)
1
2
3
4
5
6
7
1
1
1
1
1
1
1
1-2-3-4
2-3-4-5
3-4-5-6
1-2-3-4-5-6-7-8
2-3-4-5-6-7-8-9
1-2-3-4-5…15-16
2-3-4-5-6…16-17
3-4-5-6-7…17-18
4-5-6-7-8…18-19
5-6-7-8-9…19-20
6-7-8-9-10…20-21
7-8-9-10-11…21-22
1-2-3-4-5-6-7-…
2-3-4-5-6-7-8-…
3-4-5-6-7-8-9-…
3-4-5-6-7-8-9-10
4-5-6-7-8-9-10-11
5-6-7-8-9-10-11-12
6-7-8-9-10-11-12-13
7-8-9-10-11-12-13-14
4-5-6-7-8-9-10…
5-6-7-8-9-10-11…
6-7-8-9-10-11-12-…
7-8-9-10-11-12-13…
14-15-16-17-18-19-20-
…
14
15
1
1
14-15-16-17-18…28-29
15-16-17-18-19…29-30
15-16-17-18-19-20-21-
…
11.2.7
11.2.8
Clock Edge
The Clock Edge (CE) bit selects either a rising (default) or falling clock edge for CLK.
This clock edge is used at the start of a burst cycle, to output synchronous data, and to
assert/deassert WAIT.
Burst Wrap
The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length
accesses wrap within the selected word-length boundaries or cross word-length
boundaries. When BW is set, burst wrapping does not occur (default). When BW is
cleared, burst wrapping occurs.
When performing synchronous burst reads with BW set (no wrap), an output delay may
occur when the burst sequence crosses its first device-row (16-word) boundary. If the
burst sequence’s start address is 4-word aligned, then no delay occurs. If the start
address is at the end of a 4-word boundary, the worst case output delay is one clock
cycle less than the first access Latency Count. This delay can take place only once, and
doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT
informs the system of this delay when it occurs.
11.2.9
Burst Length
The Burst Length bits (BL[2:0]) select the linear burst length for all synchronous burst
reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word or
continuous.
Continuous-burst accesses are linear only, and do not wrap within any word length
boundaries (see Table 19, “Burst Sequence Word Ordering” on page 43). When a burst
cycle begins, the device outputs synchronous burst data until it reaches the end of the
“burstable” address space.
11.3
One-Time-Programmable (OTP) Registers
The device contains 17 one-time programmable (OTP) registers that can be used to
implement system security measures and/or device identification. Each OTP register
can be individually locked.
The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower
64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit
number. The upper 64-bit segment, as well as the other sixteen 128-bit OTP Registers,
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are blank. Users can program these registers as needed. Once programmed, users can
then lock the OTP Register(s) to prevent additional bit programming (see Figure 16,
“OTP Register Map” on page 45).
The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR
bits cannot be erased. Each OTP Register can be accessed multiple times to program
individual bits, as long as the register remains unlocked.
Each OTP Register has an associated Lock Register bit. When a Lock Register bit is
programmed, the associated OTP Register can only be read; it can no longer be
programmed. Additionally, because the Lock Register bits themselves are OTP, when
programmed, Lock Register bits cannot be erased. Therefore, when a OTP Register is
locked, it cannot be unlocked.
.
Figure 16: OTP Register Map
0x109
128-bit Protection Register 16
(User-Programmable)
0x102
0x91
128-bit Protection Register 1
(User-Programmable)
0x8A
0x89
Lock Register 1
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0x88
64-bit Segment
(User-Programmable)
0x85
0x84
128-Bit Protection Register 0
64-bit Segment
(Factory-Programmed)
0x81
0x80
Lock Register 0
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
11.3.1
Reading the OTP Registers
The OTP Registers can be read from OTP-RA address. To read the OTP Register, first
issue the Read Device Identifier command at OTP-RA address to place the device in the
Read Device Identifier state (see Section 6.0, “Command Set” on page 21). Next,
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perform a read operation using the address offset corresponding to the register to be
read. Table 10, “Device Identifier Information” on page 26 shows the address offsets of
the OTP Registers and Lock Registers. PR data is read 16 bits at a time.
11.3.2
Programming the OTP Registers
To program an OTP Register, first issue the Program OTP Register command at the
parameter’s base address plus the offset of the desired OTP Register location(see
Section 6.0, “Command Set” on page 21). Next, write the desired OTP Register data to
the same OTP Register address (see Figure 16, “OTP Register Map” on page 45).
The device programs the 64-bit and 128-bit user-programmable OTP Register data 16
bits at a time (see Figure 41, “Protection Register Programming Flowchart” on
page 83). Issuing the Program OTP Register command outside of the OTP Register’s
address space causes a program error (SR.4 set). Attempting to program a locked OTP
Register causes a program error (SR.4 set) and a lock error (SR.1 set).
Note:
When programming the OTP bits in the OTP registers for a Top Parameter Device,
the following upper address bits must also be driven properly: A[Max:17] driven high
(VIH) for TSOP and Easy BGA packages, and A[Max:16] driven high (VIH) for QUAD+
SCSP.
11.3.3
Locking the OTP Registers
Each OTP Register can be locked by programming its respective lock bit in the Lock
Register. To lock a OTP Register, program the corresponding bit in the Lock Register by
issuing the Program Lock Register command, followed by the desired Lock Register
data (see Section 6.0, “Command Set” on page 21). The physical addresses of the Lock
Registers are 0x80 for register 0 and 0x89 for register 1. These addresses are used
when programming the lock registers (see Table 10, “Device Identifier Information” on
page 26).
Bit 0 of Lock Register 0 is already programmed during the manufacturing process by
Numonyx factory, locking the lower half segment of the first 128-bit OTP Register. Bit 1
of Lock Register 0 can be programmed by user to the upper half segment of the first
128-bit OTP Register. When programming Bit 1 of Lock Register 0, all other bits need to
be left as ‘1’ such that the data programmed is 0xFFFD.
Lock Register 1 controls the locking of the upper sixteen 128-bit OTP Registers. Each
bit of Lock Register 1 corresponds to a specific 128-bit OTP Register. Programming a bit
in Lock Register 1 locks the corresponding 128-bit OTP Register; e.g., programming
LR1.0 locks the corresponding OTP Register 1.
Caution:
After being locked, the OTP Registers cannot be unlocked.
Datasheet
46
Apr 2009
Order Number: 320002-08
P30-65nm
12.0
Power and Reset Specifications
12.1
Power-Up and Power-Down
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
V
CC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
12.2
Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Invalid bus conditions are masked, providing a level of memory
protection.
Table 20: Power and Reset
Num
Symbol
Parameter
RST# pulse width low
Min
Max
Unit
Notes
P1
t
100
-
-
ns
1,2,3,4
1,3,4,7
1,3,4,7
1,4,5,6
PLPH
RST# low to device reset during erase
RST# low to device reset during program
25
25
-
P2
P3
t
t
PLRH
VCCPH
-
us
V
Power valid to RST# de-assertion (high)
300
CC
Notes:
1.
2.
3.
4.
5.
6.
7.
These specifications are valid for all device versions (packages and speeds).
The device may reset if t is < t , but this is not guaranteed.
PLPH
PLPH MIN
Not applicable if RST# is tied to Vcc.
Sampled, but not 100% tested.
When RST# is tied to the V supply, device will not be ready until t
after V ≥ V
VCCPH
.
CC
CCQ
VCCPH
CC
CC
CCMIN
When RST# is tied to the V
supply, device will not be ready until t
after V ≥ V
.
CCMIN
Reset completes within t
if RST# is asserted while no erase or program operation is executing.
PLPH
Datasheet
47
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 17: Reset Operation Waveforms
P1
P2
P2
P3
R5
VIH
VIL
(
A) Reset during
read mode
RST# [P]
RST# [P]
RST# [P]
VCC
Abort
Complete
R5
(B) Reset during
VIH
VIL
program or block erase
P1
≤ P2
Abort
Complete
R5
(C) Reset during
VIH
VIL
program or block erase
P1
≥ P2
VCC
0V
(D) VCC Power-up to
RST# high
12.3
Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are 1) standby current levels, 2) active current levels,
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because flash memory devices draw their power from VCC, VPP, and VCCQ, each power
connection should have a 0.1 µF ceramic capacitor to ground. High-frequency,
inherently low-inductance capacitors should be placed as close as possible to package
leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Datasheet
48
Apr 2009
Order Number: 320002-08
P30-65nm
13.0
Maximum Ratings and Operating Conditions
13.1
Absolute Maximum Ratings
Warning:
Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
Table 21:
Parameter
Maximum Rating
Notes
Temperature under bias
Storage temperature
–40 °C to +85 °C
–65 °C to +125 °C
–0.5 V to +4.1 V
–0.2 V to +10 V
–0.2 V to +2.5 V
–0.2 V to +4.1 V
100 mA
Voltage on any signal (except V , V and V )
CCQ
1
1,2,3
1
CC
PP
V
V
V
voltage
voltage
PP
CC
voltage
1
CCQ
Output short circuit current
4
Notes:
1.
Voltages shown are specified with respect to V . Minimum DC voltage is –0.5 V on input/output signals and –0.2 V on
SS
V
, V
, and V . During transitions, this level may undershoot to –2.0 V for periods less than 20 ns. Maximum DC
CC
CCQ PP
voltage on V is V + 0.5 V, which, during transitions, may overshoot to V + 2.0 V for periods less than 20 ns.
CC
CC
CC
Maximum DC voltage on input/output signals and V
CCQ
is V
+ 0.5 V, which, during transitions, may overshoot to
CCQ
CCQ
V
+ 2.0 V for periods less than 20 ns.
Maximum DC voltage on V may overshoot to +11.5 V for periods less than 20 ns.
2.
3.
PP
Program/erase voltage is typically 1.7 V – 2.0 V. 9.0 V can be applied for 80 hours maximum total, to any blocks for
1000 cycles maximum. 9.0 V program/erase voltage may reduce block cycling capability.
4.
Output shorted for no more than one second. No more than one output shorted at a time.
13.2
Operating Conditions
Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device reliability.
Table 22: Operating Conditions
Symbol
Parameter
Min
Max
Unit
Notes
T
Operating Temperature
V Supply Voltage
CC
–40
1.7
+85
2.0
3.6
3.6
3.6
9.5
80
-
°C
1
3
C
V
CC
CMOS inputs
TTL inputs
1.7
V
I/O Supply Voltage
Voltage Supply (Logic Level)
CCQ
2.4
V
V
V
0.9
PPL
PPH
PPH
PP
V
Buffered Enhanced Factory Programming V
8.5
PP
PP
PP
PP
PP
t
Maximum V Hours
PP
V
V
V
V
= V
-
Hours
Cycles
PPH
2
Main and Parameter Blocks
Main Blocks
= V
100,000
100,000
100,000
PPL
Block
Erase
Cycles
= V
= V
-
PPH
PPH
Parameter Blocks
-
Notes:
1.
2.
T
= Case Temperature.
C
In typical operation VPP program voltage is V
.
PPL
Datasheet
49
Apr 2009
Order Number: 320002-08
P30-65nm
14.0
Electrical Specifications
14.1
DC Current Characteristics
Table 23: DC Current Characteristics (Sheet 1 of 2)
CMOS
TTL Inputs
(V
2.4 V - 3.6
V)
Inputs
=
CCQ
(V
=
CCQ
Sym
Parameter
Unit
Test Conditions
Notes
1.7V - 3.6 V)
Typ
-
Max
±1
Typ
-
Max
±2
V
V
V
= V Max
CC
CC
I
Input Load Current
µA
µA
= V
Max
LI
CCQ
= V
CCQ
CCQ
or V
SS
IN
1,6
1.2
Output
Leakage
Current
V
V
V
= V Max
CC CC
I
DQ[15:0], WAIT
-
±1
-
±10
210
= V
CCQ
Max
LO
CCQ
CCQ
= V
or V
SS
IN
256-Mbit
512-Mbit
65
210
65
V
V
= V Max
CC CC
= V
Max
CCQ
CCQ
I
I
,
V
Standby,
CC
CE# = V
RST# = V
RST# = V (for I
WP# = V
CCS
CCQ
CCQ
µA
(for I
)
CCS
CCD
Power-Down
CCD
130
26
420
31
130
26
420
31
)
SS
IH
Asynchronous Single-
Word f = 5 MHz (1 CLK)
16-Word
Read
mA
mA
Page-Mode Read
16-Word
Read
V
= V Max
CC
12
19
16
16
22
18
12
19
16
16
22
18
CC
f = 13 MHz (17 CLK)
Average
CE# = V
OE# = V
Inputs: V or
V
IL
V
CC
Read
Current
I
mA 8-Word Read
1
CCR
IH
IL
16-Word
Read
Synchronous Burst
f = 52 MHz, LC=4
mA
IH
Continuous
Read
21
24
21
24
mA
35
35
65
50
50
35
35
65
50
50
V
V
= V , Pgm/Ers in progress
1,3,5
PP
PP
PPL
I
I
V
V
Program Current,
Erase Current
CCW,
CC
CC
mA
µA
CCE
= V
, Pgm/Ers in progress
1,3,5
PPH
V
Program Suspend
256-Mbit
512-Mbit
210
210
CC
I
Current,
V
Suspend Current
CE# = V
progress
; suspend in
CCWS,
CCQ
I
Erase
1,3,4
CCES
CC
70
225
5
70
225
5
I
V
V
V
Standby Current,
Program Suspend Current,
Erase Suspend Current
PPS,
PP
PP
PP
I
0.2
0.2
µA
V
= V , suspend in progress
1,3,7
PPWS,
PP
PPL
IPPES
I
V
Read
2
15
2
15
µA
V
V
V
V
V
= V
= V
= V
= V
= V
1,3
-3
PPR
PP
PP
PP
PP
PP
PP
PP
PPL
0.05
0.05
0.05
0.05
0.10
0.10
0.10
0.10
0.05
0.05
0.05
0.05
0.10
0.10
0.10
0.10
program in progress
program in progress
erase in progress
erase in progress
PPL,
PPH,
PPL,
PPH,
I
V
Program Current
mA
PPW
I
V
Erase Current
mA
3
PPE
PP
Datasheet
50
Apr 2009
Order Number: 320002-08
P30-65nm
Table 23: DC Current Characteristics (Sheet 2 of 2)
CMOS
TTL Inputs
(V
2.4 V - 3.6
V)
Inputs
=
CCQ
(V
=
CCQ
Sym
Parameter
Unit
Test Conditions
Notes
1.7V - 3.6 V)
Typ
Max
Typ
Max
0.05
0.05
0.10
0.10
0.05
0.05
0.10
0.10
V
V
= V
= V
erase in progress
erase in progress
PP
PPL,
PPH,
I
V
Blank Check
mA
3
PPBC
PP
PP
Notes:
1.
2.
3.
4.
5.
All currents are RMS unless noted. Typical values at typical V , T = +25 °C.
CC C
I
is the average current measured over any 5 ms time interval 5 µs after CE# is deasserted.
CCS
Sampled, not 100% tested.
I
I
is specified with the device deselected. If device is read while in erase suspend, current is I
CCW CCE
plus I
.
CCR
CCES
, I
measured over typical or max times specified in Section 16.0, “Program and ECraCEsSe
Characteristics” on page 62.
6.
7.
if V > V the input load current increases to 10uA max.
IN CC
the I
I
I
Will increase to 200uA when Vpp/WP# is at V
PPS, PPWS, PPES PPH.
14.2
DC Voltage Characteristics
Table 24: DC Voltage Characteristics
(1)
CMOS Inputs
TTL Inputs
(V
= 1.7 V – 3.6 V)
(V
= 2.4 V – 3.6 V)
CCQ
CCQ
Sym
Parameter
Unit
Test Conditions
Notes
Min
Max
Min
Max
V
Input Low Voltage
Input High Voltage
-0.5
– 0.4
0.4
+ 0.5
-0.5
2.0
0.6
+ 0.5
V
V
IL
2
-
V
V
V
V
CCQ
IH
CCQ
CCQ
V
= V Min
CC
CCQ
= 100 µA
CC
V
Output Low Voltage
Output High Voltage
-
0.2
-
-
0.2
-
V
V
V
= V
Min
OL
CCQ
I
OL
V
= V Min
CC
CC
V
V
– 0.2
V
– 0.2
V
I
= V Min
-
OH
CCQ
CCQ
CCQ
OH
CCQ
= –100 µA
V
V
Lock-Out Voltage
-
0.4
-
0.4
V
V
V
3
-
PPLK
PP
V
V
Lock Voltage
Lock Voltage
1.0
0.9
-
-
1.0
0.9
-
-
LKO
CC
V
V
-
LKOQ
CCQ
V
Voltage Supply
PP
V
1.5
8.5
3.6
9.5
1.5
8.5
3.6
9.5
V
V
PPL
(Logic Level)
Buffered Enhanced
V
Factory Programming
PPH
V
PP
Notes:
1.
2.
3.
Synchronous read mode is not supported with TTL inputs.
V
V
can undershoot to –0.4 V and V can overshoot to V
+ 0.4 V for durations of 20 ns or less.
IL
PP
IH
CCQ
≤ V
inhibits erase and program operations. Do not use V
and V
PPLK
PPL PPH
.
outside their valid ranges
Datasheet
51
Apr 2009
Order Number: 320002-08
P30-65nm
15.0
AC Characteristics
15.1
AC Test Conditions
Figure 18: AC Input/Output Reference Waveform
VCCQ
Input VCCQ/2
Test Points
VCCQ/2 Output
0V
IO_REF.WMF
Note: AC test inputs are driven at V
for Logic "1" and 0 V for Logic "0." Input/output timing begins/ends at V
/2. Input rise
CCQ
CCQ
and fall times (10% to 90%) < 5 ns. Worst case speed occurs at V = V
.
CC
CCMin
Figure 19: Transient Equivalent Testing Load Circuit
Device
Under Test
Out
CL
Notes:
1.
2.
See the following table for component values.
Test configuration component value for worst-case speed conditions.
3.
C includes jig capacitance.
L
.
Table 25: Test Configuration Component Value For Worst Case Speed Conditions
Test Configuration
Min Standard Test
C
(pF)
L
V
30
CCQ
Figure 20: Clock Input AC Waveform
R201
VIH
CLK [C]
VIL
R202
R203
Datasheet
52
Apr 2009
Order Number: 320002-08
P30-65nm
15.2
Capacitance
Table 26: Capacitance
Parameter
Signals
Min
Typ
Max
Unit
Condition
Notes
Address, Data,
CE#, WE#, OE#,
RST#, CLK, ADV#,
WP#
Typ temp = 25 °C,
Max temp = 85 °C,
Input Capacitance
Output Capacitance
2
2
6
4
7
5
pF
pF
V
= (0 V - 2.0 V),
= (0 V - 3.6 V),
1,2,3
CC
CCQ
V
Discrete silicon die
Data, WAIT
Notes:
1.
Capacitance values are for a single die; for 2-die and 4-die stacks, multiply the capacitance values by the number of
dies in the stack.
2.
3.
Sampled, but not 100% tested.
Silicon die capacitance only; add 1 pF for discrete packages.
15.3
AC Read Specifications
Table 27: AC Read Specifications (Sheet 1 of 2)
Num
Symbol
Parameter
Min
Max
Unit
Note
Asynchronous Specifications
Easy BGA
TSOP
100
110
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
-
R1
R2
R3
t
t
t
Read cycle time
AVAV
AVQV
ELQV
-
Easy BGA
TSOP
100
110
100
110
25
-
-
Address to output valid
CE# low to output valid
Easy BGA
TSOP
-
-
-
R4
R5
R6
R7
R8
R9
tGLQV
tPHQV
tELQX
tGLQX
tEHQZ
tGHQZ
OE# low to output valid
RST# high to output valid
-
-
1,2
1
150
-
CE# low to output in low-Z
OE# low to output in low-Z
CE# high to output in high-Z
OE# high to output in high-Z
0
0
-
1,3
1,2,3
-
20
-
15
1,3
Output hold from first occurring address, CE#, or
OE# change
R10
tOH
0
-
ns
R11
R12
R13
R15
R16
R17
tEHEL
tELTV
tEHTZ
tGLTV
CE# pulse width high
17
-
-
ns
ns
ns
ns
ns
ns
1
CE# low to WAIT valid
CE# high to WAIT high-Z
OE# low to WAIT valid
OE# low to WAIT in low-Z
OE# high to WAIT in high-Z
17
20
17
-
-
1,3
1
-
t
t
0
-
GLTX
1,3
20
GHTZ
Latching Specifications
Datasheet
53
Apr 2009
Order Number: 320002-08
P30-65nm
Table 27: AC Read Specifications (Sheet 2 of 2)
Num
Symbol
Parameter
Address setup to ADV# high
Min
Max
Unit
Note
R101
R102
tAVVH
tELVH
10
10
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
CE# low to ADV# high
Easy BGA
TSOP
100
110
-
R103
t
ADV# low to output valid
1
VLQV
R104
R105
R106
R108
R111
tVLVH
tVHVL
tVHAX
ADV# pulse width low
ADV# pulse width high
Address hold from ADV# high
Page address access
10
10
9
-
-
1,4
1
t
t
-
25
-
APA
RST# high to ADV# high
30
phvh
Clock Specifications
R200
R201
R202
R203
fCLK
CLK frequency
CLK period
-
19.2
5
52
-
MHz
MHz
ns
tCLK
1,3,5
tCH/CL
tFCLK/RCLK
CLK high/low time
CLK fall/rise time
(5)
-
0.3
3
ns
Synchronous Specifications
R301
R302
R303
R304
R305
R306
R307
R311
R312
tAVCH/L
tVLCH/L
tELCH/L
tCHQV / tCLQV
tCHQX
Address setup to CLK
ADV# low setup to CLK
CE# low setup to CLK
CLK to output valid
9
9
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,6
9
-
-
17
-
Output hold from CLK
Address hold from CLK
CLK to WAIT valid
3
1,6
1,4,6
1,6
1
tCHAX
10
-
-
tCHTV
17
-
tCHVL
CLK Valid to ADV# Setup
WAIT Hold from CLK
3
tCHTX
3
-
1,6
Notes:
1.
See Figure 18, “AC Input/Output Reference Waveform” on page 52 for timing measurements and max
allowable input slew rate.
2.
3.
4.
5.
6.
OE# may be delayed by up to t
Sampled, not 100% tested.
– t
after CE#’s falling edge without impact to t
ELQV
GLQV ELQV.
Address hold in synchronous burst mode is t
or t
, whichever timing specification is satisfied first.
VHAX
CHAX
Synchronous read mode is not supported with TTL level inputs.
Applies only to subsequent synchronous reads.
Datasheet
54
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 21: Asynchronous Single-Word Read (ADV# Low)
R1
R2
Address [A]
ADV#
R3
R8
CE# [E}
R4
R9
OE# [G]
R15
R17
WAIT [T]
R7
R6
Data [D/Q]
R5
RST# [P]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 22: Asynchronous Single-Word Read (ADV# Latch)
R1
R2
Address [A]
A[1:0][A]
R101
R105
R106
ADV#
CE# [E}
OE# [G]
WAIT [T]
R3
R8
R4
R9
R15
R17
R7
R6
R10
Data [D/Q]
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Datasheet
55
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 23: Asynchronous Page-Mode Read Timing
R2
A[Max:4] [A]
A[3:0]
Valid Address
R10
R10
R10
R10
0
1
2
F
R101
R105
R106
ADV#
R3
R8
CE# [E]
R4
R9
OE# [G]
WAIT [T]
R6
R13
R108
Q2
R108
Q3
R108
Q16
DATA [D/Q]
Q1
Note: WAIT shown deasserted during asynchronous read mode (RCR.10=0, WAIT asserted low).
Figure 24: Synchronous Single-Word Array or Non-array Read Timing
R301
R306
CLK [C]
R2
Address [A]
R101
R104
R106
R105
ADV# [V]
R303
R102
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R7
R9
R15
R307
R304
R17
R312
R4
R305
Data [D/Q]
1.
2.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
This diagram illustrates the case in which an n-word burst is initiated to the flash memory array and it is terminated by
CE# deassertion after the first word in the burst.
Datasheet
56
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 25: Continuous Burst Read, Showing An Output Delay Timing
R301
R302
R306
R304
R304
R304
CLK [C]
Address [A]
ADV# [V]
R2
R101
R106
R105
R303
R102
R3
CE# [E]
OE# [G]
R15
R307
R304
R312
WAIT [T]
R4
R7
R305
R305
R305
R305
Data [D/Q]
Notes:
1.
WAIT is driven per OE# assertion during synchronous array or non-array read, and can be configured to assert either
during or one data cycle before valid data.
At the end of Word Line; the delay incurred when a burst access crosses a 16-word boundary and the starting address is
not 4-word boundary aligned.
2.
Figure 26: Synchronous Burst-Mode Four-Word Read Timing
R302
R301
R306
CLK [C]
Address [A]
ADV# [V]
R2
R101
A
R105
R102
R106
R303
R3
R8
CE# [E]
OE# [G]
WAIT [T]
R9
R15
R17
R307
R4
R304
R305
Q0
R7
R304
R10
Data [D/Q]
Q1
Q2
Q3
Note: WAIT is driven per OE# assertion during synchronous array or non-array read. WAIT asserted during initial latency and
deasserted during valid data (RCR.10 = 0, WAIT asserted low).
Datasheet
57
Apr 2009
Order Number: 320002-08
P30-65nm
15.4
AC Write Specifications
Table 28: AC Write Specifications
Num
W1
Symbol
tPHWL
Parameter
Min
Max
Unit
Notes
RST# high recovery to WE# low
CE# setup to WE# low
150
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
1,2,3
1,2,3
1,2,4
W2
tELWL
W3
tWLWH
tDVWH
tAVWH
tWHEH
tWHDX
tWHAX
tWHWL
tVPWH
tQVVL
WE# write pulse width low
Data setup to WE# high
Address setup to WE# high
CE# hold from WE# high
Data hold from WE# high
Address hold from WE# high
WE# pulse width high
50
50
50
0
W4
W5
W6
1,2
W7
0
W8
0
W9
20
200
0
1,2,5
W10
W11
W12
W13
W14
W16
V
V
setup to WE# high
PP
PP
1,2,3,7
hold from Status read
tQVBL
WP# hold from Status read
WP# setup to WE# high
WE# high to OE# low
0
1,2,3,7
tBHWH
tWHGL
tWHQV
200
0
1,2,9
WE# high to read valid
t
+ 35
1,2,3,6,10
AVQV
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid
Write to Synchronous Read Specifications
0
-
ns
1,2,3,6,8
W19
W20
W28
tWHCH/L
tWHVH
tWHVL
WE# high to Clock valid
WE# high to ADV# high
WE# high to ADV# low
19
19
7
-
-
-
ns
ns
ns
1,2,3,6,10
Write Specifications with Clock Active
W21
W22
tVHWL
tCHWL
ADV# high to WE# low
Clock high to WE# low
-
-
20
20
ns
ns
1,2,3,11
Notes:
1.
2.
3.
4.
Write timing characteristics during erase suspend are the same as write-only operations.
A write operation can be terminated with either CE# or WE#.
Sampled, not 100% tested.
Write pulse width low (t
or t
) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
WLWH
ELEH
WLWH
(whichever occurs first). Hence, t
= t
= t
= t
.
ELWH
ELEH
WLEH
5.
Write pulse width high (t
or t
) is defined from CE# or WE# high (whichever occurs first) to CE# or WE# low
WHWL
EHEL
(whichever occurs last). Hence, t
= t
= t
= t
).
EHWL
WHWL
EHEL
WHEL
6.
7.
8.
tWHVH or tWHCH/L must be met when transiting from a write cycle to a synchronous burst read.
V
and WP# should be at a valid level until erase or program success is determined.
PP
This specification is only applicable when transiting from a write cycle to an asynchronous read. See spec W19 and W20
for synchronous read.
9.
10.
When doing a Read Status operation following any command that alters the Status Register, W14 is 20 ns.
Add 10 ns if the write operation results in a RCR or block lock status change, for the subsequent read operation to
reflect this change.
11.
These specs are required only when the device is in a synchronous mode and clock is active during address setup phase.
Datasheet
58
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 27: Write-to-Write Timing
W5
W8
W5
W8
Address [A]
W2
W6
W2
W6
CE# [E}
W3
W9
W3
WE# [W]
OE# [G]
W4
W7
W4
W7
Data [D/Q]
W1
RST# [P]
Figure 28: Asynchronous Read-to-Write Timing
R1
R2
W5
W8
Address [A]
R3
R8
R9
CE# [E}
R4
OE# [G]
W2
W3
W6
WE# [W]
R15
R17
WAIT [T]
R7
R6
W7
R10
W4
Data [D/Q]
RST# [P]
Q
D
R5
Note: WAIT deasserted during asynchronous read and during write. WAIT High-Z during write per OE# deasserted.
Datasheet
59
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 29: Write-to-Asynchronous Read Timing
W5
W8
R1
Address [A]
ADV# [V]
W2
W6
R10
CE# [E}
WE# [W]
OE# [G]
WAIT [T]
W3
W18
W14
R15
R17
R4
R2
R3
R8
R9
W4
W7
Data [D/Q]
RST# [P]
D
Q
W1
Figure 30: Synchronous Read-to-Write Timing
Latency Count
R301
R302
R306
CLK [C]
R2
W5
R101
W18
Address [A]
R105
R102
R106
R104
ADV# [V]
R303
R11
R13
R3
W6
CE# [E]
OE# [G]
R4
R8
W21
W22
W21
W22
W2
W8
W15
W3
W9
WE#
R16
R307
R304
R312
WAIT [T]
R7
R305
W7
Q
D
D
Data [D/Q]
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low). Clock is
ignored during write operation.
Datasheet
60
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 31: Write-to-Synchronous Read Timing
R302
R301
R2
CLK
W5
W8
R306
R106
Address [A]
R104
R303
ADV#
W6
W2
R11
CE# [E}
W18
W19
W20
W3
WE# [W]
OE# [G]
WAIT [T]
R4
R15
R3
R307
W7
R304
R305
R304
W4
D
Q
Q
Data [D/Q]
RST# [P]
W1
Note: WAIT shown deasserted and High-Z per OE# deassertion during write operation (RCR.10=0, WAIT asserted low).
Datasheet
61
Apr 2009
Order Number: 320002-08
P30-65nm
16.0
Program and Erase Characteristics
Table 29: Program and Erase Specifications
V
V
PPH
PPL
Note
s
Num
Symbol
Parameter
Unit
Min
Conventional Word Programming
Single word 150
Buffered Programming
Typ
Max
Min
Typ
Max
Program
Time
W200
t
-
456
-
150
456
µs
1
PROG/W
Aligned 32-Word, BP
time (32 words)
-
-
-
-
-
176
216
272
396
700
716
900
-
-
-
-
-
176
216
272
396
700
716
900
Aligned 64-Wd, BP time
(64 words)
Program
Time
Aligned 128-Wd, BP time
(128 words)
W250
t
1140
1690
3016
1140
1690
3016
µs
1
PROG
Aligned 256-Wd, BP time
(256 words)
one full buffer, BP time
(512 words)
Buffered Enhanced Factory Programming
W451
W452
t
t
Single byte
BEFP Setup
n/a
n/a
n/a
n/a
n/a
n/a
-
0.5
-
-
-
1,2
1
BEFP/B
Program
µs
5
BEFP/Setup
Erase and Suspend
W500
W501
W600
W601
W602
t
t
t
t
t
32-KByte Parameter
128-KByte Main
Program suspend
Erase suspend
-
0.8
0.8
20
4.0
4.0
25
25
-
-
-
-
-
-
0.8
0.8
20
4.0
4.0
25
25
-
ERS/PB
ERS/MB
SUSP/P
SUSP/E
ERS/SUSP
Erase Time
s
-
1
-
Suspend
Latency
-
20
20
µs
Erase to Suspend
-
blank check
-
500
500
1,3
W702
t
blank check Main Array Block
3.2
-
-
3.2
-
ms
BC/MB
Notes:
1.
Typical values measured at T = +25 °C and nominal voltages. Performance numbers are valid for all speed versions.
C
Excludes system overhead. Sampled, but not 100% tested.
2.
3.
Averaged over entire device.
W602 is the typical time between an initial block erase or erase resume command and the a subsequent erase suspend
command. Violating the specification repeatedly during any particular block erase may cause erase failures.
Datasheet
62
Apr 2009
Order Number: 320002-08
P30-65nm
17.0
Ordering Information
17.1
Discrete Products
Figure 32: Decoder for Discrete P30-65nm
J S 2 8 F 2 5 6 P 3 0 B F
Device Lithography
65nm
Package Designator
TE =56 -Lead TSOP, leaded
JS = 56 -Lead TSOP, lead-free
RC =64-Ball Easy BGA,leaded
PC=64- Ball Easy BGA ,lead-free
Parameter Location
B = Bottom Parameter
T = Top Parameter
Product Line Designator
Product Family
28F = Numonyx™ Flash Memory
P 30 = Numonyx™ StrataFlash® Embedded Memory (P30)
Device Density
256 =256-Mbit
VCC =1. 7– 2. 0V
VCCQ =1.7– 3. 6V
Table 30: Valid Combinations for Discrete Products
256-Mbit
TE28F256P30BF
TE28F256P30TF
JS28F256P30BF
JS28F256P30TF
RC28F256P30BF
RC28F256P30TF
PC28F256P30BF
PC28F256P30TF
Datasheet
63
Apr 2009
Order Number: 320002-08
P30-65nm
17.2
SCSP Products
Figure 33: Decoder for SCSP P30-65nm
P F 4 8 F 4 4 0 0 P 0 V B 0 E
Package Designator
Device Details
E = 65nm lithography
RD = Numonyx™ SCSP, leaded
PF = Numonyx™ SCSP, lead-free
RC = 64- Ball Easy BGA , leaded
PC = 64- Ball Easy BGA, lead- free
Ballout Descriptor
Q = QUAD+ ballout
0 = Discrete ballout
Product Designator
48F = Numonyx™ Flash Memory Only
Parameter Location
B = Bottom Parameter
T = Top Parameter
Device Density
0
4
= No die
= 256-Mbit
I/ O Voltage, CE # Configuration
Z = Individual Chip Enable(s)
V = Virtual Chip Enable(s)
VCC = 1. 7 to 2. 0 V
Product Family
VCCQ =1. 7 to 3.6 V
P = Numonyx™ StrataFlash® Embedded Memory (P30)
0 = No die
Table 31: Valid Combinations for Dual-Die Products
*
256-Mbit
512-Mbit
RD48F4400P0VBQE
PF48F4400P0VBQE
RC48F4400P0VB0E
PC48F4400P0VB0E
PF48F4000P0ZBQE
PF48F4000P0ZTQE
Note:
The “B” parameter is used for Top(Die1)/Bot(Die2) stack option in the 512-Mbit density.
Datasheet
64
Apr 2009
Order Number: 320002-08
P30-65nm
Appendix A Supplemental Reference Information
A.1
Common Flash Interface Tables
The Common Flash Interface (CFI) is part of an overall specification for multiple
command-set and control-interface descriptions. This appendix describes the database
structure containing the data returned by a read operation after issuing the Read CFI
command (see Section 6.0, “Command Set” on page 21). System software can parse
this database structure to obtain information about the flash device, such as block size,
density, bus width, and electrical specifications. The system software will then know
which command set(s) to use to properly perform flash writes, block erases, reads and
otherwise control the flash device.
A.1.1
CFI Structure Output
The CFI database allows system software to obtain information for controlling the flash
device. This section describes the device’s CFI-compliant interface that allows access to
CFI data.
CFI data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is the address relative to the maximum bus width supported by the device.
On this family of devices, the CFI table device starting address is a 10h, which is a word
address for x16 devices.
For a word-wide (x16) device, the first two CFI-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0
)
and 00h in the high byte (DQ15-8).
At CFI addresses containing two or more bytes of information, the least significant data
byte is presented at the lower address, and the most significant data byte is presented
at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 32: Summary of CFI Structure Output as a Function of Device and Mode
Hex
Hex
Code
51
52
59
ASCII
Value
"Q"
"R"
"Y"
Device
Offset
00010:
00011:
00012:
Device Addresses
Datasheet
65
Apr 2009
Order Number: 320002-08
P30-65nm
Table 33: Example of CFI Structure Output of x16 Devices
Offset
A -A
Hex Code
Value
D
-D
0
X
1
15
00010h
00011h
00012h
00013h
00014h
00015h
00016h
00017h
00018h
...
0051
0052
0059
“Q”
“R”
“Y”
P_ID
LO
PrVendor ID#
P_ID
HI
P
LO
PrVendor TblAdr
P
HI
A_ID
LO
AltVendor ID#
...
A_ID
...
HI
A.1.2
CFI Structure Overview
The CFI command causes the flash component to display the Common Flash Interface
(CFI) structure or “database.” The structure sub-sections and address locations are
summarized below.
Table 34: CFI Structure
00001-Fh Reserved
Reserved for vendor-specific information
Command set ID and vendor data offset
Device timing & voltage information
Flash device layout
00010h
0001Bh
00027h
CFI query identification string
System interface information
Device geometry definition
Vendor-defined additional information specific
to the Primary Vendor Algorithm
(3)
P
Primary Numonyx-specific Extended Query Table
Notes:
1.
Refer to the CFI Structure Output section and offset 28h for the detailed definition of offset address as a function of device
bus width and mode.
2.
3.
BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32-KWord).
Offset 15 defines “P” which points to the Primary Numonyx-specific Extended CFI Table.
A.1.3
Read CFI Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
Datasheet
66
Apr 2009
Order Number: 320002-08
P30-65nm
Table 35: CFI Identification
Offset Length
Description
Query-unique ASCII string “QRY“
Add. Hex Code Value
10h
3
10:
11:
12:
13:
14:
15:
16:
17:
--51
--52
--59
--01
--00
--0A
--01
--00
--00
--00
--00
"Q"
"R"
"Y"
13h
15h
17h
19h
2
2
2
2
Primary vendor command set and control interface ID code.
16-bit ID code for vendor-specified algorithms
Extended Query Table primary algorithmaddress
Alternate vendor command set and control interface ID code.
0000h means no second vendor-specified algorithmexists 18:
Secondary algorithmExtended Query Table address.
0000h means none exists
19:
1A:
Datasheet
67
Apr 2009
Order Number: 320002-08
P30-65nm
A.1.4
Device Geometry Definition
Table 36: System Interface Information
He x
Code
--17
Offset Length Description
Add.
1B:
Value
1.7V
1Bh
1Ch
1Dh
1Eh
1
1
1
1
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
V
CC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
1C:
1D:
1E:
--20
--85
--95
--08
2.0V
8.5V
bits 4–7 BCD volts
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
V
PP [programming] supply maximum program/erase voltage
bits 0–3 BCD 100 mV
9.5V
bits 4–7 HEX volts
1Fh
20h
21h
22h
23h
24h
25h
26h
1
1
1
1
1
1
1
1
“n” such that typical single w ord programtime-out = 2n µ-sec
“n” such that typical full buffer w rite time-out = 2n µ-sec
“n” such that typical block erase time-out = 2n m-sec
“n” such that typical full chip erase time-out = 2n m-sec
“n” such that maximum w ord program time-out = 2n times typical
“n” such that maximum buf f er w rite time-out = 2n times typical
“n” such that maximumblock erase time-out = 2n times typical
“n” such that maximum chip erase time-out = 2n times typical
1F:
20:
21:
22:
23:
24:
25:
26:
256µs
--0A 1024µs
--0A
--00
--01
1s
NA
512µs
--02 4096µs
--02
--00
4s
NA
Datasheet
68
Apr 2009
Order Number: 320002-08
P30-65nm
Table 37: Device Geometry Definition
He x
Code
Offset Length
Description
Add.
Value
See table below
27h
1
“n” such that device size = 2n in number of bytes
Flash device interface code assignment:
27:
"n" such that n+1 specifies the bit field that represents the flash device w idth
capabilities as described in the table:
7
6
5
4
3
x64
11
2
x32
10
1
x16
9
0
x8
8
28h
2
—
15
—
14
—
13
—
12
28:
--01
x16
—
—
—
—
—
—
—
—
29:
2A:
2B:
--00
--0A
--00
2Ah
2Ch
2
1
“n” such that maximumnumber of bytes in w rite buffer = 2n
1024
Number of erase block regions (x) w ithin device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions w ith one or
more contiguous same-size erase blocks.
See table below
2C:
3. Symmetrically blocked partitions have one blocking region
2Dh
31h
35h
4
4
4
Erase Block Region 1 Information
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
See table below
See table below
See table below
Erase Block Region 2 Information
bits 0–15 = y, y+1 = number of identical-size erase blocks
bits 16–31 = z, region erase block(s) size are z x 256 bytes
Reserved for future erase block region information
Address
256-Mbit
–B
–T
27:
28:
29:
2A:
2B:
2C:
2D:
2E:
2F:
30:
31:
32:
33:
34:
35:
36:
37:
38:
--19
--01
--00
--06
--00
--02
--03
--00
--80
--00
--FE
--00
--00
--02
--00
--00
--00
--00
--19
--01
--00
--06
--00
--02
--FE
--00
--00
--02
--03
--00
--80
--00
--00
--00
--00
--00
Datasheet
69
Apr 2009
Order Number: 320002-08
P30-65nm
A.1.5
Numonyx-Specific Extended CFI Table
Table 38: Primary Vendor-Specific Extended CFI
Offset(1) Length
P = 10Ah
Description
(Optional flash features and commands)
Hex
Add. Code Value
(P+0)h
(P+1)h
(P+2)h
(P+3)h
(P+4)h
(P+5)h
(P+6)h
(P+7)h
(P+8)h
3
Primary extended query table
10A
10B:
10C:
10D:
10E:
10F:
110:
111:
--50
--52
--49
--31
--34
--E6
--01
--00
"P"
"R"
"I"
"1"
"4"
Unique ASCII string “PRI“
1
1
4
Major version number, ASCII
Minor version number, ASCII
Optional feature and command support (1=yes, 0=no)
bits 11–29 are reserved; undefined bits are “0.” If bit 31 is
“1” then another 31 bit field of Optional features follows at
the end of the bit–30 field.
112: See table below
bit 0 Chip erase supported
bit 1 Suspend erase supported
bit 2 Suspend program supported
bit 3 Legacy lock/unlock supported
bit 4 Queued erase supported
bit 5 Instant individual block locking supported
bit 6 Protection bits supported
bit 7 Pagemode read supported
bit 8 Synchronous read supported
bit 9 Simultaneous operations supported
bit 10 Extended Flash Array Blocks supported
bit 0 = 0
bit 1 = 1
bit 2 = 1
bit 3 = 0
bit 4 = 0
bit 5 = 1
bit 6 = 1
bit 7 = 1
bit 8 = 1
bit 9 = 0
bit 10 = 0
No
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
See
table
below
bit 30 CFI Link(s) to follow
bit 30
bit 31
bit 31 Another "Optional Features" field to follow
(P+9)h
1
2
Supported functions after suspend: read Array, Status, Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
113:
--01
bit 0 Program supported after erase suspend
Block status register mask
bit 0 = 1
114:
115:
Yes
(P+A)h
(P+B)h
--03
--00
bits 2–15 are Reserved; undefined bits are “0”
bit 0 Block Lock-Bit Status register active
bit 1 Block Lock-Dow n Bit Status active
bit 4 EFA Block Lock-Bit Status register active
bit 0 = 1
Yes
Yes
No
No
1.8V
bit 1 = 1
bit 4 = 0
bit 5 = 0
Address
Discrete
512-Mbit
–T –B
–- –- die 1 (B) die 2 (T) die 1 (T) die 2 (B)
--00 --00 --40
–B
–T
(P+C)
112:
116:
--18
--00
--40
--00
(P+D)
PP
bits 0–3 BCD value in 100 mV
117:
--90
9.0V
bits 4–7 HEX value in volts
Datasheet
70
Apr 2009
Order Number: 320002-08
P30-65nm
Table 39: Protection Register Information
Offset(1) Length
Description
Hex
P = 10Ah
(P+E)h
(Optional flash features and commands)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
Add. Code Value
1
4
118:
--02
2
(P+F)h
(P+10)h
(P+11)h
(P+12)h
Protection Field 1: Protection Description
119:
11A:
11B:
11C:
--80
--00
--03 8 byte
--03 8 byte
80h
00h
This field describes user-available One Time Programmable
(OTP) Protection register bytes. Some are pre-programmed
w ith device-unique serial numbers. Others are user
programmable. Bits 0–15 point to the Protection register Lock
byte, the section’s first byte. The follow ing bytes are factory
pre-programmed and user-programmable.
bits 0–7 = Lock/bytes Jedec-plane physical low address
bits 8-15 = Lock/bytes Jedec-plane physical high address
bits 16-23 = "n" such that 2n =factory pre-programmed bytes
bits 24-31 = "n" such that 2n =user programmable bytes
(P+13)h
(P+14)h
(P+15)h
(P+16)h
(P+17)h
(P+18)h
(P+19)h
(P+1A)h
(P+1B)h
(P+1C)h
10
Protection Field 2: Protection Description
Bits 0–31 point to the Protection register physical Lock-w ord
address in the Jedec-plane.
11D:
11E:
11F:
120:
121:
122:
123:
124:
125:
126:
--89
--00
--00
--00
--00
--00
--00
--10
--00
89h
00h
00h
00h
0
0
0
16
0
16
Follow ing bytes are factory or user-programmable.
bits 32–39 = “n” such that n = factory pgm'd groups (low byte)
bits 40–47 = “n” such that n = factory pgm'd groups (high byte)
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n” such that n = user pgm'd groups (low byte)
bits 64–71 = “n” such that n = user pgm'd groups (high byte)
bits 72–79 = “n” such that 2n = user programmable bytes/group
--04
Datasheet
71
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 34: Burst Read Information
Offset(1) Length
P = 10Ah
Description
(Optional flash features and commands)
Page Mode Read capability
Hex
Add. Code Value
(P+1D)h
1
127:
--05 32 byte
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device w ord w idth to
determine page-mode data output w idth. 00h indicates no
read page buffer.
(P+1E)h
(P+1F)h
1
1
Number of synchronous mode read configuration fields that follow . 00h
indicates no burst capability.
128:
129:
--04
--01
4
4
Synchronous mode read capability configuration 1
Bits 3–7 = Reserved
bits 0–2 “n” such that 2n+1 HEX value represents the maximumnumber of
continuous synchronous reads w hen the device is configured for its
maximumw ord w idth. A value of 07h indicates that the device is capable of
continuous linear bursts that w ill output data until the internal burst counter
reaches the end of the device's burstable address space. This filed's 3-bit
value can be w ritten directly to the Read Configuration Register bits 0-2 if
the device is configured for its maximumw ord w idth. See offset 28h for w ord
w idth to determine the burst data output w idth.
(P+20)h
(P+21)h
(P+22)h
1
1
1
Synchronous mode read capability configuration 2
Synchronous mode read capability configuration 3
Synchronous mode read capability configuration 4
12A:
12B:
12C:
--02
--03
--07
8
16
Cont
Table 40: Partition and Erase Block Region Information
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
Len
Number of device hardw are-partition regions w ithin the device.
x = 0: a single hardw are partition device (no fields follow ).
x specifies the number of device partition regions containing
one or more contiguous erase block regions.
1
12D:
12D:
(P+23)h (P+23)h
Datasheet
72
Apr 2009
Order Number: 320002-08
P30-65nm
Table 41: Partition Region 1 Information
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
12E
12F
130:
131:
132:
Len
(P+24)h (P+24)h Data size of this Parition Region Information field
(P+25)h (P+25)h (# addressable locations, including this field)
(P+26)h (P+26)h Number of identical partitions w ithin the partition region
(P+27)h (P+27)h
(P+28)h (P+28)h Number of program or erase operations allow ed in a partition
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
2
12E:
12F
130:
131:
132:
2
1
(P+29)h (P+29)h Simultaneous program or erase operations allow ed in other partitions w hile a
partition in this region is in Program mode
1
1
1
133:
134:
135:
133:
134:
135:
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2A)h (P+2A)h Simultaneous program or erase operations allow ed in other partitions w hile a
partition in this region is in Erase mode
bits 0–3 = number of simultaneous Program operations
bits 4–7 = number of simultaneous Erase operations
(P+2B)h (P+2B)h Types of erase block regions in this Partition Region.
x = 0 = no erase blocking; the Partition Region erases in bulk
x = number of erase block regions w / contiguous same-size
erase blocks. Symmetrically blocked partitions have one
blocking region. Partition size = (Type 1 blocks)x(Type 1 block sizes)
+(Type 2 blocks)x(Type 2 block sizes)+...+(Type n blocks)x(Type n block
sizes)
Datasheet
73
Apr 2009
Order Number: 320002-08
P30-65nm
Table 42: Partition Region 1 Information (continued)
Offset(1)
P = 10Ah
Bottom Top
See table below
Address
Description
(Optional flash features and commands)
Bot
Top
136:
137:
138:
139:
13A:
13B:
13C:
Len
(P+2C)h (P+2C)h Partition Region 1 Erase Block Type 1 Information
4
136:
137:
138:
139:
13A:
13B:
13C:
(P+2D)h (P+2D)h
(P+2E)h (P+2E)h
(P+2F)h (P+2F)h
(P+30)h (P+30)h Partition 1 (Erase Block Type 1)
(P+31)h (P+31)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+32)h (P+32)h Partition 1 (erase block Type 1) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+33)h (P+33)h Partition 1 (erase block Type 1) page mode and synchronous mode capabilities
defined in Table 10.
1
6
13D:
13D:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partition Region 1 (Erase Block Type 1) Programming Region Information
(P+34)h (P+34)h
(P+35)h (P+35)h
(P+36)h (P+36)h
(P+37)h (P+37)h
(P+38)h (P+38)h
(P+39)h (P+39)h
bits 0–7 = x, 2^x = Programming Region aligned size (bytes)
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode valid size in bytes
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A:
bits 24-31 = Reserved
bits 32-39 = z = Control Mode invalid size in bytes
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
(P+3A)h (P+3A)h Partition Region 1 Erase Block Type 2 Information
4
(P+3B)h (P+3B)h
(P+3C)h (P+3C)h
(P+3D)h (P+3D)h
(P+3E)h (P+3E)h Partition 1 (Erase Block Type 2)
(P+3F)h (P+3F)h Block erase cycles x 1000
bits 0–15 = y, y+1 = # identical-size erase blks in a partition
bits 16–31 = z, region erase block(s) size are z x 256 bytes
2
1
(P+40)h (P+40)h Partition 1 (erase block Type 2) bits per cell; internal EDAC
bits 0–3 = bits per cell in erase region
bit 4 = internal EDAC used (1=yes, 0=no)
bits 5–7 = reserve for future use
(P+41)h (P+41)h Partition 1 (erase block Type 2) page mode and synchronous mode capabilities
defined in Table 10.
1
6
14B:
14B:
bit 0 = page-mode host reads permitted (1=yes, 0=no)
bit 1 = synchronous host reads permitted (1=yes, 0=no)
bit 2 = synchronous host w rites permitte
Partition Region 1 (Erase Block Type 2) Programming Region Information
(P+42)h (P+42)h
(P+43)h (P+43)h
(P+44)h (P+44)h
(P+45)h (P+45)h
(P+46)h (P+46)h
(P+47)h (P+47)h
bits 0–7 = x, 2^x = Programming Region aligned size (
)
14C:
14D:
14E:
14F:
150:
151:
bytes
14C:
14D:
14E:
14F:
150:
151:
bits 8–14 = Reserved; bit 15 = Legacy flash operation (ignore 0:7)
bits 16–23 = y = Control Mode
bits 24-31 = Reserved
size in bytes
valid
bits 32-39 = z = Control Mode
size in bytes
invalid
bits 40-46 = Reserved; bit 47 = Legacy flash operation (ignore 23:16 & 39:32)
Datasheet
74
Apr 2009
Order Number: 320002-08
P30-65nm
Table 43: Partition and Erase Block Region Information
Partition and Erase-block Region Information
Address
256-Mbit
–B
–T
12D:
--01
--24
--00
--01
--00
--11
--00
--00
--02
--03
--00
--80
--00
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--FE
--00
--00
--02
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--01
--24
--00
--01
--00
--11
--00
--00
--02
--FE
--00
--00
--02
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
--03
--00
--80
--00
--64
--00
--02
--03
--00
--80
--00
--00
--00
--80
12E:
12F:
130:
131:
132:
133:
134:
135:
136:
137:
138:
139:
13A
13B:
13C:
13D:
13E:
13F:
140:
141:
142:
143:
144:
145:
146:
147:
148:
149:
14A
14B:
14C:
14D:
14E:
14F:
150:
151:
Datasheet
75
Apr 2009
Order Number: 320002-08
P30-65nm
Table 44: CFI Link Information
Offset(1) Len
Description
(Optional flash features and commands)
CFI Link Field bit definitions
Hex
P = 10Ah
(P+48)h
(P+49)h
(P+4A)h
(P+4B)h
Add. Code Value
4
1
152:
See
table
Bits 0–9 = Address offset (w ithin 32Mbit segment) of referenced CFI table
Bits 10–27 = nth 32Mbit segment of referenced CFI table
Bits 28–30 = Memory Type
153:
154:
155:
below
Bit 31 = Another CFI Link field immediately follow s
CFI Link Field Quantity Subfield definitions
Bits 0–3 = Quantity field (n such that n+1 equals quantity)
Bit 4 = Table & Die relative location
(P+4C)h
156:
See
table
below
Bit 5 = Link Field & Table relative location
Bits 6–7 = Reserved
Address
Discrete
512-Mbit
–B
–-
–T
–-
–B
–T
die 1 (B)
--10
--20
die 2 (T)
die 1 (T)
--10
--20
die 2 (B)
--FF
--FF
152:
153:
154:
155:
156:
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--FF
--00
--00
--FF
--00
--10
--00
--10
--FF
--FF
Datasheet
76
Apr 2009
Order Number: 320002-08
P30-65nm
A.2
Flowcharts
Figure 35: Word Program Flowchart
Start
Command Cycle
- Issue Program Command
- Address = location to program
- Data = 0x40
Data Cycle
- Address = location to program
- Data = Data to program
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal D7
No
No
Program Suspend
See Suspend/
Resume Flowchart
No
D7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
Error-Handler
User Defined Routine
End
Datasheet
77
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 36: Program/Erase Suspend/Resume Flowchart
Start
Command Cycle
- Issue Suspend Command
- Address = any device address
- Data = 0xB0
Command Cycle
Wait
tSUSP
- Issue Resume Command
- Address = any device address
- Data = 0xD0
Read Status Register
See Status Register
Flowchart
Erase
Suspended ?
(SR.6 = '1')
Program
Suspended ?
(SR.2 = '1')
Program Device
See Program
Flowchart
Yes
No
Yes
Program ?
Yes
No
No
Program
Suspended ?
(SR.2 = '1')
Yes
Yes
Read ?
Read Device
No
No
Yes
Error Handler
User-Defined Routine
Any Errors ?
No
End
Datasheet
78
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 37: Buffer Program Flowchart
Bus
Operation
Command
Comments
Data = E8H
Write to
Buffer
Write
Read
Addr = Block Address
Start
SR.7 = Valid
Addr = Block Address
Device
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Use Single Word
Supports Buffer
Standby
No
Programming
Writes?
Yes
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes1, 2)
Set Timeout or
Loop Counter
Write
(Notes3, 4)
Data = Write Buffer Data
Addr = Start Address
Get Next
Target Address
Write
(Notes5, 6)
Data = Write Buffer Data
Addr = Block Address
Issue Write to Buffer
Command E8h and
Block Address
Program
Confirm
Data = D0H
Addr = Block Address
Write
Read
Status register Data
CE# and OE# low updates SR
Addr = Block Address
Read Status Register
(at Block Address)
Check SR.7
1 = WSM Ready
0 = WSM Busy
No
Standby
Timeout
or Count
Expired?
0 = No
Is WSM Ready?
SR.7 =
1. Word count values on DQ0-DQ7 are loaded into the Count
register. Count ranges for this device are N = 0000h to 0001Fh.
2. The device outputs the status register when read.
3. Write Buffer contents will be programmed at the device start
address or destination flash address.
Yes
1 = Yes
Write Word Count,
Block Address
4. Align the start address on a Write Buffer boundary for
maximum programming performance(i.e., A4–A0 of the start
address = 0).
Write Buffer Data,
Start Address
5. The device aborts the Buffered Program command if the
current address is outside the original block address.
6. The Status register indicates an "improper command
sequence" if the Buffered Program command is aborted. Follow
this with a Clear Status Register command.
X = X + 1
Write Buffer Data,
Block Address
X = 0
Full status check can be done after all erase and write
sequences complete. Write FFh after the last operation to reset
the device to read array mode.
No
No
Abort Bufferred
Program?
X = N?
Yes
Yes
Write Confirm D0h
and Block Address
Write to another
Block Address
Buffered Program
Aborted
Read Status Register
No
Suspend
Program
Loop
Yes
0
Suspend
Program
SR.7 =?
Full Status
Check if Desired
1
Yes
Another Buffered
Programming?
No
Program Complete
Datasheet
79
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 38: BEFP Flowchart
Setup Phase
Start
Program/Verify Phase
Exit Phase
Read Status
Register
Read Status
Register
A
B
Issue BEFP Setup Cmd
(Data = 0x80)
No (SR.0=1)
Buffer Ready ?
No (SR.7=0)
BEFP Exited ?
Issue BEFP Confirm Cmd
(Data = 00D0h)
Yes (SR.0=0)
Write Data Word to Buffer
Yes (SR.7=1)
BEFP
Setup
Delay
Full Status
Register check for
errors
No
Buffer Full ?
Yes
Read Status
Register
Finish
Read Status
Register
Yes (SR.7=0)
BEFP Setup
Done ?
A
No (SR.0=1)
No (SR.7=1)
Program
Done ?
SR Error Handler
(User-Defined)
Yes (SR.0=0)
Exit
Program
Yes
More Data ?
No
Write 0xFFFFh outside Block
B
Datasheet
80
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 39: Block Erase Flowchart
Start
Command Cycle
- Issue Erase command
- Address = Block to be erased
- Data = 0x20
Confirm Cycle
- Issue Confirm command
- Address = Block to be erased
- Data = Erase confirm (0xD0)
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
No
Erase Suspend
See Suspend/
Resume Flowchart
Yes
No
SR.7 = '1'
?
Suspend
?
Errors
?
Yes
Yes
Error-Handler
User Defined Routine
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
81
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 40: Block Lock Operations Flowchart
Start
No
Check Lock
Status ?
Command Cycle
- Issue Block Lock Setup Command
- Address = block address
- Data = 0x60
Yes
Command Cycle
- Issue Read Device ID Command
- Address = block base address + 0x2
- Data = 0x90
Data Cycle
- Issue Lock/Unlock Command
- Address = block address
- Data = 0x01 (Lock Block) -or-
0xD0 (Unlock Block) -or-
Data Cycle
- Read Block Lock Status
0x2F (Lock Down Block)
Block Status WP# D1
D0
0
1
Unlocked
Locked
1
1
0
0
0
1
Read Status Register
See Status Register
Flowchart
Locked Down
1
Done
Yes
No
Error Handler
User-Defined Routine
Errors ?
Datasheet
82
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 41: Protection Register Programming Flowchart
Start
OTP Program Setup
- Write 0xC0
- OTP Address
Confirm Data
- Write OTP Address and Data
Check Ready Status
- Read Status Register Command not required
- Perform read operation
- Read Ready Status on signal SR.7
No
SR.7 = '1'
?
Yes
Read Status Register
- Toggle CE# or OE# to update Status Register
- See Status Register Flowchart
End
Datasheet
83
Apr 2009
Order Number: 320002-08
P30-65nm
Figure 42: Status Register Flowchart
Start
Command Cycle
- Issue Status Register Command
- Address = any device address
- Data = 0x70
Data Cycle
- Read Status Register SR[7:0]
No
SR7 = '1'
Yes
Yes
- Set/Reset
by WSM
Erase Suspend
See Suspend/Resume Flowchart
SR6 = '1'
No
Yes
Program Suspend
See Suspend/Resume Flowchart
SR2 = '1'
No
Error
Command Sequence
Yes
Yes
SR5 = '1'
SR4 = '1'
No
No
Error
Erase Failure
Yes
Error
Program Failure
SR4 = '1'
No
- Set by WSM
- Reset by user
- See Clear Status
Register Command
Yes
Error
< VPENLK/PPLK
SR3 = '1'
VPEN/PP
No
Yes
Error
Block Locked
SR1 = '1'
No
End
Datasheet
84
Apr 2009
Order Number: 320002-08
P30-65nm
A.3
Write State Machine
The Next State Table shows the command state transitions (Next State Table) based on
incoming commands. Only one partition can be actively programming or erasing at a
time. Each partition stays in its last read state (Read Array, Read Device ID, Read CFI
or Read Status Register) until a new command changes it. The next WSM state does
not depend on the partition’s output state.
Note: IS refers to Illegal State in the Next State Tables
Table 45: Next State Table for P30-65nm (Sheet 1 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
N/A
N/A
N/A
N/A
Ready
Ready
Ready
Ready
Ready
(Lock Ready
Ready
(Set
Ready (Lock
Error [Botch])
(Lock
Ready (Lock Error
[Botch])
Error (Lock
Lock/RCR/ECR Setup
Ready (Lock Error [Botch])
down
[Botc Block)
h])
CR)
Block)
Setup
OTP Busy
OTP Busy
N/A
N/A
OTP Busy
OTP Busy
N/A
Ready
N/A
IS in
OTP
Busy
OTP
IS in OTP
Busy
Illegal State in OTP
Busy
OTP Busy
Pgm Busy
OTP Busy
OTP Busy
OTP
Busy
Busy
IS in OTP Busy
Setup
OTP Busy
OTP Busy
Word Program Busy
N/A
N/A
Pgm Busy
Pgm Busy
IS in
Pgm
Busy
Pgm
Busy
IS in Pgm
Busy
Pgm Pgm
Busy Susp
Busy
Word Pgm Busy
IS in Word Pgm Busy
Word Pgm Busy
Ready
IS in Pgm Busy
Word Pgm Busy
Pgm
Word
Program
IS in
Susp Word
Pgm
Susp
IS in Pgm
Susp
Pgm
Busy
Illegal State in Pgm
Suspend
Word Program
Suspend
Suspend
Pgm Pgm Suspend
Susp
Pgm Susp
(Er
bits
Pgm
N/A
Word Pgm Susp
Susp
N/A
N/A
clear)
IS in Pgm
Suspend
EFI Setup
Sub-function
Setup
Word Program Suspend
Sub-function Setup
Sub-op-code Load 1
Sub-op-code
Load 1
Sub-function Load 2 if word count >0, else Sub-function confirm
Sub-function
Load 2
Sub-function
Confirm
Sub-function Confirm if data load in program buffer is complete, ELSE Sub-function Load 2
S-fn
Ready (Error [Botch])
Ready (Error [Botch])
Busy
EFI
IS in
S-fn
Busy
S-fn
Illegal State S-fn
S-fn
Sub-function Busy
S-fn Busy
S-fn Busy
IS in S-fn Busy
S-fn Busy
S-fn Busy
S-fn Susp
Busy
in S-fn Busy Busy Susp
Ready
N/A
IS in Sub-function
Busy
Sub-function Busy
S-fn
IS in
Susp
S-fn
Susp
Illegal State S-fn
in S-fn Busy Busy
S-fn
Sub-function Susp
IS in S-fn Susp
S-fn Sub-function
Susp
S-fn Suspend (Er
IS in S-fn Susp
S-fn Suspend
N/A
Susp
bits
clear)
Sub-function Suspend
Datasheet
85
Apr 2009
Order Number: 320002-08
P30-65nm
Table 45: Next State Table for P30-65nm (Sheet 2 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
Setup
BP Load 1 (8)
BP Load 1
BP Load 2 if word count >0, else BP confirm
Ready BP Confirm if data
(Error load in program
[Botc buffer is complete,
N/A
BP Load 2 (8)
BP Confirm if data load in program buffer is complete, ELSE BP load 2
BP
h])
else BP load 2
BP Confirm
Ready (Error [Botch])
Ready (Error [Botch])
Busy
Buffer
IS in
BP
Busy
Pgm
BP
Busy
Illegal State
in BP Busy
BP
BP
BP Busy
BP Busy
BP Busy
BP Busy
IS in BP Busy
BP Busy
BP Busy
Busy Susp
Ready
N/A
(BP)
IS in BP Busy
BP Susp
BP
Susp
(Er
IS in
BP
Susp
BP
Susp
Illegal State
in BP Busy
BP
Busy
BP
Susp
BP Suspend
BP Suspend
IS in BP Susp
BP Suspend
N/A
BP Susp
bits
clear)
IS in BP Susp
Setup
BP Suspend
Erase
Busy
Ready (Err
Botch0])
Ready (Error [Botch])
Ready (Error [Botch])
N/A
N/A
N/A
IS in
Erase
Busy
IS in Erase Erase Erase
Busy Busy Susp
Busy
Erase Erase Busy
Busy
Erase Busy
IS in Erase Busy
Erase Busy
Ers Busy
IS in Erase Busy
Erase Busy
Ready
Lock/
RCR/
ECR
Erase
Word
Pgm
EFI
Setup
in
BP
Setup
in
Erase
Susp
IS in
Erase
Susp
Erase Setup
IS in Erase Erase
Erase
Erase
Susp
Erase
Susp
Suspend
(Er
bits
Setup
in
Erase Suspend
N/A
N/A
Erase Susp
Susp
in
Erase
Susp
Erase
Susp
Suspend
Busy
Suspend
N/A
N/A
Erase
Susp
clear)
Erase
Susp
Erase Suspend
IS in Erase Susp
Setup
Word Pgm busy in Erase Suspend
Word
Pgm
busy
in
Erase
Susp
Word
Word
Pgm
Pgm
IS in
Pgm
Word Pgm
IS in Word
busy
in
Word Pgm busy in IS in Word Pgm busy Word Pgm busy in
Erase Susp in Ers Susp Erase Susp
Erase
Susp
Busy
busy busy in Erase Pgm busy in
Susp
in Ers
Susp
in Ers
Susp
Susp
Ers Susp
Erase
Susp
Illegal state(IS) in
IS in
Ers
Word Pgm Busy in
Ers Suspend
Pgm busy in Erase
Word Pgm busy in Erase Suspend
Word
Word
Suspend
Susp
Pgm in
Erase
Word
Pgm
Susp
in Ers
Susp
(Er
Word iS in
Pgm pgm
susp susp
in Ers in Ers
susp Susp
Word Word
Pgm Pgm
susp susp
in Ers in Ers
susp susp
Word
Pgm
susp
in Ers
susp
Pgm
busy
in
Erase
Susp
Suspend
Suspend
Word Pgm
susp in Ers
susp
iS in pgm
susp in Ers
Susp
iS in Word Pgm susp Word Pgm susp in
N/A
in Ers Susp
Ers susp
N/A
bits
clear)
Illegal State in
Word Program
Suspend in Erase
Suspend
Setup
BP Load 1 (8)
Word Pgm busy in Erase Suspend
BP Load 1 in Erase Suspend
BP Load 2 in Erase Suspend if word count >0, else BP confirm
Ers
Susp
(Error
[Botc
h])
BP Confirm in
Erase Suspend
when count=0,
ELSE BP load 2
N/A
BP Load 2 (8)
BP Confirm
BP Confirming Erase Suspend if data load in program buffer is complete, ELSE BP load 2 in Erase Suspend
Erase Suspend (Error [BotchBP])
IS in
Erase Susp (Error [Botch BP])
IS in BP Busy in
BP Busy in Ers Susp N/A
BP
BP
BP
Busy
in Ers
Susp
BP
Illegal State
Busy
in Ers
Susp
BP Busy in
Erase Susp
Susp
in Ers
Susp
BP Busy in Ers
Susp
Erase
Susp
BP in
Erase
BP Busy
Busy
in Ers
Susp
in BP Busy in
Ers Susp
BP Busy in Ers Susp
Erase Suspend
Suspend
IS in
Ers
IS in BP Busy
BP Busy in Erase Suspend
BP
Susp
IS in
BP
Susp
in Ers
Susp
Susp
BP
BP
BP
BP Suspend Illegal State
in Ers
Susp
in Ers
Susp
Busy
in Ers
Susp
BP Susp in
Ers Susp
Susp
in Ers
Susp
IS in BP Busy in
Erase Suspend
BP Susp in Ers
Susp
BP Susp
in Erase
Suspend
in BP Busy in
Ers Susp
Susp
(Er
BP Susp in Ers Susp N/A
N/A
bits
clear)
IS in BP Suspend
BP Suspend in Erase Suspend
Datasheet
86
Apr 2009
Order Number: 320002-08
P30-65nm
Table 45: Next State Table for P30-65nm (Sheet 3 of 3)
(1)
Command Input and Resulting Chip Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
EFI Setup
Sub-function Setup in Erase Suspend
Sub-function
Setup
Sub-op-code Load 1 in Erase Suspend
Sub-op-code
Load 1
Sub-function Load 2 in Erase Suspend if word count >0, else Sub-function confirm in Erase Suspend
Ers
Sub-function
Confirm if data
load in program
buffer is complete,
ELSESub-function
Load 2
N/A
Susp
(Error
[Botc
h])
Sub-function
Load 2
Sub-function Confirm in Erase Suspend if data load in program buffer is complete, ELSE Sub-function Load 2
Sub-function
Confirm
Erase Suspend (Error [Botch])
IS in
Erase Suspend (Error [Botch])
S-fn
Busy
in Ers
Susp
EFI in
S-fn
Busy
in Ers
Susp
S-fn
Susp
in Ers
Susp
S-fn
Busy
in Ers
Susp
Illegal State
Erase
S-fn Busy in
Ers Suspend
S-fn Busy in Ers
Susp
IS in S-fn Busy in
Ers Susp
S-fn Busy in Ers
S-fn Busy in Ers Erase
Sub-function Busy
in S-fn Busy
in Ers Susp
N/A
N/A
Suspend
Susp
Susp
Susp
IS in
Ers
Susp
IS in Sub-function
Busy
Sub-function Busy in Ers Susp
S-fn
IS in
S-fn
Susp
in Ers
Susp
Susp
S-fn
Susp
in Ers
Susp
S-fn
S-fn
Illegal State
in S-fn Busy
in Ers Susp
in Ers
S-fnSuspend
in Ers Susp
Busy S-fnSuspend
in Ers in Ers Susp
Susp
Susp
in Ers
Susp
IS in S-fn Susp in S-fn Suspend in Ers
S-fn Susp in Ers
Susp
Sub-function Susp
Susp
(Er
Ers Susp
Susp
N/A
bits
clear)
IS in Phase-1
Susp
Sub-Function Suspend in Erase Suspend
Ers
Susp
(Un-
lock
Ers
Ers
Susp
Blk
Ers
Susp
Blk
Ers
Susp
CR
Lock/RCR/ECR/Lock
EFA Block Setup in
Erase Suspend
Susp
Ers Susp (Error
[Botch])
Ers Susp (Lock Error [Botch])
(Error
[Botc
h])
N/A
N/A
N/A
N/A
Erase Suspend (Lock Error [Botch])
Ready (Error [Botch])
Lk-
Lock
Set
Block)
Down
BC
Busy
Ready (Error
[Botch])
Setup
Ready (Error [Botch])
IS in
BC
Blank
Blank Check Busy
Check
BC
Busy
BC Busy
IS in BC Busy
Blank Check Busy
BP Busy
IS in BC Busy
BC Busy
Busy
BC Busy
Ready
IS in Blank Check
Busy
BEFP
Load
Data
Setup
Ready (Error [Botch])
Ready (Error [Botch])
N/A
BEFP
BEFP Program and Verify Busy (if Block Address given matches address given on BEFP Setup command). Commands
treated as data. (7)
BEFP Busy
Ready
BEFP Busy
Ready
Datasheet
87
Apr 2009
Order Number: 320002-08
P30-65nm
Table 46: Output Next State Table for P30-65nm
(1)
Command Input to Chip and Resulting Output MUX Next State
Current Chip State
(90h,
98h)
(03h,
04h)
(FFh) (40h) (E8h) (EBh) (20h) (80h) (D0h) (B0) (70h) (50h)
(60h) (BCh) (C0h) (01h) (2Fh)
other
BEFPSetup,
BEFP Pgm & Verify Busy,
Erase Setup,
OTP Setup,
BP Setup, Load 1, Load 2
BP Setup, Load1, Load 2 - in
Erase Susp.
BP Confirm
EFI Sub-function Confirm
WordPgmSetup,
Word Pgm Setup in Erase
Susp,
Status Read
BP Confirm in Erase Suspend,
EFI S-fn Confirm in Ers Susp,
Blank Check Setup,
Blank Check Busy
Lock/RCR/ECR Setup,
Lock/RCR/ECR Setup in Erase
Susp
Status Read
EFI S-fn Setup, Ld 1, Ld 2
EFI S-fn Setup, Ld1, Ld 2 - in
Erase Susp.
Output MUX will not change
BP Busy
BP Busy in Erase Suspend
EFI Sub-function Busy
EFI Sub-fn Busy in Ers Susp
Word Program Busy,
Word Pgm Busy in Erase
Suspend,
OTP Busy
Erase Busy
Status
Read
Status
Read
Output MUX does
not Change
Status Read
Ready,
Word Pgm Suspend,
BP Suspend,
Phase-1 BP Suspend,
Erase Suspend,
BP Suspend in Erase Suspend
Phase-1 BP Susp in Ers Susp
Notes:
1.
2.
3.
4.
IS refers to Illegal State in the Next State Table.
“Illegal commands” include commands outside of the allowed command set.
The device defaults to "Read Array" on powerup.
If a “Read Array” is attempted when the device is busy, the result will be “garbage” data (we should not tell the user that
it will actually be Status Register data). The key point is that the output mux will be pointing to the “array”, but garbage
data will be output. “Read ID” and "Read Query" commands do the exact same thing in the device. The ID and Query data
are located at different locations in the address map.
The Clear Status command only clears the error bits in the status register if the device is not in the following modes:1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, BEFP modes) 2. Suspend states (Erase
Suspend, Pgm Suspend, Pgm Suspend In Erase Suspend).
5.
6.
7.
BEFP writes are only allowed when the status register bit #0 = 0 or else the data is ignored.
Confirm commands (Lock Block, Unlock Block, Lock-Down Block, Configuration Register and Blank Check) perform the
operation and then move to the Ready State.
8.
9.
Buffered programming will botch when a different block address (as compared to the address given on the first data write
cycle) is written during the BP Load1 and BP Load2 states.
All two cycle commands will be considered as a contiguous whole during device suspend states. Individual commands will
not be parsed separately. (I.e. If an erase set-up command is issued followed by a D0h command, the D0h command will
not resume the program operation. Issuing the erase set-up places the CUI in an “illegal state”. A subsequent command
will clear the “illegal state”, but the command will be otherwise ignored.
Datasheet
88
Apr 2009
Order Number: 320002-08
P30-65nm
Appendix B Conventions - Additional Information
B.1
Conventions
VCC:
Signal or voltage connection
V
:
Signal or voltage level
CC
0x:
h:
Hexadecimal number prefix
Hexadecimal number suffix
0b:
Binary number prefix
SR.4:
A[15:0]:
A5:
Denotes an individual register bit.
Denotes a group of similarly named signals, such as address or data bus.
Denotes one element of a signal group membership, such as an individual address bit.
Bit:
Binary unit
Byte:
Eight bits
Word:
Kbit:
Two bytes, or sixteen bits
1024 bits
KByte:
KWord:
Mbit:
1024 bytes
1024 words
1,048,576 bits
1,048,576 bytes
1,048,576 words
MByte:
MWord:
B.2
Acronyms
BEFP:
CFI:
MLC:
OTP:
PLR:
PR:
Buffer Enhanced Factory Programming
Common Flash Interface
Multi-Level Cell
One-Time Programmable
Protection Lock Register
Protection Register
RCR:
RFU:
SR:
Read Configuration Register
Reserved for Future Use
Status Register
WSM:
SRD
CUI
Write State Machine
Status Register Data
Command User Interface
Extended Function Interface
Password Access Data
EFI
PAD
Datasheet
89
Apr 2009
Order Number: 320002-08
P30-65nm
B.3
Nomenclature
A group of bits, bytes, or words within the flash memory array that erase
simultaneously. The P30-65nm has two block sizes: 32 KByte and 128 KByte.
Block :
An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Main block :
Parameter block :
An array block that may be used to store frequently changing data or small system
parameters that traditionally would be stored in EEPROM.
A device with its parameter blocks located at the highest physical address of its
memory map.
Top parameter device :
A device with its parameter blocks located at the lowest physical address of its
memory map.
Bottom parameter device :
Datasheet
90
Apr 2009
Order Number: 320002-08
P30-65nm
Appendix C Revision History
Revision Date
Revision
Description
May 2008
01
Initial Release
Add W28 AC specification;
Fix Buffered Program Command error in figure 38;
Update block locking state diagram;
Update Address range in Memory Map figure;
July 2008
02
Change LSB Address in ballout and pinout description from A0 back to A1 to match P30
130nm.
Update new trademark Axcell;
Remove 64M related contents.
Sep 2008
Nov 2008
03
04
Update Buffer program flowchart same as 130nm;
Minor wording modifications.
Remove 128M related contents;
Returne to StrataFlash trademark;
Nov 2008
Dec 2008
05
06
Update the buffer program for cross 512-Word boundary;
Correct A24 to A25 for virtual CE description in section 1.3;
Remove Numonyx Confidential.
Correct page buffer address bit to Four on Section 7.1, “Asynchronous Page-
Mode Read” on page 25.
Correct VHH to V
note 7.
on Table 23, “DC Current Characteristics” on page 50
PPH
Update QUAD+ package ballout H8 from OE# to F2-OE#. See Figure 8, “QUAD+
SCSP Ballout and Signals” on page 15.
Update QUAD+ Signal Description A[MAX:1] to A[MAX:0] and its Name and Function.
See Figure 6, “QUAD+ SCSP Signal Descriptions” on page 17.
Update Virtual Chip Enable Description from Adress 25 to the maximum address bit. See
Jan 2008
07
Section 1.3, “Virtual Chip Enable Description” on page 6.
Update TSOP Pinout P13 from VCC to RFU. See Section 6, “56-Lead TSOP
Pinout (256-Mbit)” on page 13.
Complete Section 9.2, “Blank Check” on page 32.
Minor wording modifications.
Add 512 Mbit (256/256) memory map in Figure 1, “P30-65nm Memory Map”
on page 7
Update QUAD+ signal description by changing A25 into RFU in Figure 8, “QUAD+
SCSP Ballout and Signals” on page 15
Apr 2009
08
Correct RCR.4, RCR.5, RCR.7 and RCR.9 definitions in Table 15, “Read
Configuration Register Description” on page 38
Correct A to A signal naming and remove invalid x8 information in Table 33,
0
1
“Example of CFI Structure Output of x16 Devices” on page 66
Datasheet
91
Apr 2009
Order Number: 320002-08
相关型号：
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