NSBMC096-16 [NSC]
NSBMC096-16/-25/-33 Burst Memory Controller; NSBMC096-16 / -25 / -33突发内存控制器
| 型号： | NSBMC096-16 |
| 厂家： | 
National Semiconductor |
| 描述： | NSBMC096-16/-25/-33 Burst Memory Controller |
| 文件： | 总18页 (文件大小：268K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 1993
NSBMC096-16/-25/-33 Burst Memory Controller
General Description
The NSBMC096 Burst Memory Controller is an integrated
The NSBMC096 has been designed to allow maximum flexi-
bility in its application. The full range of processor speeds is
supported for a wide range of DRAM speeds, sizes and or-
ganizations.
circuit which implements all aspects of DRAM control for
CA/CF
high performance systems using an i960
É
SuperScalar Embedded Processor. The NSBMC096 is func-
tionally equivalent to the V96BMCTM
.
No glue logic is required because the bus interface is cus-
tomized to the i960 CA/CF. System integration is further
enhanced by providing a 24-bit heartbeat timer and a bus
watch timer on-chip.
The extremely high instruction rate achieved by these proc-
essors place extraordinary demands on memory system de-
sign if maximum throughput is to be sustained and costs
minimized.
The NSBMC096 is packaged as a 132-pin PQFP with a foot-
print of only 1.3 square inches. It reduces design complexi-
ty, space requirements and is fully derated for loading, tem-
perature and voltage.
Static RAM offers a simple solution for high speed memory
systems. However, high cost and low density make this an
expensive and space consumptive choice.
Dynamic RAMs are an attractive alternative with higher den-
sity and low cost. Their drawbacks are, slower access time
and more complex control circuitry required to operate
them.
Features
Y
Interfaces directly to the i960 CA
Y
Integrated Page Cache Management
Y
The access time problem is solved if DRAMs are used in
page mode. In this mode, access times rival that of static
RAM. The control circuit problem is resolved by the
NSBMC096.
Manages Page Mode Dynamic Memory devices
Y
On-chip Memory Address Multiplexer/Drivers
Y
Supports DRAMs trom 256 kB to 64 MB
Y
Bit counter/timer
The function that the NSBMC096 performs is to optimally
translate the burst access protocol of the i960 CA/CF to the
page mode access protocol supported by dynamic RAMs.
Y
Non-interleaved or two way interleaved operation
Y
5-Bit Bus Watch Timer
Y
Software-configured operational parameters
The device manages one or two-way interleaved arrange-
ments of DRAMs such that during burst access, data can be
read, or written, at the rate of one word per system clock
cycle.
Y
High-Speed/Low Power CMOS technology
Block Diagram
TL/V/11805–1
This document contains information concerning a product that has been developed by National Semiconductor Corporation/V3 Corporation. This information
is intended to help in evaluating this product. National Semiconductor Corporation/V3 Corporation reserves the right to change and improve the specifications
of this product without notice.
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
NSBMC096TM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
i960É is a registered trademark of Intel Corporation.
V96BMCTM is a trademark of V3 Corporation.
C
1995 National Semiconductor Corporation
TL/V/11805
RRD-B30M115/Printed in U. S. A.
Logic and Connection Diagrams
TL/V/11805–2
TL/V/11805–3
Order Number NSBMC096VF
See Package Number VF132A
2
Pin Descriptions
TABLE I
Signal Name
Ý
Ý
Ý
Pin
Signal Name
Pin
Pin
Signal Name
1
A14
A15
A16
44
LEB
TXA
TXB
91
V
CC
2
3
4
5
6
45
46
47
48
53
92
93
94
95
96
V
SS
AB4
AB5
AB6
AB7
V
V
CC
CC
A17
A19
V
SS
AA0
7
8
A20
A18
A21
A24
A22
A23
54
55
56
57
58
59
AA1
AA2
AA3
97
98
V
CC
V
SS
9
99
AB8
AB9
10
11
12
V
CC
100
101
102
V
SS
AB10
AB11
AA4
13
14
15
19
20
21
A26
A25
A27
A31
A28
A29
60
61
62
63
64
65
AA5
AA6
AA7
103
104
105
106
107
108
V
CC
V
SS
CASB0
CASB1
CASB2
CASB3
V
CC
V
SS
AA8
22
23
24
25
26
27
A30
D/C
66
67
68
69
70
71
AA9
AA10
AA11
109
110
111
112
113
114
V
CC
V
SS
SUP
PCLK
INT
RASB0
RASB1
RASB2
RASB3
V
CC
V
SS
BERR
CASA0
28
29
30
31
32
33
W/R
BE0
72
73
74
75
76
77
CASA1
CASA2
CASA3
115
118
119
120
121
122
V
CC
MWEB
DEN
V
SS
BLAST
BE1
V
CC
RESET
A2
V
SS
V
SS
RASA0
A3
34
35
36
37
38
39
ADS
BE2
78
79
80
81
82
86
RASA1
RASA2
RASA3
123
124
125
126
127
128
A4
A5
A6
A7
A8
A9
BE3
BTERM
READY
ID0
V
CC
MWEA
V
SS
40
41
42
43
ID1
ID2
87
88
89
90
AB0
AB1
AB2
AB3
129
130
131
132
A10
A11
A12
A13
REFRESH
LEA
Note: In order for the switching characteristics of this device to be guaranteed, it is necessary to connect all of the power pins (V , V ) to the appropriate power
CC SS
levels. The use of low impedance wiring to the power pins is required. In systems using the i960 CA with its attendant high switching rates, multi-layer printed circuit
boards with buried power and ground planes are required.
3
Pin Descriptions (Continued)
i960 CA/CF INTERFACE
be wired together. All 3-State outputs are to be weakly
pulled up to V . In typical situations, a 10 kX resistor is
sufficient.
CC
The following pins are functionally equivalent to those on
the i960 CA/CF from which their names are taken. Like
named pins on the i960 CA/CF and the NSBMC960 are to
Pin
Description
Address Bus (Input): This system bus is a word address which determines the location at which an access is
A2–31
required.
ADS
Address Strobe (Input; Active Low): Indicates that a new access cycle is being started.
Data/*Code (Input): Signals whether an access is for data or instructions.
Burst Last (Input; Active Low): Indicates that the last cycle of a burst is in progress.
D/*C
BLAST
DEN
Data Enable (Input; Active Low): This input is monitored by the Bus Watch Timer to detect a bus access not
returning READY.
BTERM
READY
RESET
BE0–3
Burst Terminate (Output; 3-State; Active Low): This output is used to request termination of a burst in progress.
Used to disable burst writes.
Data Ready (Output; 3-State; Active Low): The READY output is used to signal that data on the processor bus is
valid for Read, or that data has been accepted for Write.
Reset (Input; Active Low): Assertion of this input sets the NSBMC960 to its initial state. Following initialization, the
NSBMC960 must be configured before any memory access is possible.
Byte Enable (Input; Active Low): These inputs are used to determine which byte(s) within the addressed word are to
be accessed.
W/*R
WRITE/*READ (Input): This input indicates the direction which data is to be transferred to/from on the data bus.
SUP
Supervisor (Input; Active Low): Indicates that the processor is operating in supervisor mode. Required for access to
configuration registers.
PCLK
BERR
System Clock (Input): Processor output clock required to operate and synchronize NSBMC960 internal functions.
Bus Error (Output; Active Low): When enabled, this signal is generated by the Bus Watch Circuit to prevent
processor lock-up on access to a region that is not responding.
INT
Interrupt (Output; 12 mA; Active Low): This signal is assented when the 24-bit counter reaches terminal count and
interrupt out is enabled. May be programmed for pulse or handshake operation.
ID0–2
Chip ID (Input): These inputs select the address offset of the NSBMC960 configuration registers. Each NSBMC960 in
a system must have a unique address for proper operation.
4
Pin Descriptions (Continued)
MEMORY INTERFACE
drivers in order to minimize propagation delay due to input
impedance and trace capacitance. External array drivers
are not required. The address and control signals, however,
should be externally terminated.
The NSBMC960 is designed to drive a memory array orga-
nized as 2 leaves each of 32 bits. The address and control
signals for the memory array are output through high current
Pin
Description
A(A,B)0–11
Multiplexed Address Bus (Output; 24 mA): These two buses transfer the multiplexed row and column
addresses to the memory array leaves A and B. When non-interleaved operation is selected, only address bus A
should be used.
RAS(A,B)0–3
Row Address Strobes (Output; 12 mA Active Low): These strobes indicate the presence of a valid row
address on busses A(A,B)0–11. These signals are to be connected one to each leaf of memory. Four banks of
interleaved memory may be attached to a NSBMC960.
CAS(A,B)0–3
MWE(A,B)
Column Address Strobe (Output; 12 mA, Active Low): These strobes latch a column address from A(A,B)0–
11. They are assigned one to each byte in a leaf.
Memory Write Enable (Output; 24 mA, Active Low): These are the DRAM write strobes. One is supplied for
each leaf to minimize signal loading.
REFRESH
Refresh in progress (Output; 12 mA, Active Low): This output gives notice that a refresh cycle is to be
executed. The timing leads refresh RAS by one cycle.
BUFFER CONTROLS
Multiple operating modes facilitate choice of buffer type,
and simple bus buffers (‘‘245’’s), bus latches (‘‘543’’s) and
bus registers (‘‘646’’s) are all supported.
Buffer control signals are provided to simplify the control of
the interface between the DRAM and i960 data busses.
Pin
Description
TX(A,B)
Data Bus Transmit A and B (Output; Active Low): These outputs are multi-function signals. The signal names,
e
as they appear on the logic symbol, are the default signal names (Mode
0). The purpose of these outputs is to
control buffer output enables during data read transactions and, in effect, control the multiplexing of data from
each memory leaf onto the i960 CA/CF data bus.
LE(A,B)
Data Bus Latch Enable A and B (Output; Active Low): These outputs are mode independent, however, the
timing of the signals change for different operational modes. They control transparent latches that hold data
transmiffed during a write transaction. In modes 0 and 1, the latch controls follow the timing of CAS for each
leaf, while in modes 2 and 3 the timing of LEA and LEB is shortened to (/2 clock.
5
Functional Description
PRODUCT OVERVIEW
allowed. If interleaved mode is selected, burst access is
zero-wait-state; if memory is non-interleaved, 1-wait-state
burst access results.
The NSBMC960 couples the i960 CA/CF interface to
DRAM access protocols, generates bus buffer and data
multiplexor controls and incorporates system and bus moni-
tor timing resources. These functional elements are shown
inFigure 1. A maximum of 8 controllers may be included in a
system, each managing up to 4 banks of memory.
The NSBMC960 allows for flexibility in the control of data
buffers to the memory array. Propagation delay is minimized
by providing these controls directly, and design flexibility
maximized by allowing the control strategy to be program-
mable. Buffers as diverse as 74FCT245, 74FCT543,
74FCT646, 74FCT853 and 74FCT861 may be used without
additional glue logic.
The NSBMC960 directly drives an array of fast page mode
DRAMs. This array may be organized as 1 or 2 leaves of
32 bits each. Standard memory sizes from 256 kbit to
64 Mbit are supported and 8-, 16-, and 32-bit access are
TL/V/11805–4
FIGURE 1. Functional Block Diagram
[
]
ed by the contents of the byte data field. Bits 1,0 are re-
served and must be ‘‘0’’. The base address is fixed at
0xff0f0000 while the BMC select field must match the value
CONFIGURATION AND CONTROL
The NSBMC960 contains 64 bits of configuration data that
controls it’s operational mode. The configuration is pro-
grammed by sending data on the address bus. Figure 2
shows the format of a configuration access. The byte select
field determines which byte of the 64-bit field will be updat-
[
]
programmed at the ID 2..0 pins. In order to protect against
accidental programming, the configuration registers can
only be modified when the processor is in supervisor mode.
TL/V/11805–5
FIGURE 2. Address Bus Fields Used to Access Configuration Data
6
Functional Description (Continued)
BLOCK ADDRESS FIELD
control bits. The block address, however, is constrained to
start on a boundary that is an integer multiple of the block
Once configured, a NSBMC096 responds to access re-
quests within the programmed block address range. The
programmed value sets the starting address of the block,
while the size of the block is determined by the DRAM size
c
size. For example, if 1 Mbit
1 DRAMs are used, the mem-
ory block size is 8 Mbytes and must start on an 8 Mbyte
boundary.
TL/V/11805–6
FIGURE 3. Configuration Register Control Fields
CYCLE EXTEND
violations during burst writes. If burst writes are disabled,
latching buffers are no longer required.
In order to maximize the choice of memory device speeds
that may be used for various system clock rates, the Row
Address Strobe (RAS) period for a basic access may be
programmed for either 3 or 4 clock cycles. When cleared to
‘‘0’’, configuration bit 20 indicates that 3 clock cycles (2 wait
states) are to be used (2-0-0-0 burst access), when set to
‘‘1’’, 4 are required (3 wait states for a basic access 3-0-1-0
for burst). Setting bit 20 to ‘‘1’’ also has the effect of in-
creasing the RAS pre-charge time by 1 clock cycle. Calcula-
tion of the number of cycles required per access type is
detailed in the NSBMC096 Application Guide.
ROW ADDRESS HOLD
Bit 18 of the configuration register controls the time at which
the memory address switches from row to column address.
This allows the designer to control the address hold time
relative to RAS so that the slowest memory can be used for
a range of clock speeds. Setting Bit 18 yields the maximum
row address hold time, clearing it shortens the row address
hold in favor of additional column address setup.
INTERLEAVE DISABLE
In cost sensitive applications, it is sometimes desirable for a
system to operate with a single bank of memory so as to
reduce the minimum memory required. In this case the inter-
leave mode bit is programmed to ‘‘1’’. If a second bank of
memory is added, this bit can be programmed to ‘‘0’’ to
enable interleave operation and peak performance. In non-
interleave mode a burst access is either 2-1-1-1 with Cycle
Extend disabled, or 3-2-2-2 with Extended Cycle. Non-inter-
leave operation uses only leaf A signals.
BURST WRITE DISABLE
It bit 19 of the configuration word is set to ‘‘1’’, burst write
cycles are disabled. Subsequently, when the NSBMC096
detects the start of a burst write access, it asserts the
BTERM signal to request that the processor terminate the
burst in progress and transfer the remaining data using a
series of simple cycles. This feature is included in order to
facilitate the implementation of systems without latching
buffers. Latching buffers are required to prevent data hold
7
Functional Description (Continued)
BUFFER CONTROL MODE FIELD
TABLE IV. Size Code Settings, DRAM
Density and Address Range Size
The transfer of Data from the memory sub-system to the
i960 bus occurs through buffers controlled by the
NSBMC096. Two of the signals (LEA, LEB) provide trans-
parent latch controls for use during write cycles. LEA and
LEB have variable timing but fixed interpretation. The other
two signals, TXA and TXB, change in both timing and func-
tion according to programmed mode. Table II presents
these signals using names that are based on the function
performed.
Memory
Memory
Max
Memory
Types
Size Code
Block Size
Banks
0 0 0
0 0 1
0 1 0
0 1 1
2 MB
8 MB
1
1
1
1
256k x 1
1 MB x 1
4 MB x 1
16 MB x 1
32 MB
128 MB
1 0 0
1 0 1
1 1 0
1 1 1
2 MB
8 MB
4*
4*
4*
4*
64k x 4
256k x 4
1 MB x 4
4 MB x 4
Signals containing TX are transmit controls for buffers that
have output enables (transmit from the memory system).
Buffers such as ’245s or ’646s, which have direction and
enable pins, are controlled by CE (chip enable) in modes 1
and 3. Signals ending with A or B are specific to one or the
other of the two leaves of memory controlled by the
NSBMC096. Signals without suffixes apply to both leaves.
The signal LeafB/*A, required in some configurations, indi-
cates which memory leaf will be selected on the next clock
cycle.
32 MB
128 MB
*Note that banks are sequentially addressed within a block.
REFRESH RATE FIELD
The system clock frequency is used to derive the period of
DRAM refresh cycles. The refresh rate is calculated as
(PCLK clock frequency) / (16 x (programmed value
a
1)).
If, for example, the system clock is 25 MHz and the pro-
grammed value is 24 (0x18), the NSBMC096 will execute
the 256 refresh cycles for a 256k DRAM in 4.096 ms.
TABLE II. Interpretation of the Buffer Control
Signals for Various Control Modes
Mode
Signal 1
Signal 2
The algorithm employed by the NSBMC096 guarantees the
time for complete device refresh, however, individual row
refresh may be delayed so as not to pre-empt bursts in
progress. Since the maximum burst is 6 clock cycles in
length, this delay in no way endangers data integrity. Ac-
cess to devices other than NSBMC096 controlled memory
are not delayed by refresh, access to memory while refresh
is in progress are completed once the refresh cycle is com-
plete.
0
1
2
3
TXA
CEA
TX
TXB
CEB
LeafB/*A
LeafB/*A
CE
Table III presents some of the possible configurations with
the corresponding mode settings. For a comprehensive dis-
cussion of the selection of a buffer strategy, refer to the
NSBMC096 Application Guide.
TIMER CONTROL FIELD
TABLE III. Possible NSBMC096
Memory/Buffer Configurations
The 24-bit timer is a counter which scales PCLK by a pro-
grammable amount and automatically reloads when termi-
nal count is reached. The contents of the timer cannot be
read directly, however, the counter will generate an interrupt
when terminal count is reached. The timer is disabled fol-
lowing a RESET and the Timer Reload value (Configuration
Bytes 4–6) must be programmed before the timer is en-
abled.
Buffer
Type
DRAM
Type
Write
Read
Buffer
Mode
Access
Access
74FCT245
74FCT245
74FCT646
74FCT543
Nibble
Bit
2-4-4-4*
2-4-4-4*
1-0-0-0
1-0-0-0
1-0-0-0
2-4-4-4*
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
2-0-0-0
Mode 3
Mode 1
Mode 3
Mode 0
Mode 2
Mode 2, 3
Nibble
Bit
The terminal count interrupt can be generated to comply
with either edge triggered or level sense interrupt control-
lers. Edge triggered mode generates a pulse that is low for
two cycles when terminal count is reached. In Level sense
mode, the output is asserted low when terminal count is
reached and the output remains low until the Acknowledge
Timer Interrupt op-code is written to configuration byte 0.
See the section on Operation Control for further detail con-
cerning timer interrupt control.
Am29C983 Bit
None Nibble
*These configurations have burst writes disabled.
DRAM SIZE FIELD
This three bit field, bits 12–14, selects the DRAM device
address size, and consequently, memory block size. Note
that the memory in both leaves of a bank are required to be
of the same size and organization for correct operation. Ta-
ble IV lists the size codes and the corresponding device
sizes.
BUS WATCH TIMER CONTROL FIELD
The NSBMC096 contains circuitry that monitors all bus ac-
cess requests regardless of the target address. Access
made to a region configured for external ready can hang the
processor if for some reason READY is not returned to ter-
minate the access. The NSBMC096 can detect such a con-
dition and if the bus watch feature is enabled, will return
READY and BERR.
8
Functional Description (Continued)
The bus monitor operates by monitoring the state of the
DEN signal. Should it be asserted for longer than the pro-
grammed Bus Time Out value in configuration register 7,
Ready is asserted if configuration bit 63 is set. If configura-
tion bit 62 is set, BERR is also asserted. The BERR signal
behaves much like the timer interrupt in that it can be pro-
grammed to produce a pulse or a level state.
must be zero for proper in-circuit operation. The second
field is the operation control field which is used to control
the state of the page cache, timer, interrupts and bus error
signal. The third field is the Iow two bits of the refresh rate.
The NSBMC096 has been designed such that if any of the
bits in the operation control field is written with a ‘‘1’’, ac-
cess to the other two fields is disabled and the previous
value is retained. If all bits in the operation control field are
‘‘0’’, the reserved and refresh rate fields are updated from
the current input.
e
If level state operation is selected, (configuration bit 61
1), BERR will only be deasserted when configuration regis-
ter 7 is accessed in a read cycle. If configuration bit 61 is
cleared to zero, a two cycle pulse is produced on time-out.
By providing both modes of operation, the BERR signal may
be connected directly to the processor, or to an external
WATCHDOGTM circuit.
Since the control register is accessed as a byte, automatic
masking of the non-control field bits simplifies programming
of the control parameters. AII parameters in this field may
be modified on-the-fly, and all functions are disabled by re-
set. The operational controls have been encoded such that
any access to the register will only modify one parameter.
OPERATION CONTROL FIELD
Byte 0 of the configuration register contains three fields.
The first field (from LSB) is reserved for test purposes and
Bit
Control
7
6
5
4
3
2
1
0
Function
D
X
D
X
0
0
0
1
0
0
0
0
D
X
D
X
Update Bits 0, 1, 6 and 7 with data D
Instruction Access Page Cache Disable
(Default)
X
X
X
X
X
X
X
X
X
X
0
0
0
1
1
1
1
1
0
0
1
0
1
0
1
0
1
1
0
0
X
X
X
X
X
X
X
X
X
X
Instruction Access Page Cache Enable
Data Access Page Cache Disable (Default)
Data Access Page Cache Enable
Acknowledge Timer Interrupt
Enable Timer Output for Level Sense
Interrupt
X
X
X
X
1
1
1
1
0
1
0
0
X
X
X
X
Disable All Timer Interrupts
Enable Timer Output for Edge Sense
Interrupt
on the behavior of the program being executed as related to
the ‘‘run-length’’ of data and instruction access, the proces-
sor internal cache utilization, and the locality of data and
instruction references. Since throughput is lowered by
cache misses, the page cache can be dynamically enabled/
disabled for instruction and/or data access. In this manner
the programmer can apply the mechanism judiciously in or-
der to maximize throughput.
PAGE CACHE MANAGEMENT
The Page Cache management implemented by the
NSBMC096 incorporates a mechanism whereby advantage
can be taken of the page access mode of DRAMs, not only
for burst access, but also for non-sequential data and in-
struction access. The mechanism relies on the fact that as
long as RAS is asserted, access to the selected row can be
gained by simply asserting a column address and the CAS
strobe. The resulting access is slower than a burst only by
the amount of time required to ensure that the desired ad-
dress is in the same row as was previously selected.
For systems in which Instruction and data spaces are con-
trolled by independent NSBMC096s, the page cache man-
agement can be used to greater effect as data and instruc-
tion ‘‘run length’’ ceases to be a factor in determining per-
formance. In this type of configuration cache efficiency is
simply a function of locality of reference and a control strat-
egy for the page cache mechanism is much simpler to de-
rive and implement. PCache management is independently
controlled for instruction and data access. A recommended
starting strategy for improving performance of mixed in-
struction/data systems is to rely on the burst mechanism
and the internal cache for instruction fetching, and enable
PCache for Data access only. This general rule of thumb
can be improved on, once program behavior is bench-
marked.
The benefits of this type of access are obvious, however,
there can be drawbacks. If the required address does not
reside in the same page as that selected, the currently se-
lected row must be released and the new row selected be-
fore the access can proceed. The process of de-selecting a
row and selecting a new one requires that the RAS pre-
charge time be allowed to expire before the selection of a
new row can begin. This pre-charge time can require up to
two additional cycles over a standard access startup.
The efficiency of this type of cache (PCache) is related to a
large extent on the locality of reference of the datum being
accessed. For systems that have mixed Instruction and
Data memory systems, PCache efficiency is very dependent
9
Application Example
System Clock:
Refresh Rate:
Memory Size:
Buffer Mode:
25 MHz
Cycle Extend:
Disabled (3 clock RAS derived from
of NSBMC096, RAS access time
of DRAM, buffer delay of 74FCT245
and setup time of the processor’s data
inputs)
t
c
RSHL
16 ms per row (0
18)
1)
CEA, Signal
e
1 MB x 1 (Size
e
e
CEB
Signal 1
(Mode 1)
2
Burst Write:
Disabled
Interleave:
Enabled
Base Address:
8 MB (0b000000000100)
Row Address Hold: (/2 clock cycle
(Row Address Hold
e
0)
Required Configuration for startup
0000 0000 1000 1000 1001 0110 0000 0000 (0x00889600)
Configuration Setup
0xFF0F0000 (0xFF0F0000, 0);
e
0 */
/* Config. bits 7..0
a
a
m
e
0xFF0F0658 (0xFF0F0400
0xFF0F0A20 (0xFF0F0800
(0x96 2), 0);
/* Config. bits 15..8
/* Config. bits 23..16
/* Config. bits 31..24
0 */
0 */
0 */
m
(0x88 2), 0);
e
e
0xFF0F0C00 (0xFF0F0C00, 0);
The ease with which the NSBMC096 may be integrated into
a system design is illustrated in the diagram in Figure 4. The
system shown supports an i960 CA/CF with between 2 and
128 MB of memory, depending on the devices selected,
managed by a single NSBMC096. This specific example ac-
commodates 1 MB x 1, 4 MB x 1 or 16 MB x 1 devices.
ate inputs of the processor and require only a small pull up
resistor to keep them de-asserted when in the high imped-
ance state.
If multiple processor peripherals are connected to READY
or BTERM, 3-state drivers should be used in such a manner
that the signals are actively de-asserted prior to the driver
being placed in its’ high impedance state. If this rule is fol-
lowed, a simple ‘‘wire or’’ can be used. Alternately, all
sources of READY or BTERM can be combined using multi-
ple input gates and the processor signals driven by the out-
puts.
Connection of the NSBMC096 to the i960 CA/CF processor
is accomplished simply by wiring together pins with the
same names. The only exceptions are READY and BTERM.
If the NSBMC096 is the only device that generates these
two signals, they can be connected directly to the appropri-
TL/V/11805–7
FIGURE 4. Possible System Interconnection using V96BMC
(Mode 1 where TXA is used as CEA and TXB as CEB)
10
Timing Parameters
INTERFACE TIMING
depending on whether Cycle Extend is enabled. If multiple
access cycles are requested back to back then the BMC will
pause for a minimum of 2 clocks between RAS cycles to
insure that the RAS pre-charge time is met. This will result in
5 or 6 clocks between successive simple cycles.
The NSBMC096 interface to the i960 CA/CF has been de-
signed for direct interconnect. It is not necessary to place
other Iogic devices between the processor and the
NSBMC096, nor is their use encouraged. The introduction
of intermediate address or control signal buffers can result
in skews or delays that will require the system clock fre-
quency to be derated for operation under worst case condi-
tions. The timing diagrams presented in this section assume
that all signals between the processor and the NSBMC096
are un-buffered.
Figure 6 shows the timing relationship between the system
clock, processor control signals and NSBMC096 outputs.
AIl NSBMC096 outputs are derived synchronously with the
exception of t
(processor address to row address de-
ARA
lay). Two simple access cycles are shown in the diagram.
The first is a read cycle that assumes that the NSBMC096
was idle prior to the start of the cycle, the second is backed
onto the first to show the effect of RAS pre-charge imposed
by NSBMC096. If Cycle Extend is enabled, a wait state will
be inserted after cycles T3 and T8.
REFRESH TIMING
Figure 5 details the timing of the RAS only refresh per-
formed by the memory controller when there is a competing
request from a bus master. A competing request is defined
as any request that occurs between T0 and T5. For any
request in this range, the timing is exactly as shown. As
illustrated, the diagram represents the timing that results
when Cycle Extend is disabled. If Cycle Extend is enabled,
an additional cycle is inserted at T3 and T8.
BURST ACCESS TIMING
When a burst access is requested by the processor, the
NSBMC096 generates the sequence in Figure 7. If the burst
is for 2 words (load double for example), the processor gen-
erates *BLAST in T5 and the sequence is shortened appro-
priately. The first access of the burst sequence begins in the
same manner as a simple access. Consequently the timing
parameters from Figure 6 may be applied in Figure 7.
SIMPLE ACCESS TIMING
The NSBMC096 can return data to the processor in only 3
or 4 clock cycles for a basic access (2 or 3 wait states)
TL/V/11805–8
FIGURE 5. Refresh Timing
11
Timing Parameters (Continued)
TL/V/11805–9
FIGURE 6. Basic Access Timing
TL/V/11805–10
FIGURE 7. Burst Access Timing
12
Timing Parameters (Continued)
TL/V/11805–11
FIGURE 8. Burst Access w/t PCache Hit
Figures 8 and 9 show the sequence of events that can oc-
cur when PCache is enabled. The sequence in Figure 8
shows two back-to-back bursts in the same page. This type
of sequence yields the highest data transfer rate achievable
with DRAM. Figure 9 shows the worst case scenario. This
example shows two back-to-back simple access to different
rows with PCache is enabled.
TL/V/11805–12
FIGURE 9. Simple Access w/t PCache Miss
13
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
)
CC
4.5V to 5.5V
O
Ambient Temperature Range (
Plastic Package
Ceramic Package
)
A
b
0.3V to V
a
0.3V to 7V
Supply Voltage (V
Input Voltage (V
)
b
a
CC
)
0 C to 70 C
§
§
§
b
a
0.3V
b
a
55 C to 85 C
IN
CC
§
g
50 mA
D.C. Input Current (I
)
IN
Storage Temperature (
O
b
a
65 C to 150 C
§
)
§
STG
All Voltages References to Ground
DC Electrical Characteristics
Symbol
Description
Conditions
Min
Max
Units
V
e
e
V
V
Low Level Input Voltage
High Level Input Voltage
Low Level Input Current
High Level Input Current
Low Level Output Voltage
V
V
V
V
V
4.75V
5.25V
1.4
IL
CC
CC
IN
3.7
V
IH
e
e
b
10
I
I
V
V
V
, V
SS CC
5.25V
mA
mA
IL
IH
e
e
e
5.25V
10
IN
CC
or V
IL
V
V
I
OL
IN
IH
0.4
V
e
I
24 mA
OL
e
e
High Level Output Voltage
V
IN
V or V
IL
24 mA
OH
IH
IH
IH
3.7
V
I
OL
e
e
Low Level TRI-STATE
V
V
V or V
IL
É
OZL
IN
b
20
mA
mA
mA
Output Current
V
SS
O
e
e
I
I
Low Level TRI-STATE
Output Current
V
V
V or V
IL
5.25V
OZH
IN
20
O
Maximum Supply Current
Continuous Burst Access
Continuous Simple Access
100
30
CC(Max)
C
C
Input Capacitance
Output Capacitance
20
20
pF
pF
IN
OUT
14
k
k
70 C.)
e
g
5.0V 5%, 0 C
AC Timing Parameters (Unless otherwise stated V
T
A
§
§
CC
16 MHz
25 MHz
33 MHz
Symbol
Description
Units
Min
Max
3
Min
Max
3
Min
Max
1.
2.
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Address Strobe Setup Time
14
12
12
12
9
9
9
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ADSU
ADH
SU
Address Strobe Hold Time
3
3.
Synchronous Input Setup
14
14
4.
Synchronous Input Hold
3
3
3
H
5.
BLAST Input Setup
BLSU
BLH
6.
BLAST Input Hold
3
3
3
7.
READY 3-state to Valid Delay Relative to *PCLK
READY Synchronous Assertion Delay
READY Synchronous De-assertion Delay
READY Valid to 3-state Delay Relative to *PCLK
29
26
25
27
23
40
38
24
21
20
22
19
33
31
19
17
16
17
15
26
25
RZH
RHL
8.
9.
RLH
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
29.
30.
31.
32.
33.
RHZ
ARA
RAH
CAV
Address Input to Row Address Output Delay (Note 1)
*PCLK or PCLK to Row Address Hold
*PCLK or PCLK to Column Address Valid (Note 1)
PCLK to Column Address Hold
4
4
4
CAH
DRAH
RSHL
RSLH
CHL
DRAM Row Address Hold (Note 2)
t
t
t
M-3
M-4
M-4
PCLK to RAS Asserted Delay (Note 1)
29
26
23
20
26
23
26
24
21
19
16
21
19
21
19
17
15
13
17
15
17
PCLK to RAS De-asserted Delay (Note 1)
PCLK to CAS Asserted Delay (Note 1)
PCLK to CAS De-asserted Delay (Note 1)
PCLK to Buffer Control Asserted Delay (Note 1)
PCLK to Buffer Control De-asserted Delay (Note 1)
PCLK to Bank Select Valid Time (Note 1)
PCLK to Bank Select Hold Time (Note 1)
*PCLK to Write Enable Asserted Delay (Note 1)
PCLK to Write Enable De-asserted Delay (Note 1)
CLH
BHL
4
4
4
4
4
4
BLH
BSV
BSH
WEHL
WELH
BCAH
BCAV
LEHL
LELH
RFA
31
25
20
*PCLK to Column Address Hold Time (Burst) (Note 1)
*PCLK to Column Address Valid Delay (Burst) (Note 1)
*PCLK to Latch Enable Assertion
5
5
4
29
23
20
38
23
19
16
31
19
15
13
25
PCLK to Latch Enable De-assertion
PCLK to Row Address Valid (Refresh)
PCLK to Row Address Hold (Refresh)
5
5
4
RFH
RFHL
RFLH
REFRESH Synchronous Assertion Delay
REFRESH Synchronous De-assertion Delay
20
20
16
16
13
13
*Signal output delays are measured relative to PCLK (except as indicated) using a 50 pF load.
Note 1: Derate the given delays by 0.006 ns per pF of load in excess of 50 pF.
e
e
e
e
e
for configuration bit 18 1. Timing for Rev AB
Note 2: t
PCLK High duration when configuration bit 18
0. t
PCLK cycle time
1/
M
M
(PCLK frequency)
silicon.
15
Errata for NSBMC096
The document defines all known errata related to the opera-
tion of the NSBMC096 Memory Controller.
Ý
2
ERRATUM
When the NSBMC096 is programmed for extended timing
mode operation, back to back memory read cycles will fail.
Ý
ERRATUM
1
Pulse mode interrupts from the NSBMC096 are two cycles
long. The current rev. of the i960CA/CF requires a minimum
interrupt pulse width of three clock cycles.
RECOMMENDED FIX
Program the i960CA/CF memory region for the NSBMC096
to insert one wait state following each memory access (i.e.,
e
Set N
1).
XDA
RECOMMENDED FIX
Program the NSBMC096 for level mode interrupts.
Ordering Code Information
NS BMC 096 VF 33
National Semiconductor
Frequency
16 MHz
25 MHz
33 MHz
Mode
Burst Mode Controller
Processor
Intel i960
Packaging
VF 132-Lead PQFP
16
17
Physical Dimensions inches (millimeters)
132-Pin Plastic Quad Flatpak (PQFP)
Order Number NSBMC096VF
NS Package Number VF132A
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