NM24C05M8 [NSC]
IC 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, SOP-8, Programmable ROM;
| 型号： | NM24C05M8 |
| 厂家： | 
National Semiconductor |
| 描述： | IC 512 X 8 I2C/2-WIRE SERIAL EEPROM, PDSO8, PLASTIC, SOP-8, Programmable ROM 可编程只读存储器 电动程控只读存储器 电可擦编程只读存储器 时钟 光电二极管 内存集成电路 |
| 文件： | 总12页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1993
NM24C03/C05/C09/C17
2K-/4K-/8K-/16K-Bit Serial EEPROM
2
with Write Protect (I C Synchronous 2-Wire Bus)
General Description
The NM24C03/C05/C09/C17 devices are 2048/4096/
8192/16,834 bits, respectively, of CMOS non-volatile elec-
trically erasable memory. These devices conform to all
Features
Y
Hardwire write protect for upper block
Y
Low Power CMOS
Ð 2 mA active current typical
2
specifications in the I C 2-wire protocol, and are designed
Ð 60 mA standby current typical
2
2-wire I C serial interface
Y
Y
Y
to minimize device pin count and simplify PC board layout
requirements.
Ð Provides bidirectional data transfer protocol
Sixteen byte page write mode
Ð Minimizes total write time per byte
Self timed write cycle
Ð Typical write cycle time of 5 ms
The upper half of the memory can be disabled (Write Pro-
tected) by connecting the WP pin to V . This section of
CC
memory then becomes unalterable unless WP is switched
to V
.
SS
6
Endurance: 10 data changes
Y
Y
Y
This communication protocol uses CLOCK (SCL) and DATA
I/O (SDA) lines to synchronously clock data between the
master (for example a microprocessor) and the slave EEP-
ROM device(s). In addition, this bus structure allows for a
maximum of 16K of EEPROM memory. This is supported by
the NSC family in 2K, 4K, 8K and 16K devices, allowing the
user to configure the memory as the application requires
with any combination of EEPROMs (not to exceed 16K).
Data retention greater than 40 years
Packages available: 8 pin mini-DIP or 14 pin SO
package
National EEPROMs are designed and tested for applica-
tions requiring high endurance, high reliability, and low pow-
er consumption.
Functional Diagram
TL/D/11100–1
C
1995 National Semiconductor Corporation
TL/D/11100
RRD-B30M65/Printed in U. S. A.
Connection Diagrams
Dual-In-Line Package (N) and (M8)
Pin Names
SO Package (M)
A0, A1, A2 Device Address Inputs
V
SS
Ground
SDA
SCL
Data I/O
Clock Input
a
V
CC
5V
TL/D/11100–2
WP
NC
Write Protect
Top View
No Connection
See NS Package Number
N08E (N) or M08A (M8)
TL/D/11100–3
Top View
See NS Package Number M14B
Ordering Information
a
Commercial Temperature Range (0 C to 70 C)
§
§
Order Number
NM24C03N/NM24C05N/NM24C09N/NM24C17N
NM24C03M8/NM24C05M8/NM24C09M/NM24C17M
b
a
Extended Temperature Range ( 40 C to 85 C)
§
§
Order Number
NM24C03EN/NM24C05EN/NM24C09EN/NM24C17EN
NM24C03EM8/NM24C05EM8/NM24C09EM/NM24C17EM
b
a
Military Temperature Range ( 55 C to 125 C)
§
§
Order Number
NM24C03MN/NM24C05MN/NM24C09MN/NM24C17MN
NM24C03MM8/NM24C05MM8/NM24C09MM/NM24C17MM
Note: For 14-lead SO package availability for the NM24C03/05 devices, check with your NSC sales representative.
2
Absolute Maximum Ratings
Operating Conditions
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Ambient Operating Temperature
NM24C03/C05/C09/C17
NM24C03E/C05E/C09E/C17E
NM24C03M/C05M/C09M/C17M
(Mil. Temp.)
a
0 C to 70 C
§
§
§
b
a
40 C to 85 C
§
b
a
65 C to 150 C
Ambient Storage Temperature
§
§
b
a
55 C to 125 C
§
§
4.5V to 5.5V
All Input or Output Voltages
with Respect to Ground
Positive Power Supply (V
)
CC
a
b
6.5V to 0.3V
Lead Temperature
(Soldering, 10 sec.)
a
300 C
§
2000V
ESD Rating
e
g
5V 10% (unless otherwise specified)
DC and AC Electrical Characteristics V
CC
Limits
Symbol
Parameter
Test Conditions
Units
Typ.
Min
(Note 1)
Max
e
SCL
I
I
I
I
Active Power Supply Current
Standby Current
f
100 kHz
2.0
60
3.0
100
10
mA
mA
mA
mA
V
CCA
SB
LI
e
e
V
V
V
GND or V
GND to V
IN
IN
CC
Input Leakage Current
Output Leakage Current
Input Low Voltage
0.1
0.1
CC
e
GND to V
CC
10
LO
OUT
b
V
V
V
0.3
V
x 0.3
IL
CC
a
Input High Voltage
V
x 0.7
V
0.5
V
V
IH
OL
CC
CC
e
Output Low Voltage
I
3 mA
0.4
OL
e
e
e
5V
CC
Capacitance T
25 C, f
§
1.0 MHz, V
A
Symbol
Test
Input/Output Capacitance (SDA)
Input Capacitance (A , A , A , SCL, WP)
Conditions
Max
8
Units
e
V
I/O
C
C
(Note 2)
0V
pF
pF
I/O
e
V
IN
(Note 2)
0V
6
IN
0
1
2
A.C. Conditions of Test
Input Pulse Levels
V
CC
x 0.1 to V x 0.9
CC
Input Rise and
Fall Times
10 ns
Input and Output
Timing Levels
V
x 0.5
CC
Output Load
1 TTL Gate and
e
C
100 pF
L
e
Note 1: Typical values are for T
25 C and nominal supply voltage (5V).
§
Note 2: This parameter is periodically sampled and not 100% tested.
A
3
Read and Write Cycle Limits
Symbol
Parameter
Min
Max
Units
f
SCL Clock Frequency
100
kHz
SCL
T
Noise Suppression Time
I
100
3.5
ns
Constant at SCL, SDA Inputs
t
t
SCL Low to SDA Data Out Valid
0.3
4.7
ms
AA
Time the Bus Must Be Free
before a New Transmission
Can Start
BUF
ms
t
t
t
t
Start Condition Hold Time
Clock Low Period
4.0
4.7
4.0
ms
ms
ms
ms
HD:STA
LOW
Clock High Period
HIGH
Start Condition Setup Time
SU:STA
4.7
(for a Repeated Start Condition)
t
t
t
t
t
t
t
Data in Hold Time
0
ms
ns
ms
ns
ms
ns
ms
HD:DAT
SU:DAT
R
Data in Setup Time
250
SDA and SCL Rise Time
SDA and SCL Fall Time
Stop Condition Setup Time
Data Out Hold Time
Write Cycle Time
1
300
F
4.7
SU:STO
DH
300
(Note 3)
10
WR
Note 3: The write cycle time (t ) is the time from a valid stop condition of a write sequence to the end ot the internal erase/program cycle. During the write cycle,
WR
the NM24Cxx bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and the device does not respond to its slave
address.
Bus Timing
TL/D/11100–4
4
2
BACKGROUND INFORMATION (I C Bus)
2
As mentioned, the I C bus allows synchronous bidirectional
DEFINITIONS
communication between Transmitter/Receiver using the
SCL (clock) and SDA (Data I/O) lines. All communication
must be started with a valid START condition, concluded
with a STOP condition and acknowledged by the Receiver
with an ACKNOWLEDGE condition.
WORD
PAGE
8 bits (byte) of data.
16 sequential addresses (one byte
each) that may be programmed
during a ‘‘Page Write’’ programming
cycle.
2
In additon, since the I C bus is designed to support other
devices such as RAM, EPROM, etc., the device type identifi-
er string must follow the START condition. For EEPROMs,
this 4-bit string is 1010.
PAGE BLOCK
MASTER
2,048 (2K) bits organized into 16
pages of addressable memory.
e
(8 bits) x (16 bytes) x (16 pages)
2,048 bits
2
2
As shown below, the EEPROMs on the I C bus may be
configured in any manner required, providing the total mem-
ory addressed does not exceed 16K (16,834 bits). EEPROM
memory addressing is controlled by two methods:
Any I C device CONTROLLING the
transfer of data (such as a
microprocessor).
Hardware configuring the A0, A1 and A2 pins (Device
Address pins) with pull-up or pull-down resistors. ALL
#
SLAVE
Device being controlled (EEPROMs
are always considered Slaves).
Device currently SENDING data on
the bus (may be either a Master OR
Slave).
UNUSED PINS MUST BE GROUNDED (tied to V ).
SS
TRANSMITTER
Software addressing the required PAGE BLOCK within
the device memory array (as sent in the Slave Address
string)
#
RECEIVER
Device currently receiving data on
the bus (Master or Slave).
Addressing an EEPROM memory location involves sending
a command string with the following information:
[
DRESS - BYTE ADDRESS
] [
] [
DEVICE TYPE - DEVICE ADDRESS - PAGE BLOCK AD-
] [
]
Example of 16k (Maximum Size) of Memory on 2-Wire Bus
TL/D/11100–20
Note:
2
The SDA pull-up resistor is required due to the open-drain/open-collector output of I C bus devices.
The SCL pull-up resistor is recommended because of the normal SCL line inactive ‘‘high’’ state.
It is recommended that the total line capacitance be less than 400 pF.
Specific timing and addressing considerations are described in greater detail in the following sections.
Address Pins
Number of
Device
Memory Size
Page Blocks
A0
A1
DA
DA
A2
DA
DA
DA
NM24C03
NM24C05
DA
2048 Bits
4096 Bits
8192 Bits
16,384 Bits
1
2
4
8
V
SS
SS
SS
NM24C09
V
V
V
SS
SS
NM24C17
V
V
SS
DA: Device Address
5
Pin Descriptions
SERIAL CLOCK (SCL)
If tied to V , normal memory operation is enabled, READ/
SS
WRITE over the entire memory is possible.
The SCL input is used to clock all data into and out of the
device.
This feature allows the user to assign the upper half of the
memory as ROM which can be protected against accidental
programming. When write is disabled, slave address and
word address will be acknowledged but data will not be ac-
knowledged.
SERIAL DATA (SDA)
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector out-
puts.
Device Operation
DEVICE ADDRESS INPUTS (A0, A1, A2)
The NM24C03/C05/C09/C17 supports a bidirectional bus
oriented protocol. The protocol defines any device that
sends data onto the bus as a transmitter and the receiving
device as the receiver. The device controlling the transfer is
the master and the device that is controlled is the slave. The
master will always initiate data transfers and provide the
clock for both transmit and receive operations. Therefore,
the NM24Cxx is considered a slave in all applications.
Device address pins A0, A1 and A2 are connected to V
CC
or V
SS
to configure the EEPROM address. The following
table (Table A) shows the active pins across the NM24Cxx
device family.
TABLE A
Device
A0 A1 A2
Effects of Addresses
CLOCK AND DATA CONVENTIONS
3
2
2
2
1
2
0
2
e
e
e
e
c
e
e
e
e
NM24C03 ADR ADR ADR
8
4
2
1
(8) ( 2K)
16K
16K
16K
16K
Data states on the SDA line can change only during SCL
LOW. SDA state changes during SCL HIGH are reserved for
indicating start and stop conditions. Refer to Figures 1 and
2.
c
(4) ( 4K)
NM24C05
NM24C09
NM24C17
X
X
X
ADR ADR
c
(2) ( 8K)
X
X
ADR
X
c
(1) (16K)
ADR: Denotes an active pin used for device addressing
START CONDITION
X: Not used for addressing (must be tied to Ground/V
)
SS
All commands are preceded by the start condition, which is
a HIGH to LOW transition of SDA when SCL is HIGH. The
NM24Cxx continuously monitors the SDA and SCL lines for
the start condition and will not respond to any command
until this condition has been met.
WP WRITE PROTECTION
If tied to V , PROGRAM operations onto the upper half of
CC
the memory will not be executed. READ operations are pos-
sible.
Write Cycle Timing
TL/D/11100–5
TL/D/11100–6
FIGURE 1. Data Validity
TL/D/11100–7
FIGURE 2. Definition of Start and Stop
6
TL/D/11100–8
FIGURE 3. Acknowledge Response from Receiver
STOP CONDITION
All communications are terminated by a stop condition,
which is a LOW to HIGH transition of SDA when SCL is
HIGH. The stop condition is also used by the NM24Cxx to
place the device in the standby power mode.
NM24C03
NM24C05
TL/D/11100–17
ACKNOWLEDGE
Acknowledge is a software convention used to indicate suc-
cessful data transfers. The transmitting device, either mas-
ter or slave, will release the bus after transmitting eight bits.
During the ninth clock cycle the receiver will pull the SDA
line LOW to acknowledge that it received the eight bits of
data. Refer to Figure 3.
The NM24Cxx device will always respond with an acknowl-
edge after recognition of a start condition and its slave ad-
dress. If both the device and a write operation have been
selected, the NM24Cxx will respond with an acknowledge
after the receipt of each subsequent eight bit word.
TL/D/11100–9
TL/D/11100–18
TL/D/11100–19
In the read mode the NM24Cxx slave will transmit eight bits
of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is detected and no stop
condition is generated by the master, the slave will continue
to transmit data. If an acknowledge is not detected, the
slave will terminate further data transmissions and await the
stop condition to return to the standby power mode.
NM24C09
Device Addressing
NM24C17
Following a start condition the master must output the ad-
dress of the slave it is accessing. The most significant four
bits of the slave address are those of the device type identi-
fier, (see Figure 4). This is fixed as 1010 for all four devices:
NM24C03, NM24C05, NM24C09 and NM24C17.
FIGURE 4. Slave Addresses
7
Device Addressing (Continued)
Refer to the following table for Slave Address string details:
Number of
Device
A0
A1
A2
Page Block Addresses
Page Blocks
NM24C03
NM24C05
NM24C09
NM24C17
A
P
P
P
A
A
P
P
A
A
A
P
1
2
4
(2K)
(4K)
(None)
1
0
(8K)
00 01
10
11
1
(16K)
000 001 010 011 . . . 111
A: Refers to a hardware configured Device Address pin
P: Refers to an internal PAGE BLOCK memory segment
2
All I C EEPROMs use an internal protocol that defines a
PAGE BLOCK size of 2K bits (for Word addresses 0000
through 1111). Therefore, address bits A0, A1 or A2 (if des-
ignated ‘‘P’’) are used to access a PAGE BLOCK in con-
junction with the Word address used to access any individu-
al data byte (Word).
Write Operations
BYTE WRITE
For a write operation a second address field is required
which is a word address that is comprised of eight bits and
provides access to any one of the 256 words in the selected
page of memory. Upon receipt of the word address the
NM24Cxx responds with an acknowledge and waits for the
next eight bits of data, again, responding with an acknowl-
edge. The master then terminates the transfer by generat-
ing a stop condition, at which time the NM24Cxx begins the
internal write cycle to the nonvolatile memory. While the
internal write cycle is in progress the NM24Cxx inputs are
disabled, and the device will not respond to any requests
from the master. Refer toFigure 5 for the address, acknowl-
edge and data transfer sequence.
The last bit of the slave address defines whether a write or
read condition is requested by the master. A ‘‘1’’ indicates
that a read operation is to be executed and a ‘‘0’’ initiates
the write mode.
A simple review: After the NM24C03/C05/C09/C17 recog-
2
nizes the start condition, the devices interfaced to the I C
bus wait for a slave address to be transmitted over the SDA
line. If the transmitted slave address matches an address of
one of the devices, the designated slave pulls the line LOW
with an acknowledge signal and awaits further transmis-
sions.
TL/D/11100–10
FIGURE 5. Byte Write
8
Write Operations (Continued)
Read Operations
Read operations are initiated in the same manner as write
operations, with the exception that the R/W bit of the slave
address is set to a one. There are three basic read opera-
tions: current address read, random read and sequential
read.
PAGE WRITE
The NM24Cxx is capable of a sixteen byte page write opera-
tion. It is initiated in the same manner as the byte write
operation; but instead of terminating the write cycle after the
first data word is tranferred, the master can transmit up to
fifteen more words. After the receipt of each word, the
NM24Cxx will respond with an acknowledge.
CURRENT ADDRESS READ
Internally the NM24Cxx contains an address counter that
maintains the address of the last word accessed, incre-
mented by one. Therefore, if the last access (either a read
or write) was to address n, the next read operation would
After the receipt of each word, the internal address counter
increments to the next address and the next SDA data is
accepted. If the master should transmit more than sixteen
words prior to generating the stop condition, the address
counter will ‘‘roll over’’ and the previously written data will
be overwritten. As with the byte write operation, all inputs
are disabled until completion of the internal write cycle. Re-
fer toFigure 6 for the address, acknowledge and data trans-
fer sequence.
a
access data from address n
1. Upon receipt of the slave
address with R/W set to one, the NM24Cxx issues an ac-
knowledge and transmits the eight bit word. The master will
not acknowledge the transfer but does generate a stop con-
dition, and therefore the NM24Cxx discontinues tranmis-
sion. Refer to Figure 7 for the sequence of address, ac-
knowledge and data transfer.
ACKNOWLEDGE POLLING
RANDOM READ
Once the stop condition is issued to indicate the end of the
host’s write operation, the NM24Cxx initiates the internal
write cycle. ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the NM24Cxx is still busy
with the write operation, no ACK will be returned. If the
NM24Cxx has completed the write operation, an ACK will be
returned and the host can then proceed with the next read
or write operation.
Random read operations allow the master to access any
memory location in a random manner. Prior to issuing the
slave address with the R/W bit set to one, the master must
first perform a ‘‘dummy’’ write operation. The master issues
a start condition, slave address and then the word address it
is to read. After the word address acknowledge, the master
immediately reissues the start condition and the slave ad-
dress with the R/W bit set to one. This will be followed by
an acknowledge from the NM24Cxx and then by the eight
bit word. The master will not acknowledge the transfer but
does generate the stop condition, and therefore the
NM24Cxx discontinues transmission. Refer to Figure 8 for
the address, acknowledge and data transfer sequence.
WRITE PROTECTION
Programming of the upper half of the memory will not take
place if the WP pin of the NM24Cxx is connected to V
CC
a
(
5V). The NM24Cxx will accept slave and word address-
es; but if the memory accessed is write protected by the WP
pin, the NM24Cxx will not generate an acknowledge after
the first byte of data has been received, and thus the pro-
gram cycle will not be started when the stop condition is
asserted.
TL/D/11100–11
FIGURE 6. Page Write
TL/D/11100–12
FIGURE 7. Current Address Read
9
Read Operations (Continued)
SEQUENTIAL READ
The data output is sequential, with the data from address n
a
followed by the data from n
1. The address counter for
Sequential reads can be initiated as either a current address
read or random access read. The first word is transmitted in
the same manner as the other read modes; however, the
master now responds with an acknowledge, indicating it re-
quires additional data. The NM24Cxx continues to output
data for each acknowledge received. The read operation is
terminated by the master not responding with an acknowl-
edge or by generating a stop condition.
read operations increments all word address bits, allowing
the entire memory contents to be serially read during one
operation. After the entire memory has been read, the coun-
ter ‘‘rolls over’’ and the NM24Cxx continues to output data
for each acknowledge received. Refer to Figure 9 for the
address, acknowledge and data transfer sequence.
TL/D/11100–13
FIGURE 8. Random Read
TL/D/11100–14
FIGURE 9. Sequential Read
TL/D/11100–15
FIGURE 10. Typical System Configuration
10
Physical Dimensions inches (millimeters)
8-Pin Molded Small Outline Package (M8)
Order Number: NM24C03M8/EM8 or MM8
NM24C05M8/EM8 or MM8
NS Package Number M08A
14-Pin Molded Small Outline Package (M)
Order Number: NM24C03M, NM24C03EM or NM24C03MM;
NM24C05M, NM24C05EM or NM24C05MM;
NM24C09M, NM24C09EM or NM24C09MM;
NM24C17M, NM24C17EM or NM24C17MM
NS Package Number M14B
11
Ý
Lit. 112247
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package (N)
Order Number: NM24C03N, NM24C03EN or NM24C03MN;
NM24C05N, NM24C05EN or NM24C05MN;
NM24C09N, NM24C09EN or NM24C09MN;
NM24C17N, NM24C17EN or NM24C17MN
NS Package Number N08E
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