MM74HC51J/A+ [NSC]
IC,LOGIC GATE,2/2-INPUT AND-NOR,HC-CMOS,DIP,14PIN,CERAMIC;
| 型号： | MM74HC51J/A+ |
| 厂家： | 
National Semiconductor |
| 描述： | IC,LOGIC GATE,2/2-INPUT AND-NOR,HC-CMOS,DIP,14PIN,CERAMIC 栅 |
| 文件： | 总4页 (文件大小：129K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC51/MM74HC51 Dual AND-OR-Invert Gate
MM54HC58/MM74HC58 Dual AND-OR Gate
General Description
Features
Y
Typical propagation delay: 10 ns
These gates utilize advanced silicon-gate CMOS technology
to achieve operating speeds similar to LS-TTL gates with
the low power consumption of standard CMOS integrated
circuits. All gates have buffered outputs, providing high
noise immunity and the ability to drive 10 LS-TTL loads. The
54HC/74HC logic family is functionally as well as pin-out
compatible with the standard 54LS/74LS logic family. All
inputs are protected from damage due to static discharge by
Y
Wide power supply range: 2–6V
Y
Low quiescent supply current: 20 mA maximum
(74 Series)
Y
Y
Low input current: 1 mA maximum
High output current: 4 mA minimum
internal diode clamps to V
and ground.
CC
Connection Diagrams
Dual-In-Line Package
TL/F/5302–1
Top View
Order Number MM54HC51 or MM74HC51
Dual-In-Line Package
TL/F/5302–2
Top View
Order Number MM54HC58 or MM74HC58
C
1995 National Semiconductor Corporation
TL/F/5302
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
Units
Supply Voltage (V
)
CC
2
6
V
DC Input or Output Voltage
(V , V
0
V
CC
V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
IN OUT
b
b
a
a
DC Input Voltage (V
)
1.5 to V
1.5V
0.5V
IN
CC
CC
Operating Temp. Range (T )
A
DC Output Voltage (V
)
0.5 to V
OUT
b
b
a
MM74HC
MM54HC
40
55
85
C
C
§
§
g
g
g
Clamp Diode Current (I , I
)
20 mA
25 mA
50 mA
IK OK
a
125
DC Output Current, per pin (I
)
OUT
Input Rise or Fall Times
DC V or GND Current, per pin (I
CC
)
CC
e
e
e
(t , t )
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
r
f
CC
CC
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temp. (T ) (Soldering 10 seconds)
L
260 C
§
DC Electrical Characteristics (Note 4)
74HC
54HC
e
T
A
25 C
§
eb
eb
T
A
40 to 85 C
T
55 to 125 C
§
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
V
V
V
Minimum High Level
Input Voltage
2.0V
4.5V
6.0V
1.5
3.15
4.2
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
Maximum Low Level
Input Voltage**
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
e
V or V
IH IL
Minimum High Level
Output Voltage
V
I
OH
IN
s
20 mA
2.0V
4.5V
6.0V
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
I
V
s
or V
4.0 mA
5.2 mA
IN
IH IL
4.5V
6.0V
4.2
5.7
3.98
5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
s
e
V or V
IH IL
V
OL
Maximum Low Level
Output Voltage
V
I
IN
s
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
I
V
s
or V
4.0 mA
5.2 mA
IN
IH IL
4.5V
6.0V
0.2
0.2
0.26
0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
s
e
g
g
g
I
I
Maximum Input
Current
V
V
or GND
6.0V
0.1
1.0
1.0
mA
IN
IN
CC
e
Maximum Quiescent
Supply Current
Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur.
V
IN
V
CC
or GND
6.0V
2.0
20
40
mA
CC
e
I
0 mA
OUT
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e
e
t
f
e
6 ns
AC Electrical Characteristics V
5V, T
25 C, C
§
15 pF, t
CC
A
L
r
Guaranteed
Limit
Symbol
Parameter
Conditions
Typ
Units
t , t
PHL PLH
Maximum Propagation
Delay
10
20
ns
e
e
e
e
AC Electrical Characteristics V
2.0V to 6.0V, C
50 pF, t
t
f
6 ns (unless otherwise specified)
54HC
CC
L
r
74HC
eb
e
T
A
25 C
§
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
Units
A
CC
Typ
Guaranteed Limits
t , t
PHL PLH
Maximum Propagation
Delay
2.0V
4.5V
6.0V
63
13
11
125
25
158
32
186
37
ns
ns
ns
21
27
32
t , t
TLH THL
Maximum Output Rise
and Fall Time
2.0V
4.5V
6.0V
30
8
75
15
13
95
19
16
110
22
ns
ns
ns
7
19
C
C
Power Dissipation
(per AND-OR-Gate)
20
pF
PD
Capacitance (Note 5)
Maximum Input
Capacitance
5
10
10
10
pF
IN
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Physical Dimensions inches (millimeters)
Order Numbers MM54HC51J, MM54HC58J, MM74HC51J, MM74HC58J
NS Package J14A
Order Numbers MM74HC51N, MM74HC58N
NS Package N14A
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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