MM54HC640J [NSC]
Inverting Octal TRI-STATE Transceiver; 反相八路三态收发器
| 型号： | MM54HC640J |
| 厂家： | 
National Semiconductor |
| 描述： | Inverting Octal TRI-STATE Transceiver |
| 文件： | 总6页 (文件大小：139K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1988
MM54HC640/MM74HC640
Inverting Octal TRI-STATE Transceiver
É
MM54HC643/MM74HC643
True-Inverting Octal TRI-STATE Transceiver
General Description
These TRI-STATE bi-directional buffers utilize advanced sili-
con-gate CMOS technology, and are intended for two-way
asynchronous communication between data buses. They
have high drive current outputs which enable high speed
operation even when driving large bus capacitances. These
circuits possess the low power consumption and high noise
immunity usually associated with CMOS circuitry, yet have
speeds comparable to low power Schottky TTL circuits.
These devices can drive up to 15 LS-TTL Loads, and all
inputs are protected from damage due to static discharge by
diodes to V
and ground.
CC
Features
Y
Typical propagation delay: 13 ns
Wide power supply range: 2–6V
Low quiescent current: 80 mA maximum (74 HC)
TRI-STATE outputs for connection to bus oriented
systems
Y
Y
Y
Each device has an active low enable G and a direction
control input, DIR. When DIR is high, data flows from the A
inputs to the B outputs. When DIR is low, data flows from
Y
High output drive: 6 mA (min)
the
B inputs to the A outputs. The MM54HC640/
MM74HC640 transfers inverted data from one bus to other
and the MM54HC643/MM74HC643 transfers inverted data
from the A bus to the B bus and true data from the B bus to
the A bus.
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/5344–2
TL/F/5344–1
Top View
Top View
Order Number MM54HC643 or MM74HC643
Order Number MM54HC640 or MM74HC640
Truth Table
Control
Inputs
Operation
G
L
DIR
L
640
643
B data to A bus
A data to B bus
Isolation
B data to A bus
A data to B bus
Isolation
L
H
H
X
e
e
e
low level, X irrelevant
H
high level, L
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/5344
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Conditions
Min
Max
6
Units
V
Supply Voltage (V
)
CC
2
DC Input or Output Voltage
(V , V
b
a
0.5 to 7.0V
Supply Voltage (V
)
CC
)
0
V
V
IN OUT
CC
b
b
a
a
DC Input Voltage DIR and G pins (V
)
IN
1.5 to V
1.5V
0.5V
Operating Temp. Range (T )
A
MM74HC
MM54HC
CC
CC
b
b
a
85
40
55
C
C
§
DC Output Voltage (V , V
)
0.5 to V
IN OUT
a
125
§
g
g
g
Clamp Diode Current (I
)
CD
20 mA
35 mA
70 mA
Input Rise/Fall Times
DC Output Current, per pin (I
)
OUT
e
e
e
(t , t )
r f
V
V
V
2.0V
4.5V
6.0V
1000
500
400
ns
ns
ns
CC
CC
CC
DC V or GND Current, per pin (I
CC
)
CC
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
STG
Power Dissipation (P )
D
(Note 3)
600 mW
500 mW
S.O. Package only
Lead Temperature (T )
L
(Soldering 10 seconds)
260 C
§
DC Electrical Characteristics (Note 4)
74HC
eb
54HC
e
T
25 C
§
A
eb
T
40 to 85 C
§
T
A
55 to 125 C
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
V
V
V
Minimum High Level Input
Voltage
2.0V
4.5V
6.0V
1.5
1.5
3.15
4.2
1.5
3.15
4.2
V
V
V
IH
3.15
4.2
Maximum Low Level Input
2.0V
4.5V
6.0V
0.5
1.35
1.8
0.5
1.35
1.8
0.5
1.35
1.8
V
V
V
IL
Voltage**
e
V or V
IH IL
Minimum High Level Output
Voltage
V
I
OH
IN
s
20 mA
2.0V 2.0
4.5V 4.5
6.0V 6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 4.2 3.98
6.0V 5.7 5.48
3.84
5.34
3.7
5.2
V
V
l
l
OUT
OUT
l
l
I
e
V or V
IH IL
V
OL
Maximum Low Level Output
Voltage
V
IN
s
I
20 mA
2.0V
4.5V
6.0V
0
0
0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
V
V
l
OUT
l
e
V
I
V
or V
IH IL
IN
s
s
6.0 mA
7.8 mA
4.5V 0.2 0.26
6.0V 0.2 0.26
0.33
0.33
0.4
0.4
V
V
l
l
OUT
OUT
l
l
I
e
V or GND
CC
g
g
g
1.0
I
I
I
Input Leakage
V
6.0V
0.1
1.0
mA
mA
mA
IN
IN
Current (G and DIR)
e
V or GND 6.0V
CC
g
g
g
10
Maximum TRI-STATE Output
Leakage Current
V
0.5
5.0
OZ
CC
OUT
e
Enable G
V
IH
or GND
CC
e
Maximum Quiescent Supply
Current
V
IN
V
6.0V
8.0
80
160
e
I
0 mA
OUT
Note 1: Maximum Ratings are those values beyond which damage to the device may occur.
Note 2: Unless otherwise specified all voltages are referenced to ground.
b
b
Note 3: Power Dissipation temperature derating Ð plastic ‘‘N’’ package: 12 mW/ C from 65 C to 85 C; ceramic ‘‘J’’ package: 12 mW/ C from 100 C to 125 C.
§
§
§
§
Note 4: For a power supply of 5V 10% the worst case output voltages (V , and V ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing
§
§
g
OH OL
5.5V and 4.5V respectively. (The V value at 5.5V is 3.85V.) The worst case leakage current (I , I , and
IH IN CC
e
with this supply. Worst case V and V occur at V
IH IL
CC
) occur for CMOS at the higher voltage and so the 6.0V values should be used.
I
OZ
**V limits are currently tested at 20% of V . The above V specification (30% of V ) will be implemented no later than Q1, CY’89.
IL CC IL CC
2
e
e
e e
25 C, t t 6 ns
§
r f
AC Electrical Characteristics V
5V, T
CC
A
Guaranteed
Limit
Symbol
, t
Parameter
Conditions
Typ
Units
e
C
L
t
t
Maximum Propagation Delay
45 pF
13
33
17
42
ns
ns
PHL PLH
e
e
, t
PZH PZL
Maximum Output Enable Time
R
1 kX
L
C
L
45 pF
e
e
t , t
PHZ PLZ
Maximum Output Disable Time
R
1 kX
32
42
ns
L
C
L
5 pF
e
e
e e
50 pF, t t
r f
AC Electrical Characteristics V
2.0V to 6.0V, C
6 ns (unless otherwise specified)
74HC 54HC
eb
CC
L
e
T
25 C
§
A
eb
A
T
40 to 85 C
T
55 to 125 C
§
§
Symbol
Parameter
Conditions
V
CC
Units
A
Typ
Guaranteed Limits
e
e
t
t
,
Maximum Propagation Delay
C
C
50 pF
2.0V
29
38
72
96
88
96
ns
ns
PHL
L
150 pF 2.0V
116
128
PLH
L
e
e
C
C
50 pF
4.5V
14
18
18
24
22
29
24
32
ns
ns
L
150 pF 4.5V
L
e
e
C
C
50 pF
6.0V
14
18
18
24
22
29
24
32
ns
ns
L
150 pF 6.0V
L
e
t
t
,
Maximum Output Enable
R
1 kX
PZH
L
e
e
C
C
50 pF
2.0V
70
80
184
216
224
260
240
284
ns
ns
PZL
L
150 pF 2.0V
L
e
e
C
C
50 pF
4.5V
35
41
46
54
56
65
60
71
ns
ns
L
150 pF 4.5V
L
e
e
C
C
50 pF
6.0V
31
36
41
47
50
57
54
62
ns
ns
L
150 pF 6.0V
L
e
e
t
t
,
Maximum Output Disable
Time
R
1 kX
2.0V
4.5V
6.0V
47
33
31
172
43
208
52
224
56
ns
ns
ns
PHZ
L
C
L
50 pF
PLZ
41
50
54
e
t , t
THL TLH
Output Rise and Fall Time
C
L
50 pF
2.0V
4.5V
6.0V
20
6
60
12
10
75
15
13
90
18
15
ns
ns
ns
5
e
e
C
PD
Power Dissipation
G
G
V
120
12
pF
pF
IL
Capacitance (Note 5)
V
IH
C
C
Maximum Input Capacitance
5
10
20
10
20
10
20
pF
pF
IN
Maximum Input/Output
Capacitance, A or B
15
IN/OUT
2
e
a
e
a
f I
PD CC CC
Note 5: C determines the no load dynamic power consumption, P
PD
C
V
PD CC
f
I
V
CC CC
, and the no load dynamic current consumption, I
C
V
.
D
S
3
Logic Diagrams
’HC640
’HC643
TL/F/5344–5
TL/F/5344–6
4
5
Physical Dimensions inches (millimeters)
Order Number MM54HC640J, MM54HC643J, MM74HC640J or MM74HC643J
See NS Package J20A
Order Number MM74HC640N or MM74HC643N
See NS Package N20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
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Japan Ltd.
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