MF8CCJ [NSC]
4th-Order Switched Capacitor Bandpass Filter; 四阶开关电容带通滤波器
| 型号： | MF8CCJ |
| 厂家： | 
National Semiconductor |
| 描述： | 4th-Order Switched Capacitor Bandpass Filter |
| 文件： | 总24页 (文件大小：384K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
MF8 4th-Order Switched Capacitor Bandpass Filter
General Description
Features
Y
Center frequency set by external clock
The MF8 consists of two second-order bandpass filter
stages and an inverting operational amplifier. The two filter
stages are identical and may be used as two tracking sec-
ond-order bandpass filters, or cascaded to form a single
fourth-order bandpass filter. The center frequency is con-
trolled by an external clock for optimal accuracy, and may
be set anywhere between 0.1 Hz and 20 kHz. The ratio of
clock frequency to center frequency is programmable to
100:1 or 50:1. Two inputs are available for TTL or CMOS
clock signals. The TTL input will accept logic levels refer-
enced to either the negative power supply pin or the ground
pin, allowing operation on single or split power supplies. The
CMOS input is a Schmitt inverter which can be made to self-
oscillate using an external resistor and capacitor.
Y
Q set by five-bit digital word
Y
Uncommitted inverting op amp
Y
4th-order all-pole filters using only three external
resistors
Y
Y
Cascadable for higher-order filters
Bandwidth, response characteristic, and center
frequency independently programmable
Separate TTL and CMOS clock inputs
Y
Y
18 pin 0.3 wide package
×
Key Specifications
Y
Center frequency range 0.1 Hz to 20 kHz
Y
Q range 0.5 to 90
By using the uncommitted amplifier and resistors for nega-
tive feedback, any all-pole (Butterworth, Chebyshev, etc.)
filter can be formed. This requires only three resistors for a
fourth-order bandpass filter. Q of the second-order stages
may be programmed to any of 31 different values by the five
‘‘Q logic’’ pins. The available Q values span a range from
0.5 through 90. Overall filter bandwidth is programmed by
Y
g
g
Supply voltage range 9V to 14V ( 4.5V to 7V)
Center frequency accuracy 1% over full temperature
range
Y
connecting the appropriate Q logic pins to either Va or Vb
.
Filters with order higher than four can be built by cascading
MF8s.
Typical Application & Connection Diagrams
Dual-In-Line Package
TL/H/8694–2
Top View
Order Number MF8CCJ
or MF8CCN
See NS Package Number
J18A or N18A
TL/H/8694–1
Fourth-Order Butterworth Bandpass Filter
C
1995 National Semiconductor Corporation
TL/H/8694
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
See AN-450 ‘‘Surface Mounting Methods and Their Effect
on Product Reliability’’ for other methods of soldering sur-
face mount devices.
a
b
)
e
b
b
a
0.3V to 15V
Supply Voltage (V
V
V
S
Operating Ratings (Note 1)
Temperature Range
a
b
a
Voltage at any Input (Note 2)
Vb 0.3V to V
0.3V
1 mA
1 mA
s
s
T
T
T
MIN
A
MAX
70 C
§
g
g
Input Current at any Input Pin (Note 2)
Output Short-Circuit Current (Note 7)
Power Dissipation (Note 3)
Storage Temperature
s
s
s
s
a
a
MF8CCN
MF8CCJ
0 C
40 C
T
T
§
§
A
A
b
85 C
§
500 mW
a
b
)
e
b
a
a
9V to 14V
Supply Voltage (V
V
V
S
b
a
65 C to 150 C
§
§
c
f
Q Range
CLK
for 10 Hz
for 250 kHz
Soldering Information:
s
s
f
250 kHz
s
any Q
s
Q 5 MHz
CLK
f
J Package:
N Package:
SO Package:
10 sec.
10 sec.
260 C
§
s
c
CLK
1 MHz
f
CLK
300 C
§
Vapor Phase (60 sec.)
Infrared (15 sec.)
215 C
§
220 C
§
ESD rating is to be determined.
b
Filter Electrical Characteristics The following specifications apply for Va
5V, V
to T
e a
e b
5V, C
LOAD
e
e
50 pF and R
e
50 kX on filter output unless otherwise specified. Boldface limits apply for T
; all other limits
MAX
LOAD
25 C.
MIN
e
T
T
J
§
A
MF8CCN
MF8CCJ
Parameter
(Notes 4, 5)
Tested Design
Limit Limit
(Note 10) (Note 11)
Tested
Limit
(Note 10)
Design
Limit
(Note 11)
Symbol
Conditions
Units
Typical
(Note 9)
Typical
(Note 9)
e
f
CLK
100:1
ABCDE
g
6.02 .05 6.02 0.2
g
g
6.02 0.05 6.02 0.2
g
H
Gain at f
Q
250 kHz
dB
dB
dB
o
o
o
o
o
g
g
3.92 2% 3.92 10%
g g
3.92 2% 3.92 10%
Q
R
e
11100
g
g
99.2 0.3% 99.2 1%
g g
99.2 0.3% 99.2 1%
f
/f
CLK
o
e
g
6.02 0.2 6.02 0.5
g
g
6.02 0.2
g
6.02 0.5
H
o
Gain at f
Q
f
CLK
100:1
ABCDE
250 kHz
g
g
15.5 3% 15.5 12%
g g
15.5 3% 15.5 12%
Q
R
e
10011
g
g
99.7 0.3% 99.7 1%
g g
99.7 0.3% 99.7 1%
f
/f
CLK
o
e
g
5.85 0.4
g
g
5.85 0.4
g
5.85 1
H
o
Gain at f
Q
f
50:1
250 kHz
5.85
1
CLK
g
55 5% 55 14%
g
g
55 5%
g
55 14%
Q
R
e
ABCDE
00001
g
g
49.9 0.2% 49.9 1%
g g
49.9 0.2% 49.9 1%
f
/f
CLK
o
e
S
g
g
5V 5%
250 kHz
H
o
Gain at f
V
f
6.02
g
1.5
g
6.02 0.5
g
6.02 0.5
g
6.02 1.5 dB
s
CLK
e
g
g
5V 5%
250 kHz, Q
DQ/Q Q Deviation from V
TH
S
s
s
l
1
g
g
g
g
g
g
15%
Theoretical
(See Table I)
f
f
5%
2%
15%
5%
2%
CLK
100 kHz,
k
CLK
1
k
g
g
Q
57
6%
1%
6%
1%
e
S
g
g
5V 5%
250 kHz
DR/R
f
/f Deviation V
o
TH CLK
s
g
g
g
0.3%
g
from Theoretical f
(See Table I)
0.3%
CLK
e
ABCDE
Q
Q
f
250 kHz, 50:1
e
10.6
g
10%
CLK
g
10.6 2%
g
g
10.6 2% 10.6 10%
00110
e
e
e
Dynamic Range ABCDE
ABCDE
ABCDE
11100
10011
00001
86
80
75
86
80
75
dB
dB
dB
(Note 6)
Clock
Feedthrough
Filter and Op Amp
s
f
250 kHz
CLK
s
Q
Q
1
1
80
40
80
40
mV
mV
l
e
loads on outputs
I
Maximum Supply f
Current
250 kHz, no
S
CLK
9
12
12
9
13
mA
e
e
4
V
OS
Maximum Filter
Output Offset
Voltage
f
250 kHz, Q
CLK
50:1
100:1
g
g
g
g
g
g
g
g
40
80
120
240
40
80
120
240
mV
mV
e
5 kX
V
OUT
Minimum Filter
Output Swing
R
LOAD
(Note 6)
g
g
g
g
4.1
g
4.1
3.8
3.8
3.6
V
2
b
Op Amp Electrical Characteristics The following specifications apply for Va
5V, V
e a
; all other limits T
e b
5V and no
e
T
J
e
load on the Op Amp output unless otherwise specified. Boldface limits apply for T
to T
25 C.
§
MIN
MAX
A
MF8CCN
MF8CCJ
Typical Tested
Limit
Design Typical Tested
Limit Limit
Design
Limit
Symbol
Parameter
Conditions
Units
(Note 9) (Note 10) (Note 11) (Note 9) (Note 10) (Note 11)
g
g
g
g
20
V
Maximum Input Offset Voltage
Maximum Input Bias Current
Minimum Output Voltage Swing
Open Loop Gain
8
20
8
mV
pA
V
OS
I
10
10
B
e
g
g
3.5
V
R
LOAD
5 kX
3.5
OUT
VOL
A
80
1.8
10
80
1.8
10
dB
GBW
Gain Bandwidth
Product
MHz
SR
Slew Rate
V/ms
b
10V and V
Logic Input and Output Characteristics The following specifications apply for Va
e a
e
e
e
T 25 C.
J
0V unless otherwise specified. Boldface limits apply for T
MIN
to T
; all other limits T
§
MAX
A
MF8CCN
MF8CCJ
Typical Tested Design Typical Tested Design
Symbol
Parameter
Conditions
Units
Limit
Limit
Limit
Limit
(Note 9) (Note 10 (Note 11) (Note 9) (Note 10) (Note 11)
a
V
a
e
to Vb
Positive Threshold
Voltage on pin 8
Negative Threshold
Voltage on pin 8
Min V
V
b referred
b
V
0.7V
0.7V
0.58V
0.89V
0.11V
0.47V
9.0
0.7V
0.7V
0.58V
0.89V
0.11V
0.47V
9.0
V
V
T
S
S
S
S
S
S
S
S
S
S
S
e
0V (Note 8)
Max
S
S
b
V
a
b
b referred 0.35V
0.35V
V
e
to Vb
Min V
V
V
T
S
S
S
S
S
e
0V (Note 8)
Max
0.35V
0.35V
V
e b
e a
V
V
I
Output Voltage on Min High
I
I
10 mA
9.0
1.0
V
OH
O
pin 9 (Note 12)
Max Low
10 mA
1.0
1.0
V
OL
O
Output Current on Min Source Pin 9 tied to Vb
pin 9
6.0
5.0
7.0
3.0
6.0
5.0
7.0
3.0
mA
mA
V
OH
I
Min Sink
Pin 9 tied to Va
2.5
2.5
OL
V
Input Voltage on Min High
9.0
1.0
9.0
IH
IL
pins: 1, 2, 3, 10,
V
Max Low
3.0
3.0
1.0
10
V
17, & 18 (Note 12)
I
Input Current on pins: 1, 2,
3, 7, 8, 10, 17, & 18
IN
10
10
mA
b
Va
Va
10V, V
0V or
e b
2.0
0.8
2.0
0.8
2.0
0.8
V
V
e a
e a
e
V
V
Input Voltage on Min High
IH
b
pin 7
5V, V
5V
Max Low
IL
Note 1: Absolute Maximum Raings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
b
V
a), the absolute value of current at that pin should be
k
l
Note 2: When the applied voltage at any pin falls outside the power supply voltages (V
V
or V
IN
IN
limited to 1 mA or less.
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
b
T
, H , and the ambient temperature, T . The maximum
JA
JMAX
A
e
125 C, and the typical junction-to-ambient thermal resistance of the MF8CCN when board mounted is 50 C/W. For the MF8CCJ, this number
allowable power dissipation at any temperature is P
e
(T
)/H or the number given in the Absolute Maximum Ratings, whichever is lower. For this
A JA
D
JMAX
device, T
JMAX
increases to 65 C/W.
§
§
§
Note 4: The center frequency of each 2nd-order filter section is defined as the frequency where the phase shift through the filter is zero.
Note 5: Q is defined as the measured center frequency divided by the measured bandwidth, where the bandwidth is the difference between the two frequencies
where the gain is 3 dB less than the gain measured at the center frequency.
g
Note 6: Dynamic range is defined as the ratio of the tested minimum output swing of 2.69 Vrms ( 3.8V peak-to-peak) to the wideband noise over a 20 kHz
bandwidth. For Qs of 1 or less the dynamic range and output swing will degrade because the gain at an internal node is 2/Q. Keeping the input signal level below
1.23xQ Vrms will avoid distortion in this case.
3
Note 7: If it is possible for a signal output (pin 6, 14, or 15) to be shorted to Va, Vb or ground, add a series resistor to limit output current.
b
e b
5V the
Note 8: If Vb is anything other than 0V then the value of Vb should be added to the values given in the table. For example for Va
5V and V
e
a
a
e
a
b
e a
5V) 2V.
typical V
0.7 (10V)
(
T
Note 9: Typicals are at 25 C and represent the most likely parametric norm.
§
Note 10: Tested Limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 11: Design Limits are guaranteed but not 100% tested. These limits are not used to calculate outgoing quality levels.
Note 12: These logic levels have been referenced to Vb. The logic levels will shift accordingly for split supplies.
Pin Descriptions
Q Logic Inputs
A, B, C, D, E
(3, 2, 1, 18, 17):
These inputs program the Qs of the two
2nd-order bandpass filter stages. Logic
RC (9):
This pin allows the MF8 to generate its
own clock signal. To do this, connect an
external resistor between the RC pin and
the CMOS Clock input, and an external
capacitor from the CMOS Clock input to
AGND. The TTL Clock input should be
connected to Vb or Va. When the MF8
is driven from an external clock, the RC
pin should be left open.
‘‘1’’ is Va and logic ‘‘0’’ is Vb
.
AGND (4):
This is the analog and digital ground pin
and should be connected to the system
ground for split supply operation or bi-
ased to mid-supply for single supply op-
eration. For best filter performance, the
ground line should be ‘‘clean’’.
Va (12),
Vb (11):
These are the positive and negative
power supply inputs. Decoupling the
power supply pins with 0.1 mF or larger
capacitors is highly recommended.
1.0 Application Information
1.1 INTRODUCTION
A simplified block diagram for the MF8 is shown in Figure 1.
The analog signal path components are two identical 2nd-
order bandpass filters and an operational amplifier. Each
filter has a fixed voltage gain of 2. The filters’ cutoff frequen-
cy is proportional to the clock frequency, which may be ap-
plied to the chip from an external source or generated inter-
nally with the aid of an external resistor and capacitor. The
F1 IN (16),
F2 IN (5):
These are the inputs to the bandpass fil-
ter stages. To minimize gain error the
source impedance should be less than 2
kX. Input signals should be referenced
to AGND.
F1 OUT (15),
F2 OUT (6):
These are the outputs of the bandpass
filter stages.
proportionality constant f /f can be set to either 50 or
CLK 0
100 depending on the logic level on pin 10. The ‘‘Q’’ of the
two filters can have any of 31 values ranging from 0.5 to 90
and is set by the logic levels on pins 1, 2, 3, 17, and 18.
Table I shows the available values of Q and the logic levels
required to obtain them. The operational amplifier’s non-in-
verting input is internally grounded, so it may be used only
for inverting applications.
A IN (13):
This is the inverting input to the uncom-
mitted operational amplifier. The non-in-
verting input is internally connected to
AGND.
A OUT (14):
50/100 (10):
This is the output of the uncommitted
operational amplifier.
This pin sets the ratio of the clock fre-
quency to the bandpass center frequen-
cy. Connecting this pin to Va sets the
ratio to 100:1. Connecting it to Vb sets
the ratio to 50:1.
The components in the analog signal path can be intercon-
nected in several ways, three of which are illustrated in Fig-
ures 2a, 2b and2c. The two second-order filter sections can
be used as separate filters whose center frequencies track
very closely as in Figure 2a. Each filter section has a high
input impedance and low output impedance. The op amp
may be used for gain scaling or other inverting functions. If
sharper cutoff slopes are desired, the two filter sections
may be cascaded as in Figure 2b. Again, the op amp is
uncommitted. The circuit in Figure 2c uses both filter sec-
tions with the op amp and three resistors to build a ‘‘multiple
feedback loop’’ filter. This configuration offers the greatest
flexibility for fourth-order bandpass designs. Virtually any
fourth-order all pole response shape (Butterworth, Cheby-
shev) can be obtained with a wide range of bandwidths,
simply by proper choice of resistor values and Q. The three
connection schemes in Figure 2 will be discussed in more
detail in Sections 1.4 and 1.5.
TTL CLK (7):
This is the TTL-level clock input pin.
There are two logic threshold levels, so
the MF8 can be operated on either sin-
gle-ended or split supplies with the logic
input referred to either Vb or AGND.
When this pin is not used (or when
CMOS logic levels are used), it should
be connected to either Va or Vb
.
CMOS CLK (8):
This pin is the input to a CMOS Schmitt
inverter. Clock signals with CMOS logic
levels may be applied to this input. If the
TTL input is used this pin should be con-
nected to Vb
.
4
Typical Performance Characteristics
f /f Ratio vs Supply
CLK o
f
CLK
FrequencyÐ50:1 Mode
/f Ratio vs Clock
f
CLK
FrequencyÐ100:1 Mode
/f Ratio vs Clock
VoltageÐ50:1 and
100:1 Mode
o
o
TL/H/8694–24
5
Typical Performance Characteristics (Continued)
Positive Swing vs
Load Resistance
Negative Swing vs
Load Resistance
Negative Swing vs
Supply Volage
re
1
TL/H/8694–25
6
1.0 Application Information (Continued)
TL/H/8694–3
FIGURE 1. Simplified Block Diagram of the MF8
TL/H/8694–4
FIGURE 2a. Separate Second-Order ‘‘Tracking’’ Filters
TL/H/8694–5
FIGURE 2b. Fourth-Order Bandpass Made by Cascading Two Second-Order Stages
7
1.0 Application Information (Continued)
TL/H/8694–6
FIGURE 2c. Multiple Feedback Loop Connection
1.2 CLOCKS
Clock signals derived from a crystal-controlled oscillator are
recommended when maximum center frequency accuracy
is desired, but in less critical applications the MF8 can gen-
erate its own clock signal as in Figures 3c and 4c. An exter-
nal resistor and capacitor determine the oscillation frequen-
cy. Tolerance of these components and part-to-part varia-
tions in Schmitt-trigger logic thresholds limit the accuracy of
the RC clock frequency. In the self-clocked mode the TTL
Clock input should be connected to either pin 11 or pin 12.
The MF8 has two clock input pins, one for CMOS logic lev-
els and the other for TTL levels. The TTL (pin 7) input auto-
matically adjusts its switching threshold to enable operation
on either single or split power supplies. When this input is
used, the CMOS logic input should be connected to pin
11(Vb). The CMOS Schmitt trigger input at pin 8 accepts
CMOS logic levels. When it is used, the TTL input should be
connected to either pin 11 (Vb) or pin 12 (Va). The basic
clock hookups for single and split supply operation are
shown in Figures 3 and 4.
TL/H/8694–7
TL/H/8694–8
(a) MF8 Driven with CMOS Logic Level Clock
(b) MF8 Driven with TTL Logic Level Clock
1
e
f
CLK
b
b
V
V
V
V
V
T
a
S
T
b
a
RC ln
À
À
V
#
J # J
S
T
T
b
e
Typically for V
1
*
10V
S
e
f
CLK
1.69 RC
b
*V
Va
V
e
b
S
TL/H/8694–9
(c) MF8 Driven with Schmitt Trigger Oscillator
FIGURE 3. Dual Supply Operation
8
1.0 Application Information (Continued)
pled to the filter input or biased to Va/2. It is strongly rec-
ommended that each power supply pin be bypassed to
ground with at least a 0.1 mF ceramic capacitor. In single
supply applications, with Vb connected to ground, Va and
AGND should be bypassed to system ground.
1.3 POWER SUPPLIES AND ANALOG GROUND
The MF8 can be operated from single or dual-polarity power
supplies. For dual-supply operation, the analog ground (pin
4) should be connected to system ground. When single sup-
plies are used, pin 4 should be biased to Va/2 as inFigures
3 and 4. The input signal should either be capacitively cou-
TL/H/8694–10
(a) MF8 Driven with CMOS Logic Level Clock
TL/H/8694–11
(b) MF8 Driven with TTL Logic Clock
1
e
CLK
b
b
V
V
V
V
V
T
b
a
a
b
S
T
RC
IN
V
À #
J #
J À
S
T
T
e
Typically for V
1
10V
S
e
CLK
1.69 RC
TL/H/8694–12
(c) MF8 Driven with the Schmitt Trigger Oscillator
FIGURE 4. Single supply operation. The AGND pin must be biased to mid-supply.
The input signal should be dc biased to mid-supply or capacitor-coupled to the input pin.
9
1.0 Application Information (Continued)
1.4 MULTIPLE FEEDBACK LOOP CONFIGURATION
The multi-loop approach to building bandpass filters is high-
ly flexible and stable, yet uses few external components.
Figure 5 shows the MF8’s internal operational amplifier and
two second-order filter stages with three external resistors
in a fourth-order multiple feedback configuration. Higher-or-
der filters may be built by adding more second-order sec-
tions and feedback resistors as in Figure 6. The filter’s re-
sponse is determined by the clock frequency, the clock-to-
center-frequency ratio, the ratios of the feedback resistor
values, and the Qs of the second-order filter sections. The
design procedure for multiple feedback filters can be broken
down into a few simple steps:
TL/H/8694–15
FIGURE 7. Graphical representation of the amplitude
response specifications for a bandpass filter. The
filter’s response should fall within the shaded area.
1) Determine the characteristics of the desired filter. This
will depend on the requirements of the particular applica-
tion. For a given application, the required bandpass re-
sponse can be shown graphically as in Figure 7, which
shows the limits for the filter response. Figure 7 also makes
use of several parameters that must be known in order to
design a filter. These parameters are defined below in terms
of Figure 7.
TL/H/8694–13
FIGURE 5. General fourth-order multiple-feedback bandpass filter circuit. MF8 pin numbers are shown.
TL/H/8694–14
FIGURE 6. By adding more second-order filter stages and feedback resistors,
higher order multiple-feedback filters may be built.
10
1.0 Application Information (Continued)
f
These define the filter’s passband.
and f : The filter’s lower and upper cutoff frequencies.
Table I shows the available Q values; the nearest value is
8.5, which is programmed by tying pins 1, 2, 3, and 18 to Va
C1
C2
and pin 17 to Vb
.
f
and f : The boundaries of the filter’s stopband.
S1
S2
BW: The filter’s bandwidth. BW
SBW: The width of the filter’s stopband. SBW
Note that the resistor values obtained from the tables are
e
e
b
f
C1
f
C2
.
normalized for center frequency gain H 1. For differ-
OBP
ent gains, simply divide R by the desired gain.
e
b
f
S1
f
S2
.
0
f : The center frequency of the filter. f is equal to the geo-
0
0
metric mean of f and f : f
5) Choose the clock-to-center-frequency ratio. This will
nominally be 100:1 when pin 10 is connected to pin 12(Va
e
f
.
f
C1 C2
. f is also equal to
0
: The nominal passband gain of the bandpass filter.
C1
C2
0
0
)
the geometric mean of f and f
S1
S2
and 50:1 when pin 10 is connected to pin 11(Vb). 100:1
generally gives a response curve nearer the ideal and fewer
(if any) problems with aliasing, while 50:1 allows operation
over the highest octave of center frequencies (10 kHz to 20
kHz). Supply the MF8 with a clock signal of the appropriate
frequency to either the TTL or CMOS input, depending on
the available clock logic levels.
H
0BP
This is normally taken to be the gain at f .
0
f /BW: The ratio of the center frequency to the bandwidth.
0
For second-order filters, this quantity is also known as ‘‘Q’’.
SBW/BW: The ratio of stopband width to bandwidth. This
quantity is also called ‘‘Omega’’ and may be represented by
the symbol ‘‘X’’.
TABLE I. Q and Clock-to-Center-Frequency Ratio
Versus Logic Levels on ‘‘Q-set’’ Pins
A
: The maximum allowable gain variation within the filter
max
passband. This will depend on the system requirements, but
typically ranges from a fraction of a dB to 3 dB.
50:1 mode
/F
100:1 mode
/F
A : The minimum allowable attenuation in the stopband.
min
Again, the required value will depend on system constraints.
ABCDE
F
Q
F
Q
CLK
o
CLK
o
10000
11000
01000
10100
00100
01100
11100
01010
10010
10110
00010
11110
00110
11001
11010
11101
01001
10011
10101
01110
10001
10111
11011
11111
00101
01011
00111
00001
01101
00011
01111
43.7
45.8
46.8
48.4
48.7
48.9
49.2
49.3
49.4
49.4
49.5
49.6
49.6
49.6
49.7
49.7
49.7
49.7
49.7
49.7
49.8
49.8
49.8
49.8
49.8
49.8
49.8
49.9
49.9
49.9
49.9
0.45
0.71
0.96
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6
11.7
12.5
13.6
14.7
15.8
16.5
17
94.0
95.8
96.8
98.4
98.7
98.9
99.2
99.3
99.4
99.4
99.5
99.6
99.6
99.6
99.7
99.7
99.7
99.7
99.7
99.7
99.8
99.8
99.8
99.8
99.8
99.8
99.8
99.9
99.9
99.9
99.9
0.47
0.73
0.98
2.0
2.5
3.0
4.0
5.0
5.7
6.4
7.6
8.5
10.6
11.7
12.5
13.6
14.7
15.8
16.5
17
2). Choose a Butterworth or Chebyshev response charac-
teristic. Butterworth bandpass filters are monotonic on ei-
ther side of the center frequency, while Chebyshev filters
will have ‘‘ripple’’ in the passband, but generally faster at-
tenuation outside the passband. Chebyshev filters are spec-
ified according to the amount of ripple (in dB) within the
passband.
3) Determine the filter order necessary to meet the re-
sponse requirements defined above. This may be done with
the aid of the nomographs in Figures 8 and 9 for Butter-
worth and Chebyshev filters. To use the nomographs, draw
a line through the desired values on the A
/A scales
MAX MIN
to the left side of the graph. Draw a horizontal line to the
right of this point and mark its intersection with the vertical
line corresponding to the required ratio SBW/BW. The re-
quired filter order will be equal to the number of the curve
falling on or just above the intersection of the two lines. This
is illustrated in Figure 10 for a Chebyshev filter with 1 dB
ripple, 30 dB minimum attenuation in the stopband, and
e
SBW/BW
6.
3. From the Figure, the required filter order is
4) The design tables in section 2.0 can now be used to find
the component values that will yield the desired response
for filters of order 4 through 12. The ‘‘K ’’ give the ratios of
19
19
22
22
n
27
27
resistors ‘‘R ’’ to R , and K is Q divided by f /BW.
Q
n
F
0
30
30
As an example of the Tables’ use, consider a fourth-order
e
33
33
Chebyshev filter with 0.5 dB ripple and f /BW
0
6. Begin by
choosing a convenient value for R , such as 100 kX. From
40
40
F
e
e
R /R
F
the ‘‘0.5 dB Chebyshev’’ filter table, K
1.3405.
134.05k. In a similar man-
ner, R is found to equal 201.61k. Q is found using the
44
44
0
0
e
c
e
1.345
This gives R
R
57
57
0
F
2
68
68
e
c
e
f /BW 8.4174.
column labeled K . This gives Q
Q
K
Q
0
79
79
90
90
11
1.0 Application Information (Continued)
Higher-order filters are designed in a similar manner. An
eighth-order Chebyshev with 0.1 dB ripple, center frequency
equal to 1 kHz, and 100 Hz bandwidth, for example, could
be built as inFigure 11 with the following component values:
in numerical order: Filter 1 (pins 16 and 15) should always
precede Filter 2 (pins 5 and 6). If a second MF8 is used,
Filter 2 of the first MF8 should precede Filter 1 of the sec-
ond MF8, and so on.
e
e
e
e
e
R
R
R
R
R
79.86k
100k
57.82k
188.08k
203.42k
0
F
2
3
4
Dynamic Considerations
Some filter response characteristics will result in high gain
at certain internal nodes, particularly at the op amp output.
This can cause clipping in intermediate stages even when
no clipping is evident at the filter output. The consequences
are significant distortion and degradation of the overall
transfer function. The likelihood of clipping at the op amp
Pins 1, 3, 17 and 18 high, pin 2 low. For 100:1 clock-to-cen-
ter-frequency ratio, pin 10 is tied to Va and the clock fre-
quency is 100 kHz. For 50:1 clock-to-center-frequency ratio,
pin 10 is tied to Vb and the clock frequency is 50 kHz.
output becomes greater as R /R increases. As the design
F
0
tables show, R /R increases with increasing filter order
F
0
When building filters of order 4 or higher, best performance
will always be realized when the filter blocks are cascaded
and increasing ripple. It is good practice to keep out-of-band
input signal levels small enough that the first stage can’t
overload.
12
TL/H/8694–16
FIGURE 8. Butterworth Bandpass Filter Design Nomograph
13
TL/H/8694–17
FIGURE 9. Chebyshev Bandpass Filter Design Nomograph
14
TL/H/8694–18
FIGURE 10. Example of Chebyshev Bandpass Nomograph Use.
SBW
e
e
e
e
3, resulting in n 6.
A
1 dB, A
min
30 dB, and
max
BW
15
1.0 Application Information (Continued)
TL/H/8694–19
FIGURE 11. Eighth-Order multiple-feedback bandpass filter using two MF8s. The circuit shown
accepts a TTL-level clock signal and has a clock-to-center-frequency ratio of 100:1.
1.5 TRACKING AND CASCADED SECOND-ORDER
BANDPASS FILTERS
The individual second-order bandpass stages may be used
as ‘‘stand-alone’’ filters without adding external feedback
resistors. The clock frequency and Q logic voltages set the
center frequency and bandwidth of both second-order
bandpass filters, so the two filters will have equivalent re-
sponses. Thus, they may be used as separate ‘‘tracking’’
filters for two different signal sources as in Figure 2a, or
cascaded as in Figure 2b. For individual or cascaded sec-
b
ond-order bandpass filters, the 3 dB bandwidth and the
amplitude response are given by the following two equa-
tions:
TL/H/8694–21
f
0
b
BW( 3)
e
(1/N)
b
1
(1)
0
2
FIGURE 13. Design Nomograph for Cascaded
Identical Second-Order Bandpass Filters
Q
N
w
0
s
e
e
e
Q
the Q of each second order bandpass stage
the center frequency of the filter in Hertz
Q
(2)
e
c
2
H(s)
f
0
w
0
2
2
a
a
w
s
s
0
e
the center frequency of the filter in radians
w
0
2 qf
0
per second
Q
%
–
where
n
2
b
BW( 3)
e
b
the 3 dB bandwidth of the overall filter
e
e
e
N
the number of cascaded second-order stages
the overall filter transfer function
H(s)
H(s) for a second order bandpass filter is plotted in Figure
12. Curves are shown for several different values of Q. Cen-
ter frequency is normalized to 1 Hz and center-frequency
gain is normalized to 0 dB.
To find the necessary order n for cascaded second-order
bandpass filters using the nomograph in Figure 13, first de-
b
b
3 dB bandwidth BW( 3), stopband width
SBW, and minimum stopband attenuation A . Draw a ver-
termine the
min
a horizontal line
b
tical line up from SBW/BW( 3), and
across from A . The required order is shown on the curve
min
just above the point of intersection of the two lines. Remem-
ber that each second-order filter section will have a center
TL/H/8694–20
frequency gain of 2, so the overall gain of a cascaded filter
N
FIGURE 12. H(s) For second-order bandpass filters with
various values of Q. H normalized in each case to 0 dB.
will be 2
.
o
Cascading filters in this way may provide acceptable per-
formance when minimum external parts count is very impor-
16
1.0 Application Information (Continued)
tant, but much greater flexibility and better performance will
be obtained by using the feedback techniques described in
1.4.
b
ing’’. Aliasing can be reduced or eliminated by limiting the
was f /2
s
10 Hz. This phenomenon is known as ‘‘alias-
input signal spectrum to less than f /2. This may in some
s
cases require the use of a bandwidth-limiting filter (a simple
passive RC network will generally suffice) ahead of the MF8
to attenuate unwanted high-frequency signals. However,
since the clock frequency is much greater than the center
frequency, this will usually not be necessary.
1.6 INPUT IMPEDANCE
The input to each filter block is a switched-capacitor circuit
as shown in Figure 14. During the first half of a clock cycle,
the input capacitor charges to the input voltage V , and
in
during the second half-cycle, its charge is transferred to a
feedback capacitor. The input impedance approximates a
resistor of value
Output Steps
Another characteristic of sampled-data circuits is that the
output voltage changes only once every clock cycle, result-
ing in a discontinuous output signal (Figure 15). The ‘‘steps’’
are smaller when the clock-to-center-frequency ratio is
100:1 than when the ratio is 50:1.
1
j
R
.
in
C
f
in CLK
C
depends on the value of Q selected by the Q logic pins,
in
and varies from about 1 pF to about 5 pF. For a worst-case
Clock Frequency Limitations
e
calculation of R , assume C
in
5 pF. Thus,
in
The performance characteristics of a switched-capacitor fil-
ter depend on the switching (clock) frequency. At very low
clock frequencies (below 10 Hz), the internal capacitors be-
gin to discharge slightly between clock cycles. This is due to
very small parasitic leakage currents. At very low clock fre-
quencies, the time between clock cycles is relatively long,
allowing the capacitors to discharge enough to affect the
filters’ output offset voltage and gain. This effect becomes
stronger at elevated operating temperatures.
1
b
j
R (min)
in
12
f
CLK
c
5
10
At higher clock frequencies, performance deviations are pri-
marily due to the reduced time available for the internal inte-
grating op amps to settle. For this reason, the clock wave-
form’s duty cycle should be as close as possible to 50%,
especially at higher frequencies. Filter Q shows more varia-
tion from the nominal values at higher frequencies, as indi-
cated in the typical performance curves. This is the reason
TL/H/8694–22
FIGURE 14. Simplified MF8 Input Stage
e
for the different maximum limits on Q accuracy at f
CLK
100 kHz in the table of performance
At the maximum clock frequency of
j
the input impedance should never be less than this number.
Source impedance should be low enough that the gain isn’t
significantly affected.
1
MHz, this gives
decreases, so
CLK
e
250 kHz and f
specifications.
CLK
R
200k. Note that R increases as f
in
in
Center Frequency Accuracy
Ideally, the ratio f /f should be precisely 100 or 50, de-
CLK
0
pending on the logic voltage on pin 10. However, as Table I
shows, this ratio will change slightly depending on the Q
selected. As the table shows, the largest errors occur at the
lowest values of Q.
1.7 OUTPUT DRIVE
The filter outputs can typically drive a 5 kX load resistor to
g
over 4V peak-to-peak. Load resistors smaller than 5 kX
should not be used. The operational amplifier can drive the
minimum recommended load resistance of 5 kX to at least
g
3.5V.
1.8 SAMPLED-DATA SYSTEM CONSIDERATIONS
Aliasing
The MF8 is a sampled-data filter, and as such, differs in
many ways from conventional continuous-time filters. An im-
portant characteristic of sampled-data systems is their ef-
fect on signals at frequencies greater than one-half the
sampling frequency. (The MF8’s sampling frequency is the
same as its clock frequency). If a signal with a frequency
greater than one-half the sampling frequency is applied to
the input of a sampled-data system, it will be ‘‘reflected’’ to
a frequency less than one-half the sampling frequency.
TL/H/8694–23
FIGURE 15. Output Waveform of
MF8 Showing Sampling Steps
a
cause the system to respond as though the input frequency
Thus, an input signal whose frequency is f /2
s
10 Hz will
17
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters
BUTTERWORTH RIPPLE 3 dB
Order
K
K
2
K
3
K
K
K
6
K
Q
0
4
5
4
6
2.0000
2.3704
2.9142
3.6340
4.5635
4.0000
2.6667
2.0000
1.6000
1.3333
1.4142
1.5000
1.5307
1.5451
1.5529
9.1429
5.8284
4.4112
3.5800
8
14.3145
6.9094
4.3198
10
*12
27.2014
11.5043
49.0673
CHEBYSHEV RIPPLE 0.01 dB
Order
K
K
K
K
K
K
6
K
6
K
6
K
6
K
6
K
6
K
Q
0
2
3
4
5
4
6
1.9041
1.8277
1.4856
1.0171
3.6339
1.8450
0.9919
0.5740
0.4489
0.9438
1.4257
1.8908
6.6170
3.1209
1.7484
8
5.0414
1.2943
*10
4.8814
CHEBYSHEV RIPPLE 0.02 dB
Order
K
0
K
2
K
K
4
K
5
K
Q
3
4
6
1.8644
1.7024
1.2893
0.8163
3.4922
1.6787
0.8707
0.4934
0.5393
1.0849
1.6106
2.1179
6.0772
2.7661
1.5155
8
4.0779
0.9879
*10
3.7119
CHEBYSHEV RIPPLE 0.03 dB
Order
K
0
K
2
K
K
4
K
5
K
Q
3
4
6
1.8341
1.6183
1.1688
0.7034
3.3871
1.5713
0.7977
0.4467
0.6016
1.1808
1.7362
2.2724
5.7231
2.5491
1.3786
8
3.5270
0.8252
*10
3.0938
CHEBYSHEV RIPPLE 0.04 dB
Order
K
0
K
2
K
K
4
K
5
K
Q
3
4
6
1.8085
1.5535
1.0814
0.6264
3.3009
1.4908
0.7454
0.4139
0.6508
1.2560
1.8348
2.3940
5.4548
2.3919
1.2818
8
3.1471
0.7181
*10
2.6883
CHEBYSHEV RIPPLE 0.05 dB
Order
K
0
K
2
K
K
4
K
5
K
Q
3
4
6
1.7860
1.5002
1.0129
0.5686
3.2268
1.4260
0.7046
0.3888
0.6923
1.3191
1.9175
2.4961
5.2373
2.2685
1.2072
8
2.8609
0.6402
*10
2.3938
CHEBYSHEV RIPPLE 0.06 dB
Order
K
0
K
2
K
K
4
K
5
K
Q
3
4
6
1.7657
1.4548
0.9566
0.5230
3.1612
1.3717
0.6713
0.3685
0.7285
1.3741
1.9897
2.5852
5.0536
2.1670
1.1467
8
2.6336
0.5800
*10
2.1666
18
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE .07 dB
Order
K
0
K
2
K
3
K
4
K
5
K
6
K
Q
4
6
1.7471
1.4150
0.9089
0.4856
3.1020
1.3249
0.6431
0.3516
0.7609
1.4232
2.0543
2.6649
4.8943
2.0808
1.0959
8
2.4466
0.5316
*10
1.9842
CHEBYSHEV RIPPLE .08 dB
Order
K
K
K
K
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
K
Q
0
2
3
4
6
4
6
8
1.7298
1.3795
0.8675
3.0478
1.2837
0.6187
0.7905
1.4679
2.1130
4.7534
2.0060
2.2887
CHEBYSHEV RIPPLE .09 dB
Order
K
K
2
K
3
K
4
K
6
K
6
K
6
K
6
K
6
K
6
K
Q
0
4
6
8
1.7136
1.3475
0.8311
2.9978
1.2469
0.5973
0.8177
1.5090
2.1671
4.6271
1.9400
2.1529
CHEBYSHEV RIPPLE 0.1 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
8
1.6983
1.3183
0.7986
2.9512
1.2137
0.5782
0.8430
1.5473
2.2176
4.5125
1.8809
2.0343
CHEBYSHEV RIPPLE 0.2 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
8
1.5757
1.1128
0.5891
2.5998
0.9894
0.4551
1.0378
1.8413
2.6057
3.7271
1.4954
1.3309
CHEBYSHEV RIPPLE 0.3 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.4833
0.9835
0.4732
2.3575
0.8560
0.3861
1.1804
2.0568
2.8914
3.2501
1.2760
*8
0.9885
CHEBYSHEV RIPPLE 0.4 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.4067
0.8888
0.3956
2.1698
0.7618
0.3391
1.2988
2.2363
3.1299
2.9088
1.1250
*8
0.7792
CHEBYSHEV RIPPLE 0.5 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.3405
0.8143
0.3389
2.0161
0.6897
0.3040
1.4029
2.3944
3.3406
2.6447
1.0114
*8
0.6365
19
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE 0.6 dB
Order
K
K
K
K
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
K
K
K
K
K
K
K
K
Q
0
2
3
4
6
6
6
6
6
6
6
6
4
6
1.2816
0.7530
0.2952
1.8857
0.6316
0.2762
1.4975
2.5385
3.5329
2.4305
0.9212
*8
0.5326
CHEBYSHEV RIPPLE 0.7 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.2283
0.7012
0.2601
1.7727
0.5834
0.2535
1.5852
2.6724
3.7119
2.2515
0.8471
*8
0.4535
CHEBYSHEV RIPPLE 0.8 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.1797
0.6564
0.2314
1.6731
0.5424
0.2344
1.6678
2.7989
3.8811
2.0983
0.7846
*8
0.3913
CHEBYSHEV RIPPLE 0.9 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.1347
0.6171
0.2073
1.5841
0.5068
0.2181
1.7464
2.9194
4.0426
1.9650
0.7309
*8
0.3413
CHEBYSHEV RIPPLE 1.0 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.0930
0.5822
0.1869
1.5039
0.4756
0.2038
1.8219
3.0354
4.1981
1.8475
0.6840
*8
0.3002
CHEBYSHEV RIPPLE 1.1 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.0539
0.5509
0.1693
1.4310
0.4479
0.1913
1.8949
3.1476
4.3487
1.7428
0.6426
*8
0.2660
CHEBYSHEV RIPPLE 1.2 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
1.0173
0.5226
0.1540
1.3643
0.4231
0.1801
1.9657
3.2567
4.4952
1.6487
0.6056
*8
0.2372
CHEBYSHEV RIPPLE 1.3 dB
Order
K
K
2
K
3
K
4
K
Q
0
4
6
0.9828
0.4969
0.1406
1.3029
0.4006
0.1701
2.0348
3.3633
4.6385
1.5634
0.5724
*8
0.2125
20
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE 1.4 dB
Order
K
K
K
K
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
5
K
6
K
6
K
6
K
6
K
6
K
6
K
6
K
6
K
6
K
Q
0
2
3
4
4
6
0.9501
0.4733
1.2461
0.3803
2.1024
3.4678
1.4857
CHEBYSHEV RIPPLE 1.5 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.9192
0.4515
1.1934
0.3616
2.1688
3.5705
1.4145
CHEBYSHEV RIPPLE 1.6 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.8897
0.4315
1.1443
0.3445
2.2341
3.6717
1.3490
CHEBYSHEV RIPPLE 1.7 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.8617
0.4128
1.0983
0.3287
2.2986
3.7717
1.2883
CHEBYSHEV RIPPLE 1.8 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.8350
0.3955
1.0553
0.3141
2.3624
3.8706
1.2321
CHEBYSHEV RIPPLE 1.9 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.8095
0.3793
1.0148
0.3005
2.4255
3.9687
1.1797
CHEBYSHEV RIPPLE 2.0 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.7850
0.3641
0.9767
0.2878
2.4881
4.0660
1.1308
CHEBYSHEV RIPPLE 2.1 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.7616
0.3498
0.9407
0.2759
2.5503
4.1628
1.0850
CHEBYSHEV RIPPLE 2.2 dB
Order
K
0
K
2
K
K
4
K
Q
3
4
6
0.7391
0.3364
0.9067
0.2648
2.6122
4.2591
1.0420
21
2.0 Design Tables for Multiple Feedback Loop Bandpass Filters (Continued)
CHEBYSHEV RIPPLE 2.3 dB
Order
K
0
K
2
K
3
K
4
K
5
K
K
Q
6
4
6
0.7176
0.3237
0.8744
0.2544
2.6737
4.3550
1.0016
CHEBYSHEV RIPPLE 2.4 dB
Order
K
0
K
2
K
3
K
4
K
5
K
K
Q
6
4
6
0.6968
0.3118
0.8438
0.2446
2.7350
4.4507
0.9635
CHEBYSHEV RIPPLE 2.5 dB
Order
K
K
K
K
K
5
K
5
K
5
K
5
K
5
K
5
K
K
K
K
K
K
K
Q
0
2
3
4
6
6
6
6
6
6
4
6
0.6769
0.3005
0.8148
0.2353
2.7962
4.5462
0.9275
CHEBYSHEV RIPPLE 2.6 dB
Order
K
0
K
2
K
3
K
4
K
Q
4
6
0.6577
0.2897
0.7871
0.2265
2.8573
4.6415
0.8935
CHEBYSHEV RIPPLE 2.7 dB
Order
K
0
K
2
K
3
K
4
K
Q
4
6
0.6392
0.2796
0.7607
0.2182
2.9183
4.7368
0.8612
CHEBYSHEV RIPPLE 2.8 dB
Order
K
0
K
2
K
3
K
4
K
Q
4
6
0.6213
0.2699
0.7356
0.2104
2.9792
4.8322
0.8306
CHEBYSHEV RIPPLE 2.9 dB
Order
K
0
K
2
K
3
K
4
K
Q
4
6
0.6041
0.2607
0.7116
0.2029
3.0402
4.9276
0.8016
CHEBYSHEV RIPPLE 3.0 dB
Order
K
0
K
2
K
3
K
4
K
Q
4
6
0.5875
0.2519
0.6886
0.1959
3.1013
5.0231
0.7739
Note: Multiple feedback loop filters of higher order than those specified in the tables will oscillate due to phase shift at the output of the summing amplifier. This
phase shift is not the fault of the MF8; it is inherent in this type of multiple feedback loop topology. In addition, all filters marked with an asterisk (*) will be unstable
s
for Q
1, due to phase shifts caused by the MF8’s switched-capacitor design approach.
22
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number MF8CCJ
NS Package Number J18A
23
Ý
Lit. 108778
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number MF8CCN
NS Package Number N18A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
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effectiveness.
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