LP3999ITLX-1.6NOPB [NSC]
Low Noise 150mA Voltage Regulator for RF/Analog Applications; 低噪声150毫安电压调节器的射频/模拟应用
| 型号： | LP3999ITLX-1.6NOPB |
| 厂家： | 
National Semiconductor |
| 描述： | Low Noise 150mA Voltage Regulator for RF/Analog Applications |
| 文件： | 总12页 (文件大小：693K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 2005
LP3999
Low Noise 150mA Voltage Regulator for RF/Analog
Applications
General Description
Key Specifications
n 2.5V to 6.0V Input Range
The LP3999 regulator is designed to meet the requirements
of portable wireless battery-powered applications and will
provide an accurate output voltage with low noise and low
quiescent current. Ideally suited for powering RF/Analog
devices this device will also be used to meet more general
circuit requirements.
n Accurate Output Voltage; 75mV / 2%
>
n 60 mV Typical Dropout with 150 mA Load. Vout 2.5V
n Virtually Zero Quiescent Current when Disabled
n 10 µVrms output noise over 10Hz to 100kHz
n Stable with a 1 µF Output Capacitor
For battery powered applications the low dropout and low
ground current provided by the device allows the lifetime of
the battery to be maximized.The inclusion of an Enable(dis-
able) control can be used by the system to further extend the
battery lifetime by reducing the power consumption to virtu-
ally zero. Should the application require a device with an
active disable function please refer to device LP3995.
n Guaranteed 150 mA Output Current
n Fast Turn-on Time; 140 µs (Typ.)
Features
n 5 pin micro SMD Package
n Stable with Ceramic Capacitor
n Logic Controlled Enable
n Fast Turn-on
The LP3999 also features internal protection against short-
circuit currents and over-temperature conditions.
The LP3999 is designed to be stable with small 1.0 µF
ceramic capacitors. The small outline of the LP3999 micro
SMD package with the required ceramic capacitors can
realize a system application within minimal board area.
n Thermal-overload and short-circuit protection
n
−40 to +125˚C junction temperature range for operation
Applications
Performance is specified for a −40˚C to +125˚C temperature
range.
n GSM Portable Phones
n CDMA Cellular Handsets
n Wideband CDMA Cellular Handsets
n Bluetooth Devices
n Portable Information Appliances
n Handheld MP3 Devices
The device is available in micro SMD package. For other
package options contact your local NSC sales office.
The device is available in fixed output voltages in the ranges
of 1.5V to 3.3V. For availability, please contact your local
NSC sales office.
Typical Application Circuit
20052001
© 2005 National Semiconductor Corporation
DS200520
www.national.com
Block Diagram
20052002
Pin Descriptions
Package 5–pin microSMD
Pin No.
Symbol
Name and Function
A1
VEN
Enable Input; Disables the Regulator when ≤ 0.4V.
Enables the regulator when ≥ 0.9V
Common Ground
B2
C1
C3
A3
GND
VOUT
Voltage output. Connect this output to the load circuit.
Voltage Supply Input
VIN
CBYPASS
Bypass Capacitor connection.
Connect a 0.01 µF capacitor for noise reduction.
Connection Diagram
micro SMD, 5 Bump Package
20052003
See NS Package Number TLA05
www.national.com
2
Ordering Information
For micro SMD Package
LP3999 Supplied as 250
Output Voltage
(V)
Grade
LP3999 Supplied as
3000 Units, Tape and
Reel
Package
Marking
Units, Tape and Reel
1.5
1.6 (Note 2)
1.7(Note 2)
1.8
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3999ITL-1.5
LP3999ITL-1.6
LP3999ITL-1.7
LP3999ITL-1.8
LP3999ITL-1.875
LP3999ITL-1.9
LP3999ITL-2.0
LP3999ITL-2.1
LP3999ITL-2.2
LP3999ITL-2.4
LP3999ITL-2.5
LP3999ITL-2.6
LP3999ITL-2.8
LP3999ITL-3.0
LP3999ITL-3.3
LP3999ITLX-1.5
LP3999ITLX-1.6
LP3999ITLX-1.7
LP3999ITLX-1.8
LP3999ITLX-1.875
LP3999ITLX-1.9
LP3999ITLX-2.0
LP3999ITLX-2.1
LP3999ITLX-2.2
LP3999ITLX-2.4
LP3999ITLX-2.5
LP3999ITLX-2.6
LP3999ITLX-2.8
LP3999ITLX-3.0
LP3999ITLX-3.3
1.875
1.9 (Note 2)
2.0(Note 2)
2.1 (Note 2)
2.2(Note 2)
2.4
2.5
2.6(Note 2)
2.8
3.0(Note 2)
3.3
For micro SMD Package UNLEADED
Output Voltage
(V)
Grade
LP3999 Supplied as 250
Units, Tape and Reel
LP3999 Supplied as
3000 Units, Tape and
Reel
Package
Marking
1.5 (Note 2)
1.6 (Note 2)
1.7 (Note 2)
1.8 (Note 2)
1.875 (Note 2)
1.9 (Note 2)
2.0(Note 2)
2.1 (Note 2)
2.2(Note 2)
2.4 (Note 2)
2.5 (Note 2)
2.6(Note 2)
2.8 (Note 2)
3.0(Note 2)
3.3(Note 2)
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
STD
LP3999ITL-1.5 NOPB
LP3999ITL-1.6 NOPB
LP3999ITL-1.7 NOPB
LP3999ITL-1.8 NOPB
LP3999ITL-1.875 NOPB
LP3999ITL-1.9 NOPB
LP3999ITL-2.0 NOPB
LP3999ITL-2.1 NOPB
LP3999ITL-2.2 NOPB
LP3999ITL-2.4 NOPB
LP3999ITL-2.5 NOPB
LP3999ITL-2.6 NOPB
LP3999ITL-2.8 NOPB
LP3999ITL-3.0 NOPB
LP3999ITL-3.3 NOPB
LP3999ITLX-1.5 NOPB
LP3999ITLX-1.6 NOPB
LP3999ITLX-1.7 NOPB
LP3999ITLX-1.8 NOPB
LP3999ITLX-1.875 NOPB
LP3999ITLX-1.9 NOPB
LP3999ITLX-2.0 NOPB
LP3999ITLX-2.1 NOPB
LP3999ITLX-2.2 NOPB
LP3999ITLX-2.4 NOPB
LP3999ITLX-2.5 NOPB
LP3999ITLX-2.6 NOPB
LP3999ITLX-2.8 NOPB
LP3999ITLX-3.0 NOPB
LP3999ITLX-3.3 NOPB
Note 1: Available in sample quantities only
Note 2: For availability contact your local sales office
3
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Absolute Maximum Ratings
(Notes 3, 4)
Human Body Model
Machine Model
2 kV
200V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Ratings (Note 3)
Input Voltage (VIN
)
2.5 to 6.0V
0 to 6.0V
Input Voltage (VIN
Output Voltage
)
−0.3 to 6.5V
−0.3 to (VIN + 0.3V)
to 6.5V (max)
−0.3 to 6.5V
Enable Input Voltage
Junction Temperature
Ambient Temperature Range
(Note 7)
−40 to +125˚C
-40 to 85˚C
Enable Input Voltage
Junction Temperature
Lead/Pad Temperature
(Note 5)
150˚C
Thermal Properties(Note 8)
Junction to Ambient Thermal
Resistance
microSMD
260˚C
−65 to +150˚C
Internally limited
Storage Temperature
Continuous Power Dissipation
(Note 6)
θJA (micro SMD pkg.)
255˚C/W
ESD (Note 9)
Electrical Characteristics
Unless otherwise noted, VEN = 1.5, VIN = VOUT(NOM) + 1.0V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, CBP = 0.01 µF. Typical
values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the full tempera-
ture range for operation, −40 to +125˚C. (Notes 13, 14)
Limit
Symbol
Parameter
Conditions
Typical
Units
Min
Max
VIN
Input Voltage
2.5
6.0
V
<
DEVICE OUTPUT: 1.5 ≤ VOUT 1.8V
∆VOUT
Output Voltage Tolerance
IOUT = 1 mA
−50
50
mV
-75
75
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
−3.5
3.5
75
mV/V
µV/mA
dB
Load Regulation Error
Power Supply Rejection Ratio
(Note 11)
IOUT = 1 mA to 150 mA
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
10
58
58
PSRR
<
DEVICE OUTPUT: 1.8 ≤ VOUT 2.5V
∆VOUT
Output Voltage Tolerance
IOUT = 1 mA
-50
50
mV
−75
75
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
−2.5
2.5
75
mV/V
µV/mA
dB
Load Regulation Error
Power Supply Rejection Ratio
(Note 11)
IOUT = 1 mA to 150 mA
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
10
60
60
PSRR
DEVICE OUTPUT: 2.5 ≤ VOUT ≤ 3.3V
∆VOUT
Output Voltage Tolerance
IOUT = 1 mA
-2
2
% of
VOUT(NOM)
−3
3
Line Regulation Error
VIN = (VOUT(NOM)+1.0V) to 6.0V,
IOUT = 1 mA
−0.1
0.1
%/V
%/mA
mV
Load Regulation Error
Dropout Voltage
IOUT = 1 mA to 150 mA
IOUT = 1 mA
0.0004
0.4
0.002
2
VDO
IOUT = 150 mA
60
100
PSRR
Power Supply Rejection Ratio
(Note 11)
f = 1 kHz, IOUT = 1 mA
f = 10 kHz, IOUT = 1 mA
60
dB
µA
50
FULL VOUT RANGE
ILOAD
Load Current
(Notes 10, 11)
4
0
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Electrical Characteristics (Continued)
Unless otherwise noted, VEN = 1.5, VIN = VOUT(NOM) + 1.0V, CIN = 1 µF, IOUT = 1 mA, COUT = 1 µF, CBP = 0.01 µF. Typical
values and limits appearing in normal type apply for TJ = 25˚C. Limits appearing in boldface type apply over the full tempera-
ture range for operation, −40 to +125˚C. (Notes 13, 14)
Limit
Symbol
Parameter
Conditions
Typical
Units
Min
Max
FULL VOUT RANGE
IQ
Quiescent Current
VEN = 1.5V, IOUT = 0 mA
VEN = 1.5V, IOUT = 150 mA
VEN = 0.4V
85
140
150
200
1.5
µA
0.003
450
ISC
EN
Short Circuit Current Limit
mA
Output Noise Voltage ((Note 11)) BW = 10 Hz to 100 kHz,
VIN = 4.2V, No Load
10
30
µVrms
˚C
BW = 10 Hz to 100 kHz,
VIN = 4.2V, 1mA Load
TSHUTDOWN
Thermal Shutdown
Temperature
Hysteresis
160
20
ENABLE CONTROL CHARACTERISTICS
IEN
Maximum Input Current at
VEN Input
VEN = 0.0V and VIN = 6.0V
0.001
µA
VIL
VIH
Low Input Threshold
High Input Threshold
0.4
V
V
0.9
TIMING CHARACTERISTICS
TON Turn On Time (Note 11)
To 95% Level (Note 12)
140
µs
Note 3: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the Electrical
Characteristics tables.
Note 4: All voltages are with respect to the potential at the GND pin.
Note 5: For further information on these packages please refer to the following application notes;
AN-1112 Micro SMD Package Wafer Level Chip Scale Package.
Note 6: Internal Thermal shutdown circuitry protects the device from permanent damage.
Note 7: In applications where high power dissipation and/or poor thermal resistance is present, the maximum ambient temperature may have to be derated.
Maximum ambient temperature (T
) is dependant on the maximum operating junction temperature (T
), the maximum power dissipation (P
), and
A(max)
J(max-op)
D(max)
the junction to ambient thermal resistance in the application (θ ). This relationship is given by :-
JA
TA(max) = TJ(max-op) − (PD(max) x θJA
)
Note 8: Junction to ambient thermal resistance is highly dependant on the application and board layout. In applications where high thermal dissipation is possible,
special care must be paid to thermal issues in the board design.
Note 9: The human body is 100 pF discharge through 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor discharged directly into each pin.
Note 10: The device maintains the regulated output voltage without load.
Note 11: This electrical specification is guaranteed by design.
Note 12: Time from V = 0.9V to V
= 95% (V
)
OUT(NOM)
EN
OUT
Note 13: All limits are guaranteed. All electrical characteristics having room-temperature limits are tested during production at T = 25˚C or correlated using
J
Statistical Quality Control methods. Operation over the temperature specification is guaranteed by correlating the electrical characteristics to process and
temperature variations and applying statistical process control.
Note 14: V
is the stated output voltage option for the device.
OUT(NOM)
Recommended Output Capacitor
Limit
Symbol
COUT
Parameter
Output Capacitor
Conditions
Typical
Units
Min
0.70
5
Max
Capacitance (Note 15)
ESR
1.0
µF
500
mΩ
Note 15: The capacitor tolerance should be 30% or better over temperature. Recommended capacitor type is X7R however dependant on application X5R,Y5V and
Z5U can also be used.
5
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Input Test Signals
20052006
FIGURE 1. Line Transient Response Input Test Signal
20052007
FIGURE 2. PSRR Input Test Signal
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6
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN
= VOUT + 1.0V, TA = 25˚C, Enable pin is tied to VIN
.
Output Voltage Change vs Temperature
Ground Current vs Load Current (1.8V VOUT
)
20052011
20052010
@
@
Ground Current vs VIN 25˚C
Ground Current vs VIN 125˚C
20052014
20052015
@
Ground Current vs VIN -40˚C
Short Circuit Current
20052016
20052013
7
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Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN
= VOUT + 1.0V, TA = 25˚C, Enable pin is tied to VIN. (Continued)
Line Transient Response (1.8V VOUT
)
Line Transient Response (1.5V VOUT)
20052018
20052017
Ripple Rejection (1.8V VOUT
)
Ripple Rejection (1.5V VOUT)
20052019
20052020
Enable Start-Up Time (VOUT = 1.8V)
Enable Start-Up Time (VOUT = 1.8V)
20052030
20052031
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8
Typical Performance Characteristics Unless otherwise specified, CIN = COUT = 1.0 µF Ceramic, VIN
= VOUT + 1.0V, TA = 25˚C, Enable pin is tied to VIN. (Continued)
Enable Start-Up Time (VOUT = 1.5V)
Enable Start-Up Time (VOUT = 1.5V)
20052032
20052033
Load Transient Response (VOUT = 1.8V)
Load Transient Response (VOUT = 1.5V)
20052022
20052021
Output Noise Density VIN = 4.2V VOUT = 2.5V)
20052034
9
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OUTPUT CAPACITOR
Application Hints
The LP3999 is designed specifically to work with very small
ceramic output capacitors. A ceramic capacitor (dielectric
types Z5U, Y5V or X7R) in the 1.0 [to 10 µF] range, and with
ESR between 5 mΩ to 500 mΩ, is suitable in the LP3999
application circuit.
POWER DISSIPATION AND DEVICE OPERATION
The permissible power dissipation for any package is a
measure of the capability of the device to pass heat from the
power source, the junctions of the IC, to the ultimate heat
sink, the ambient environment. Thus the power dissipation is
dependent on the ambient temperature and the thermal
resistance across the various interfaces between the die and
ambient air.
For this device the output capacitor should be connected
between the VOUT pin and ground.
It may also be possible to use tantalum or film capacitors at
the device output, VOUT, but these are not as attractive for
reasons of size and cost (see the section Capacitor Charac-
teristics).
Re-stating the equation given in (Note 7) in the electrical
specification section, the allowable power dissipation for the
device in a given package can be calculated:
The output capacitor must meet the requirement for the
minimum value of capacitance and also have an ESR value
that is within the range 5 mΩ to 500 mΩ for stability.
NO-LOAD STABILITY
The LP3999 will remain stable and in regulation with no
external load. This is an important consideration in some
circuits, for example CMOS RAM keep-alive applications.
With a θJA = 255˚C/W, the device in the micro SMD package
returns a value of 392 mW with a maximum junction tem-
perature of 125˚C.
The actual power dissipation across the device can be rep-
resented by the following equation:
CAPACITOR CHARACTERISTICS
The LP3999 is designed to work with ceramic capacitors on
the output to take advantage of the benefits they offer. For
capacitance values in the range of 1 µF to 4.7 µF, ceramic
capacitors are the smallest, least expensive and have the
lowest ESR values, thus making them best for eliminating
high frequency noise. The ESR of a typical 1 µF ceramic
capacitor is in the range of 20 mΩ to 40 mΩ, which easily
meets the ESR requirement for stability for the LP3999.
PD = (VIN − VOUT) x IOUT
.
This establishes the relationship between the power dissipa-
tion allowed due to thermal consideration, the voltage drop
across the device, and the continuous current capability of
the device. These two equations should be used to deter-
mine the optimum operating conditions for the device in the
application.
The temperature performance of ceramic capacitors varies
by type. Most large value ceramic capacitors ( ≥ 2.2 µF) are
manufactured with Z5U or Y5V temperature characteristics,
which results in the capacitance dropping by more than 50%
as the temperature goes from 25˚C to 85˚C.
EXTERNAL CAPACITORS
In common with most regulators, the LP3999 requires exter-
nal capacitors to ensure stable operation. The LP3999 is
specifically designed for portable applications requiring mini-
mum board space and smallest components. These capaci-
tors must be correctly selected for good performance.
A better choice for temperature coefficient in a ceramic
capacitor is X7R. This type of capacitor is the most stable
and holds the capacitance within 15% over the tempera-
ture range. Tantalum capacitors are less desirable than ce-
ramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and volt-
age ratings in the 1 µF to 4.7 µF range.
INPUT CAPACITOR
An input capacitor is required for stability. It is recommended
that a 1.0 µF capacitor be connected between the LP3999
input pin and ground (this capacitance value may be in-
creased without limit).
Another important consideration is that tantalum capacitors
have higher ESR values than equivalent size ceramics. This
means that while it may be possible to find a tantalum
capacitor with an ESR value within the stable range, it would
have to be larger in capacitance (which means bigger and
more costly) than a ceramic capacitor with the same ESR
value. It should also be noted that the ESR of a typical
tantalum will increase about 2:1 as the temperature goes
from 25˚C down to −40˚C, so some guard band must be
allowed.
This capacitor must be located a distance of not more than
1 cm from the input pin and returned to a clean analogue
ground. Any good quality ceramic, tantalum, or film capacitor
may be used at the input.
Important: Tantalum capacitors can suffer catastrophic fail-
ures due to surge current when connected to a low-
impedance source of power (like a battery or a very large
capacitor). If a tantalum capacitor is used at the input, it must
be guaranteed by the manufacturer to have a surge current
rating sufficient for the application.
NOISE BYPASS CAPACITOR
There are no requirements for the ESR (Equivalent Series
Resistance) on the input capacitor, but tolerance and tem-
perature coefficient must be considered when selecting the
capacitor to ensure the capacitance will remain ≅ 1.0 µF over
the entire operating temperature range.
A bypass capacitor should be connected between the CBY
-
PASS pin and ground to significantly reduce the noise at the
regulator output. This device pin connects directly to a high
impedance node within the bandgap reference circuitry. Any
significant loading on this node will cause a change on the
regulated output voltage. For this reason, DC leakage cur-
rent through this pin must be kept as low as possible for best
output voltage accuracy.
The use of a 0.01µF bypass capacitor is strongly recom-
mended to prevent overshoot on the output during start-up.
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10
microSMD MOUNTING
Application Hints (Continued)
The micro SMD package requires specific mounting tech-
niques which are detailed in National Semiconductor Appli-
cation Note AN-1112.
The types of capacitors best suited for the noise bypass
capacitor are ceramic and film. High quality ceramic capaci-
tors with NPO or COG dielectric typically have very low
leakage. Polypropolene and polycarbonate film capacitors
are available in small surface-mount packages and typically
have extremely low leakage current.
Referring to the section Surface Mount Technology (SMT)
Assembly Considerations, it should be noted that the pad
style which must be used with the 5 pin package is NSMD
(non-solder mask defined) type.
Unlike many other LDO’s, the addition of a noise reduction
capacitor does not effect the transient response of the de-
vice.
For best results during assembly, alignment ordinals on the
PC board may be used to facilitate placement of the micro
SMD device.
ENABLE OPERATION
microSMD LIGHT SENSITIVITY
The LP3999 may be switched ON or OFF by a logic input at
the ENABLE pin, VEN. A high voltage at this pin will turn the
device on. When the enable pin is low, the regulator output is
off and the device typically consumes 3 nA. If the application
does not require the shutdown feature, the VEN pin should
be tied to VIN to keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive
the VEN input must be able to swing above and below the
specified turn-on/off voltage thresholds listed in the Electrical
Exposing the micro SMD device to direct sunlight will cause
incorrect operation of the device. Light sources such as
halogen lamps can affect electrical performance if they are
situated in proximity to the device.
Light with wavelengths in the red and infra-red part of the
spectrum have the most detrimental effect thus the fluores-
cent lighting used inside most buildings has very little effect
on performance. Tests carried out on a micro SMD test
board showed a negligible effect on the regulated output
voltage when brought within 1 cm of a fluorescent lamp. A
deviation of less than 0.1% from nominal output voltage was
observed.
Characteristics section under VIL and VIH
.
FAST TURN ON
Fast turn-on is guaranteed by control circuitry within the
reference block allowing a very fast ramp of the output
voltage to reach the target voltage. There is no active turn-off
on this device. Refer to LP3995 for a similar device with
active turn-off.
11
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Physical Dimensions inches (millimeters) unless otherwise noted
micro SMD, 5 Bump, Package (TLA05)
NS Package Number TLA05ADA
The dimensions for X1, X2 and X3 are given as:
X1 = 1.006 +/− 0.03mm
X2 = 1.438 +/− 0.03mm
X3 = 0.600 +/− 0.075mm
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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IC VREG 1.875 V FIXED POSITIVE LDO REGULATOR, PBGA5, LEAD-FREE, MICRO, SMD-5, Fixed Positive Single Output LDO Regulator
NSC
LP3999ITLX-1.9/NOPB
IC VREG 1.9 V FIXED POSITIVE LDO REGULATOR, PBGA5, LEAD-FREE, MICRO, SMD-5, Fixed Positive Single Output LDO Regulator
NSC
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