LP38693SD-5.0_技术文档

PRELIMINARY

January 2005

LP38691/LP38693

500mA Low Dropout CMOS Linear Regulators

Stable with Ceramic Output Capacitors

General Description

Features

n 2.0% output accuracy (25˚C)

The LP38691/3 low dropout CMOS linear regulators provide

tight output tolerance (2.0% typical), extremely low dropout

@

n Low dropout voltage: 250 mV 500mA (typ, 5V out)

n Wide input voltage range (2.7V to 10V)

n Precision (trimmed) bandgap reference

n Guaranteed specs for -40˚C to +125˚C

n 1µA off-state quiescent current

@

voltage (250 mV

500mA load current, V_OUT= 5V), and

excellent AC performance utilizing ultra low ESR ceramic

output capacitors.

The low thermal resistance of the LLP, SOT-223 and T0-252

packages allow the full operating current to be used even in

high ambient temperature environments.

n Thermal overload protection

n Foldback current limiting

The use of a PMOS power transistor means that no DC base

drive current is required to bias it allowing ground pin current

to remain below 100 µA regardless of load current, input

voltage, or operating temperature.

n T0-252, SOT-223 and 6-Lead LLP packages

n Enable pin (LP38693)

Applications

@

Dropout Voltage: 250 mV (typ) 500mA (typ. 5V out).

n Hard Disk Drives

Ground Pin Current: 55 µA (typ) at full load.

n Notebook Computers

n Battery Powered Devices

n Portable Instrumentation

Precision Output Voltage: 2.0% (25˚C) accuracy.

Typical Application Circuits

20126501

20126502

Note: * Minimum value required for stability.

**LLP package devices only.

DS201265

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Connection Diagrams

20126503

TO-252, Top View

LP38691DT-X.X

20126504

SOT-223, Top View

LP38693MP-X.X

20126505

20126506

6-Lead LLP, Bottom View

LP38693SD-X.X

6-Lead LLP, Bottom View

LP38691SD-X.X

Pin Description

DESCRIPTION

V_IN

This is the input supply voltage to the regulator. For LLP devices, both V_INpins must be tied

together for full current operation (250mA maximum per pin).

GND

SNS

Circuit ground for the regulator. This is connected to the die through the lead frame, and also

functions as the heat sink when the large ground pad is soldered down to a copper plane.

Output sense pin allows remote sensing at the load which will eliminate the error in output

voltage due to voltage drops caused by the resistance in the traces between the regulator and

the load. This pin must be tied to V_OUT

.

V_EN

The enable pin allows the part to be turned ON and OFF by pulling this pin high or low.

Regulated output voltage

V_OUT

Ordering Information

Order Number

LP38691SD-1.8

LP38691SD-2.5

LP38691SD-3.3

LP38691SD-5.0

LP38691DT-1.8

LP38691DT-2.5

LP38691DT-3.3

LP38691DT-5.0

LP38693SD-1.8

LP38693SD-2.5

LP38693SD-3.3

LP38693SD-5.0

LP38693MP-1.8

Package Marking

Package Type

6-Lead LLP

TO-252

Package Drawing

SDE06A

TD03B

Supplied As

L118B

L119B

1000 Units Tape and Reel

Available Soon

L120B

L121B

LP38691DT-1.8

LP38691DT-2.5

LP38691DT-3.3

LP38691DT-5.0

L128B

TO-252

TD03B

Available Soon

TO-252

TD03B

Available Soon

TO-252

TD03B

Available Soon

6-Lead LLP

SOT-223

SDE06A

MP05A

1000 Units Tape and Reel

L129B

L130B

L131B

LJVB

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2

Ordering Information (Continued)

Order Number

LP38693MP-2.5

LP38693MP-3.3

LP38693MP-5.0

LP38691SDX-1.8

LP38691SDX-2.5

LP38691SDX-3.3

LP38691SDX-5.0

LP38691DTX-1.8

LP38691DTX-2.5

LP38691DTX-3.3

LP38691DTX-5.0

LP38693SDX-1.8

LP38693SDX-2.5

LP38693SDX-3.3

LP38693SDX-5.0

LP38693MPX-1.8

LP38693MPX-2.5

LP38693MPX-3.3

LP38693MPX-5.0

Package Marking

LJXB

Package Type

SOT-223

Package Drawing

MP05A

Supplied As

1000 Units Tape and Reel

4500 Units Tape and Reel

Available Soon

LJYB

SOT-223

MP05A

LJZB

SOT-223

MP05A

L118B

6-Lead LLP

TO-252

SDE06A

TD03B

L119B

L120B

L121B

LP38691DT-1.8

LP38691DT-2.5

LP38691DT-3.3

LP38691DT-5.0

L128B

TO-252

TD03B

Available Soon

TO-252

TD03B

Available Soon

TO-252

TD03B

Available Soon

6-Lead LLP

SOT-223

SDE06A

MP05A

4500 Units Tape and Reel

2000 Units Tape and Reel

L129B

L130B

L131B

LJVB

LJXB

SOT-223

MP05A

LJYB

SOT-223

MP05A

LJZB

SOT-223

MP05A

3

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Absolute Maximum Ratings (Note 1)

I_OUT

Internally Limited

−40˚C to +150˚C

Junction Temperature

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Ratings

V_INSupply Voltage

Operating Junction

Temperature Range

Storage Temperature Range

Lead Temp. (Soldering, 5 seconds)

ESD Rating (Note 3)

−65˚C to +150˚C

260˚C

2.7V to 10V

−40˚C to +125˚C

2 kV

Power Dissipation (Note 2)

Internally Limited

-0.3V to 12V

V(max) All pins (with respect to GND)

Electrical Characteristics Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply

over the full operating temperature range. Unless otherwise specified: V_IN= V_OUT+ 1V, C_IN= C_OUT= 10 µF, I_LOAD= 10mA.

Min/Max limits are guaranteed through testing, statistical correlation, or design.

TYP

(Note 4)

Symbol

Parameter

Conditions

MIN

-2.0

-4.0

MAX

2.0

Units

V_O

Output Voltage Tolerance

<

%V_OUT

100 µA I_L0.5A

V_O+ 1V ≤ V_IN≤ 10V

V_O+ 0.5V ≤ V_IN≤ 10V

I_L= 25mA

4.0

∆V_O/∆V_IN

∆V_O/∆I_L

Output Voltage Line Regulation

(Note 6)

0.03

1.8

0.1

5

%/V

%/A

<

Output Voltage Load Regulation 1 mA I_L0.5A

(Note 7)

V_IN= V_O+ 1V

(V_O= 2.5V)

80

145

725

I_L= 0.1A

430

I_L= 0.5A

(V_O= 3.3V)

65

110

550

V_IN- V_OUT

Dropout Voltage (Note 8)

I_L= 0.1A

mV

330

I_L= 0.5A

(V_O= 5V)

45

100

450

I_L= 0.1A

250

I_L= 0.5A

I_Q

Quiescent Current

V_IN≤ 10V, I_L=100 µA - 0.5A

V_EN≤ 0.4V, (LP38693 Only)

V_IN- V_O≤ 4V

55

100

1

0.001

µA

I_L(MIN)

I_FB

Minimum Load Current

Foldback Current Limit

100

>

V_IN- V_O5V

350

850

mA

dB

<

V_IN- V_O4V

PSRR

T_SD

Ripple Rejection

V_IN= V_O+ 2V(DC), with 1V(p-p)

/ 120Hz Ripple

55

160

10

Thermal Shutdown Activation

(Junction Temp)

˚C

T_SD(HYST) Thermal Shutdown Hysteresis

(Junction Temp)

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Electrical Characteristics Limits in standard typeface are for T_J= 25˚C, and limits in boldface type apply

over the full operating temperature range. Unless otherwise specified: V_IN= V_OUT+ 1V, C_IN= C_OUT= 10 µF, I_LOAD= 10mA.

Min/Max limits are guaranteed through testing, statistical correlation, or design. (Continued)

TYP

(Note 4)

Symbol

Parameter

Output Noise

Conditions

MIN

MAX

Units

µV/

e_n

BW = 10Hz to 10kHz

V_O= 3.3V

0.7

@

V_O(LEAK)

V_EN

Output Leakage Current

Enable Voltage (LP38693 Only) Output = OFF

Output = ON, V_IN= 4V

V_O= V_O(NOM) + 1V 10V_IN

0.5

12

µA

0.4

1.8

3.0

4.0

-1

V

Output = ON, V_IN= 6V

Output = ON, V_IN= 10V

V_EN= 0V or 10V, V_IN= 10V

I_EN

Enable Pin Leakage (LP38693

Only)

0.001

1

µA

Note 1: Absolute maximum ratings indicate limits beyond which damage to the component may occur. Operating ratings indicate conditions for which the device

is intended to be functional, but do not guarantee specific performance limits. For guaranteed specifications, see Electrical Characteristics. Specifications do not

apply when operating the device outside of its rated operating conditions.

Note 2: At elevated temperatures, device power dissipation must be derated based on package thermal resistance and heatsink values (if a heatsink is used). The

junction-to-ambient thermal resistance ( θ ) for the TO-252 is approximately 90˚C/W for a PC board mounting with the device soldered down to minimum copper

J-A

area (less than 0.1 square inch). If one square inch of copper is used as a heat dissipator for the TO-252, the θ

drops to approximately 50˚C/W. The SOT-223

J-A

package has a θ of approximately 125˚C/W when soldered down to a minimum sized pattern (less than 0.1 square inch) and approximately 70˚C/W when soldered

J-A

to a copper area of one square inch. The θ values for the LLP package are also dependent on trace area, copper thickness, and the number of thermal vias used

J-A

(refer to application note AN-1187). If power disspation causes the junction temperature to exceed specified limits, the device will go into thermal shutdown.

Note 3: ESD is tested using the human body model which is a 100pF capacitor discharged through a 1.5k resistor into each pin.

Note 4: Typical numbers represent the most likely parametric norm for 25˚C operation.

Note 5: If used in a dual-supply system where the regulator load is returned to a negative supply, the output pin must be diode clamped to ground.

Note 6: Output voltage line regulation is defined as the change in output voltage from nominal value resulting from a change in input voltage.

Note 7: Output voltage load regulation is defined as the change in output voltage from nominal value as the load current increases from 1mA to full load.

Note 8: Dropout voltage is defined as the minimum input to output differential required to maintain the output within 100mV of nominal value.

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Block Diagrams

20126507

FIGURE 1. LP38691 Functional Diagram (LLP)

20126508

FIGURE 2. LP38691 Functional Diagram (TO-252)

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Block Diagrams (Continued)

20126509

FIGURE 3. LP38693 Functional Diagram (LLP)

20126510

FIGURE 4. LP38693 Functional Diagram (SOT-223)

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Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693 only), V_OUT= 1.8V, V_IN= V_OUT+1V, I_L= 10mA.

Noise vs Frequency

Ripple Rejection

Noise vs Frequency

Ripple Rejection

20126536

20126535

20126518

20126537

20126520

20126522

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Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693 only), V_OUT= 1.8V, V_IN= V_OUT+1V, I_L= 10mA. (Continued)

Line Transient Response

20126524

20126526

Line Transient Response

Load Transient Response

20126528

20126542

Load Transient Response

V_OUTvs Temperature (5.0V)

20126544

20126530

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Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693 only), V_OUT= 1.8V, V_IN= V_OUT+1V, I_L= 10mA. (Continued)

V_OUTvs Temperature (3.3V)

V_OUTvs Temperature (2.5V)

20126532

20126531

20126533

20126553

V_OUTvs Temperature (1.8V)

Enable Voltage vs Temperature

20126552

Load Regulation vs Temperature

Line Regulation vs Temperature

20126554

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Typical Performance Characteristics Unless otherwise specified: T_J= 25˚C, C_IN= C_OUT= 10 µF,

enable pin is tied to V_IN(LP38693 only), V_OUT= 1.8V, V_IN= V_OUT+1V, I_L= 10mA. (Continued)

MIN V_INvs I_OUT

Dropout Voltage vs I_OUT

20126556

20126557

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TANTALUM: Solid Tantalum capacitors have good tempera-

ture stability: a high quality Tantalum will typically show a

capacitance value that varies less than 10-15% across the

full temperature range of -40˚C to +125˚C. ESR will vary only

about 2X going from the high to low temperature limits.

Application Hints

EXTERNAL CAPACITORS

Like any low-dropout regulator, external capacitors are re-

quired to assure stability. These capacitors must be correctly

selected for proper performance.

PCB LAYOUT

INPUT CAPACITOR: An input capacitor of at least 1µF is

required (ceramic recommended). The capacitor must be

located not more than one centimeter from the input pin and

returned to a clean analog ground.

Good PC layout practices must be used or instability can be

induced because of ground loops and voltage drops. The

input and output capacitors must be directly connected to the

input, output, and ground pins of the regulator using traces

which do not have other currents flowing in them (Kelvin

connect).

OUTPUT CAPACITOR: An output capacitor is required for

loop stability. It must be located less than 1 centimeter from

the device and connected directly to the output and ground

pins using traces which have no other currents flowing

through them.

The best way to do this is to lay out C_INand C_OUTnear the

device with short traces to the V_IN, V_OUT, and ground pins.

The regulator ground pin should be connected to the exter-

nal circuit ground so that the regulator and its capacitors

have a "single point ground".

The minimum amount of output capacitance that can be

used for stable operation is 1µF. Ceramic capacitors are

recommended (the LP38691/3 was designed for use with

ultra low ESR capacitors). The LP38691/3 is stable with any

output capacitor ESR between zero and 100 Ohms.

It should be noted that stability problems have been seen in

applications where "vias" to an internal ground plane were

used at the ground points of the IC and the input and output

capacitors. This was caused by varying ground potentials at

these nodes resulting from current flowing through the

ground plane. Using a single point ground technique for the

regulator and it’s capacitors fixed the problem. Since high

current flows through the traces going into V_INand coming

from V_OUT, Kelvin connect the capacitor leads to these pins

so there is no voltage drop in series with the input and output

capacitors.

ENABLE PIN (LP38693 only): The LP38693 has an enable

pin which turns the regulator output on and off. Pulling the

enable pin down to a logic low will turn the part off. The

voltage the pin has to be pulled up to in order to assure the

part is on depends on input voltage (refer to Electrical Char-

acteristics section). This pin should be tied to V_INif the

enable function is not used.

Foldback Current Limiting: Foldback current limiting is

built into the LP38691/3 which reduces the amount of output

current the part can deliver as the output voltage is reduced.

The amount of load current is dependent on the differential

voltage between V_INand V_OUT. Typically, when this differen-

tial voltage exceeds 5V, the load current will limit at about

350 mA. When the V_IN- V_OUTdifferential is reduced below

4V, load current is limited to about 850 mA.

RFI/EMI SUSCEPTIBILITY

RFI (radio frequency interference) and EMI (electromagnetic

interference) can degrade any integrated circuit’s perfor-

mance because of the small dimensions of the geometries

inside the device. In applications where circuit sources are

present which generate signals with significant high fre-

>

quency energy content ( 1 MHz), care must be taken to

ensure that this does not affect the IC regulator.

SELECTING A CAPACITOR

It is important to note that capacitance tolerance and varia-

tion with temperature must be taken into consideration when

selecting a capacitor so that the minimum required amount

of capacitance is provided over the full operating tempera-

ture range.

If RFI/EMI noise is present on the input side of the regulator

(such as applications where the input source comes from the

output of a switching regulator), good ceramic bypass ca-

pacitors must be used at the input pin of the IC.

If a load is connected to the IC output which switches at high

speed (such as a clock), the high-frequency current pulses

required by the load must be supplied by the capacitors on

the IC output. Since the bandwidth of the regulator loop is

less than 100 kHz, the control circuitry cannot respond to

load changes above that frequency. This means the effective

output impedance of the IC at frequencies above 100 kHz is

determined only by the output capacitor(s).

Capacitor Characteristics

CERAMIC: For values of capacitance in the 10 to 100 µF

range, ceramics are usually larger and more costly than

tantalums but give superior AC performance for bypassing

high frequency noise because of very low ESR (typically less

than 10 mΩ). However, some dielectric types do not have

good capacitance characteristics as a function of voltage

and temperature.

In applications where the load is switching at high speed, the

output of the IC may need RF isolation from the load. It is

recommended that some inductance be placed between the

output capacitor and the load, and good RF bypass capaci-

tors be placed directly across the load.

Z5U and Y5V dielectric ceramics have capacitance that

drops severely with applied voltage. A typical Z5U or Y5V

capacitor can lose 60% of its rated capacitance with half of

the rated voltage applied to it. The Z5U and Y5V also exhibit

a severe temperature effect, losing more than 50% of nomi-

nal capacitance at high and low limits of the temperature

range.

PCB layout is also critical in high noise environments, since

RFI/EMI is easily radiated directly into PC traces. Noisy

circuitry should be isolated from "clean" circuits where pos-

sible, and grounded through a separate path. At MHz fre-

quencies, ground planes begin to look inductive and RFI/

EMI can cause ground bounce across the ground plane. In

multi-layer PCB applications, care should be taken in layout

so that noisy power and ground planes do not radiate directly

into adjacent layers which carry analog power and ground.

X7R and X5R dielectric ceramic capacitors are strongly rec-

ommended if ceramics are used, as they typically maintain a

capacitance range within 20% of nominal over full operat-

ing ratings of temperature and voltage. Of course, they are

typically larger and more costly than Z5U/Y5U types for a

given voltage and capacitance.

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Attention should be paid to the units of measurement. Spot

noise is measured in units µV/root-Hz or nV/root-Hz and total

output noise is measured in µV(rms)

Application Hints (Continued)

OUTPUT NOISE

Noise is specified in two ways: Spot Noise or Output Noise

Density is the RMS sum of all noise sources, measured at

the regulator output, at a specific frequency (measured with

a 1Hz bandwidth). This type of noise is usually plotted on a

curve as a function of frequency. Total Output Noise or

Broad-Band Noise is the RMS sum of spot noise over a

specified bandwidth, usually several decades of frequencies.

The primary source of noise in low-dropout regulators is the

internal reference. Noise can be reduced in two ways: by

increasing the transistor area or by increasing the current

drawn by the internal reference. Increasing the area will

decrease the chance of fitting the die into a smaller package.

Increasing the current drawn by the internal reference in-

creases the total supply current (ground pin current).

13

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Physical Dimensions inches (millimeters) unless otherwise noted

6-lead, LLP Package

NS Package Number SDE06A

TO-252 Package

NS Package Number TD03B

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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

SOT-223 Package

NS Package Number MP05A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products Stewardship

Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain no ‘‘Banned

Substances’’ as defined in CSP-9-111S2.

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型号：	LP38693SD-5.0
厂家：	National Semiconductor
描述：	500mA Low Dropout CMOS Linear Regulators Stable with Ceramic Output Capacitors 500毫安低压降CMOS线性稳压器稳定器用陶瓷输出电容器稳压器电容器
文件：	总15页 (文件大小：791K)
中文：	中文翻译
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LP38693SD-5.0 [NSC]

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