LMH6504MM [NSC]
Wideband, Low Power, Variable Gain Amplifier; 宽带，低功耗，可变增益放大器
| 型号： | LMH6504MM |
| 厂家： | 
National Semiconductor |
| 描述： | Wideband, Low Power, Variable Gain Amplifier |
| 文件： | 总19页 (文件大小：755K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 2004
LMH6504
Wideband, Low Power, Variable Gain Amplifier
General Description
Features
™
The LMH 6504 is a wideband DC coupled voltage con-
VS = 5V, TA = 25˚C, RF = 1 KΩ, RG = 100Ω, RL = 100Ω, AV
trolled gain stage followed by a high-speed current feedback
Op Amp which can directly drive a low impedance load. Gain
adjustment range is 80 dB for up to 10 MHz by varying the
gain control input voltage, VG.
= AVMAX = 9.7V/V, Typical values unless specified.
n −3 dB BW
n Gain control BW
n Adjustment range ( 10 MHz)
150 MHz
150 MHz
80 dB
<
Maximum gain is set by external components, and the gain
can be reduced all the way to cut-off. Power consumption is
110 mW with a speed of 150 MHz and a gain control band-
width (BW) of 150 MHz. Output referred DC offset voltage is
less than 55 mV over the entire gain control voltage range.
Device-to-device gain matching is within 0.42 dB at maxi-
mum gain. Furthermore, gain is tested and guaranteed over
a wide range. The output current feedback Op Amp allows
n Output offset voltage
n Gain matching (limit)
55 mV
0.42 dB
7V to 12V
1500 V/µs
11 mA
60 mA
2.2V
4.4 nV/
2.6 pA/
−45dBc
n Supply voltage range
n Slew rate (inverting)
n Supply Current (no load)
n Linear Output Current
n Output Voltage Swing
n Input Noise Voltage
n Input Noise Current
n THD (20 MHz, RL = 100Ω, VO = 2 VPP
n Replacement for CLC5523
>
high frequency large signals (Slew Rate
1500 V/µs) and
can also drive a heavy load current (60 mA). Near ideal input
characteristics (i.e. low input bias current, low offset, low pin
3 resistance) enable the device to be easily configured as an
inverting amplifier as well (see Application Information sec-
tion for details).
)
Applications
n Variable attenuator
n AGC
n Voltage controlled filter
n Video imaging processing
To provide ease of use when working with a single supply,
VG range is set to be from 0V to +2V relative to the ground
pin potential (pin 4). VG input impedance is high in order to
ease drive requirement. In single supply operation, the
ground pin is tied to a "virtual" half supply.
LMH6504 gain control is linear in dB for a large portion of the
total gain control range. This makes the device suitable for
AGC applications. For linear gain control applications, see
LMH6503 data sheet.
The combination of minimal external components and small
outline packages (SO8 and MSOP8) allows the LMH6504 to
be used in space-constrained applications.
Typical Application
20084302
AVMAX = 9.7 V/V
20084311
Gain vs. VG
™
LMH is a trademark of National Semiconductor Corporation.
© 2004 National Semiconductor Corporation
DS200843
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Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Junction Temperature
150˚C
Soldering Information:
Infrared or Convection (20 sec)
Wave Soldering (10 sec)
235˚C
260˚C
ESD Tolerance (Note 4):
Human Body
1000V
100V
Operating Ratings (Note 1)
Supply Voltages (V+ - V−)
Machine Model
7V to 12V
Input Current
10 mA
Operating Temperature Range
−40˚C to +85˚C
Output Current
120 mA (Note 3)
Thermal Resistance:
8 -Pin SOIC
(θJC
)
(θJA)
Supply Voltages (V+ - V−)
Voltage at Input/ Output pins
Storage Temperature Range
12.6V
60
165
235
V+ +0.8V, V− −0.8V
−65˚C to 150˚C
8-Pin MSOP
65
Electrical Characteristics(Note 2)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS
=
5V, AVMAX = 9.7 V/V, RF = 1kΩ, RG = 100Ω, VIN
=
0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Min
(Note 6)
Typ
(Note 6)
Max
(Note 6)
Symbol
Parameter
Conditions
Units
Frequency Domain Response
<
BW
GF
-3dB Bandwidth
Gain Flatness
VOUT 1 VPP
150
58
MHz
MHz
<
VOUT 4 VPP, AVMAX = 100
<
VOUT 1 VPP
40
0.9V ≤ VG ≤ 2V, 0.2 dB
<
Att Range Flat Band (Relative to Max Gain)
Attenuation Range (Note 13)
0.2 dB Flatness, f 30 MHz
26
9.5
150
dB
<
0.1 dB Flatness, f 30 MHz
BW
Gain control Bandwidth
VG = 1V (Note 12)
MHz
Control
CT (dB)
Feed-through
VG = 0V, 30 MHz
(Output/Input)
−53
dB
dB
<
<
GR
Gain Adjustment Range
f
f
10 MHz
30 MHz
80
73
Time Domain Response
tr, tf
Rise and Fall Time
0.5V Step
2.1
20
ns
%
OS %
SR
Overshoot
Slew Rate (Note 5)
4V Step, Non Inverting
4V Step, Inverting
800
1500
V/µs
Distortion & Noise Performance
HD2
HD3
THD
En tot
IN
2nd Harmonic Distortion
3rd Harmonic Distortion
Total Harmonic Distortion
Total Equivalent Input Noise
Input Noise Current
2VPP, 20 MHz
−47
–55
−45
4.4
dBc
>
>
f
f
1 MHz, RSOURCE = 50Ω
nV/
pA/
1 MHz
2.6
DG
Differential Gain
f = 4.43 MHz, RL = 100Ω
0.45
0.13
%
DP
Differential Phase
deg
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2
Electrical Characteristics(Note 2) (Continued)
Unless otherwise specified, all limits guaranteed for TJ = 25˚C, VS
=
5V, AVMAX = 9.7 V/V, RF = 1kΩ, RG = 100Ω, VIN
=
0.1V, RL = 100Ω, VG = +2V. Boldface limits apply at the temperature extremes.
Min
Typ
Max
Symbol
Parameter
Conditions
(Note 6)
(Note 6)
(Note 6)
Units
DC & Miscellaneous Performance
GACCU
G Match
K
Gain Accuracy
VG = 2.0V
0
0.33
—
0.45
3.9
dB
dB
(See Application Note)
<
<
0.8V VG 2V
Gain Matching
VG = 2.0V
0.42
(See Application Note
<
<
0.8V VG 2V
—
+2.8/−4.2
1.01
Gain Multiplier
0.920
0.965
V/V
(See Application Notes)
Input Voltage Range
0.916
1.02
V
IN NL
IN L
RG Open
3.2
V
V
RG = 100Ω
0.48
0.40
4.8
0.68
I
RG Current
Pin 3
6.8
mA
RG_MAX
4.0
IBIAS
Bias Current
Pin 2 (Note 7)
−1.4
−3.5
µA
−3.7
TC IBIAS
RIN
Bias Current Drift
Input Resistance
Input Capacitance
VG Bias Current
Pin 2 (Note 8)
Pin 2
–190
7
pA/˚C
MΩ
pF
CIN
Pin 2
2.8
0.9
10
IVG
Pin 1, VG = 2V (Note 7)
Pin 1 (Note 8)
Pin 1
µA
TC IVG
VG Bias Drift
pA/˚C
MΩ
pF
R
VG Input Resistance
VG Input Capacitance
Output Voltage Range
25
VG
C
Pin 1
2.8
2.2
VG
VOUT
L
RL = 100Ω
2.0
1.7
V
VOUT NL
ROUT
RL = Open
DC
3.1
0.12
80
Output Impedance
Output Current
Ω
IOUT
VOUT
=
4V from Rails
60
mA
40
<
<
VO
Output Offset Voltage
0V VG 2V
10
–76
–88
11
55
mV
dB
OFFSET
70
+PSRR
−PSRR
IS
+Power Supply Rejection Ratio
(Note 9)
Input Referred, 1V change,
VG = 2.2V
–65
–65
−Power Supply Rejection Ratio
(Note 9)
Input Referred, 1V change,
VG = 2.2V
dB
Supply Current
No Load
8.5
15
mA
6.5
16
3
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Electrical Characteristics(Note 2) (Continued)
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics.
Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of
>
the device such that T = T . No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where T
T .
J
A
J
A
Note 3: The maximum output current (I
) is determined by device power dissipation limitations or value specified, whichever is lower.
OUT
Note 4: Human body model, 1.5 kΩ in series with 100 pF. Machine Model, 0Ω in series with 200 pF
Note 5: Slew rate is the average of the rising and falling slew rates.
Note 6: Typical values represent the most likely parametric norm. Bold numbers refer to over temperature limits.
Note 7: Positive current corresponds to current flowing into the device.
Note 8: Drift determined by dividing the change in parameter distribution at temperature extremes by the total temperature change.
+
−
Note 9: +PSRR definition: [|∆V
/∆V | / A ], −PSRR definition: [|∆V
/∆V | / A ] with 0.1V input voltage. ∆V
is the change in output voltage with offset shift
OUT
OUT
V
OUT
V
subtracted out.
Note 10: Gain/Phase normalized to low frequency value at 25˚C.
Note 11: Gain/Phase normalized to low frequency value at each setting.
Note 12: Gain control frequency response schematic:
20084316
Note 13: Flat Band Attenuation (Relative To Max Gain) Range Definition: Specified as the attenuation range from maximum which allows gain flatness specified
<
(either 0.2dB or 0.1dB), relative to A
gain. For example, for f 30 MHz, here are the Flat Band Attenuation ranges:
VMAX
0.2 dB: 19.7 dB down to -6.3 dB = 26 dB range
0.1 dB: 19.7 dB down to 10.2 dB = 9.5 dB range
Connection Diagram
8-Pin SOIC
20084301
Top View
Ordering Information
Package
Part Number
LMH6504MA
LMH6504MAX
LMH6504MM
LMH6504MMX
Package Marking
Transport Media
NSC Drawing
8-Pin SOIC
LMH6504MA
95 Units/Rail
M08A
2.5k Units Tape and Reel
1k Units Tape and Reel
3.5k Units Tape and Reel
8-Pin MSOP
A93A
MUA08A
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4
Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values.
Frequency Response Over Temperature Frequency Response for Various VG
20084303
20084304
Frequency Response (AVMAX = 2)
Inverting Frequency Response
20084344
20084346
Frequency Response for Various VG (AVMAX = 100)
(Large Signal)
Frequency Response for Various Amplitudes
20084364
20084345
5
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Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
Gain Control Frequency Response
IS vs. VS
20084333
20084321
IS vs. VS
Input Bias Current vs. VS
20084322
20084320
PSRR
AVMAX vs. Supply Voltage
20084334
20084323
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6
Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
Feed through Isolation for Various AVMAX
Gain Variation Over entire Temp Range vs. VG
20084341
20084312
IRG vs. VIN
Gain vs. VG
20084318
20084311
#
Gain vs. VG Including Limits
Output Offset Voltage vs. VG (Typical Unit 1)
20084363
20084325
7
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Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
#
#
Output Offset Voltage vs. VG (Typical Unit 2)
Output Offset Voltage vs. VG (Typical Unit 3)
20084330
20084328
Distribution of Output Offset Voltage
Output Noise Density vs. Frequency
20084308
20084361
Output Noise Density vs. Frequency
Output Noise Density vs. Frequency
20084337
20084338
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8
Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
Input Referred Noise Density vs. Frequency
Output Voltage vs. Output Current (Sinking)
20084365
20084336
Output Voltage vs. Output Current (Sourcing)
Distortion vs. Frequency
20084331
20084342
HD vs. POUT
THD vs. POUT
20084309
20084343
9
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Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
THD vs. POUT
THD vs. Gain
20084310
20084339
THD vs. Gain
Differential Gain & Phase
20084340
20084335
VG Bias Current vs. VG
Output Impedance
20084362
20084314
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10
Typical Performance Characteristics Unless otherwise specified: VS
=
5V, TA = 25˚C,
VG = VGMAX, RF = 1 kΩ, RG = 100Ω, VIN = 0.1V, input terminated in 50Ω. RL = 100Ω, Typical values. (Continued)
Step Response Plot
Step Response Plot
20084315
20084317
Gain vs. VG Step
20084332
11
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The amount of current which the input buffer can source/sink
into RG is limited and is specified in the IRG_MAX spec. This
sets the maximum input voltage:
Application Information
GENERAL DESCRIPTION
The key features of the LMH6504 are:
•
•
Low power
Broad voltage controlled gain and attenuation range
(From AVMAX down to complete cutoff)
Eq. 2
As the IRG_MAX limit is approached (with increasing input
voltage or with lowering of RG), the device harmonic distor-
tion will increase. Changes in RF will have a dramatic effect
on the small signal bandwidth. The output amplifier of the
LMH6504 is a current feedback amplifier (CFA) and its band-
width is determined by RF. As with any CFA, doubling the
feedback resistor will roughly cut the bandwidth of the device
in half. For more about CFA’s, see the basic tutorial, OA-20,
“Current Feedback Myths Debunked”, or a more rigorous
analysis, OA-13, “Current Feedback Amplifier Loop Gain
Analysis and Performance Enhancements”.
•
Bandwidth independent, resistor programmable gain
range (RG)
•
•
•
Broad signal and gain control bandwidths
Frequency response may be adjusted with RF
High impedance signal and gain control inputs
Refer to Figure 1 below. The LMH6504 combines a closed
loop input buffer (“X1” Block), a voltage controlled variable
gain cell (“MULT” Block) and an output amplifier (“CFA”
Block). The input buffer is a transconductance stage whose
gain is set by the gain setting resistor, RG. The output
amplifier is a current feedback op amp and is configured as
a transimpedance stage whose gain is set by, and is equal
to, the feedback resistor, RF. The maximum gain, AVMAX, of
the LMH6504 is defined by the ratio: K · RF / RG where “K” is
the gain multiplier with a nominal value of 0.965. As the gain
control input (VG) changes over its 0 to 2V range, the gain is
adjusted over a range of about 80 dB relative to the maxi-
mum set gain.
OTHER CONFIGURATIONS
1) Single Supply Operation
The LMH6504 can be configured for use in a single supply
environment. Doing so requires the following:
a) Bias pin 4 and RG to a “virtual half supply” somewhere
close to the middle of V+ and V- range. The other end of
RG is tied to pin 3. The “virtual half supply” needs to be
capable of sinking and sourcing the expected current flow
through RG.
b) Ensure that VG can be adjusted from 0V to 2V above the
“virtual half supply”.
c) Bias the input (pin 2) to make sure that it stays within the
range of 1.8V above V- to 1.8V below V+ (see “Input
voltage Range” specification in the Electrical Character-
istics table). This can be accomplished by either DC
biasing the input and AC coupling the input signal, or
alternatively, by direct coupling if the output of the driving
stage is also biased to half supply.
Arranged this way, the LMH6504 will respond to the current
flowing through RG. The gain control relationship will be
similar to the split supply arrangement with VG measured
referenced to pin 4. Keep in mind that the circuit described
above will also center the output voltage to the “virtual half
supply voltage”.
20084347
2) Arbitrarily Referenced Input Signal
FIGURE 1. LMH6504 Typical Application and Block
Diagram
Having a wide input voltage range on the input (pin 2)
(+/-3.2V typical), the LMH6504 can be configured to control
the gain on signals which are not referenced to ground (e.g.
Half Supply biased circuits, etc.). We will call this node the
“reference node”. In such cases, the other end of RG (the
side not tied to pin 3) can be tied to this reference node so
that RG will “look at” the difference between the signal and
this reference only. Keep in mind that the reference node
needs to source and sink the current flowing through RG.
SETTING THE LMH6504 MAXIMUM GAIN
Eq. 1
GAIN ACCURACY
Although the LMH6504 is specified at AVMAX = 9.7V/V, the
recommended AVMAX varies between 2 and 100. Higher
gains are possible but usually impractical due to output
offsets, noise and distortion. When varying AVMAX several
tradeoffs are made:
Gain accuracy is defined as the actual gain compared
against the theoretical gain at a certain VG (results ex-
pressed in dB) (See Figure 2).
Theoretical gain is given by:
RG: determines the input voltage range
RF: determines overall bandwidth
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12
GAIN PARTITIONING
Application Information (Continued)
If high levels of gain are needed, gain partitioning should be
considered:
Eq. 3
@
Where K = 0.965 (nominal) N = 0.96V & VC = 80mV room
temperature
For a VG range, the value specified in the tables represents
the worst case accuracy over the entire range. The "Typical"
value would be the worst case difference between the "Typi-
cal gain" and the "Theoretical gain". The "Max" value would
be the worst case difference between the actual gain and the
"Theoretical gain" for the entire population.
20084352
GAIN MATCHING
Gain matching as the limit on gain variation at a certain VG
(expressed in dB) (see Figure 2) and is specified as "Max"
only (no "Typical"). For a VG range, the value specified
represents the worst case matching over the entire range.
The "Max" value would be the worst case difference between
the actual gain and the typical gain for the entire population.
FIGURE 3. Gain Partitioning
The maximum gain range for this circuit is given by the
following equation:
Eq. 4
The LMH6624 is a low noise wideband voltage feedback
amplifier. Setting R2 at 909Ω and R1 at 100Ω produces a
gain of 20 dB. Setting RF at 1000Ω as recommended and RG
at 50Ω, produces a gain of about 26 dB in the LMH6504. The
total gain of this circuit is therefore approximately 46 dB. It is
important to understand that when partitioning to obtain high
levels of gain, very small signal levels will drive the amplifiers
to full scale output. For example, with 46 dB of gain, a 20 mV
signal at the input will drive the output of the LMH6624 to 200
mV, the output of the LMH6504 to 4V. Accordingly, the
designer must carefully consider the contributions of each
stage to the overall characteristics. Through gain partitioning
the designer is provided with an opportunity to optimize the
frequency response, noise, distortion, settling time, and
loading effects of each amplifier to achieve improved overall
performance.
LMH6504 GAIN CONTROL RANGE AND MINIMUM GAIN
20084351
Before discussing Gain Control Range, it is important to
understand the issues which limit it. The minimum gain of the
LMH6504, theoretically, is zero, but in practical circuits is
limited by the amount of feedthrough, here defined as the
gain when VG = 0V. Capacitive coupling through the board
and package as well as coupling through the supplies will
determine the amount of feedthrough. Even at DC, the input
signal will not be completely rejected. At high frequencies
feedthrough will get worse because of its capacitive nature.
At frequencies below 10 MHz, the feed through will be less
FIGURE 2. LMH6504 Gain Accuracy & Gain Matching
Defined
than −60 dB and therefore, it can be said that with AVMAX
20 dB, the gain control range is 80 dB.
=
13
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improvement comes about because in the non-inverting con-
figuration, the slew rate of the overall amplifier is limited by
the input buffer. In the inverting circuit, the input buffer re-
mains at a fixed voltage and does not affect slew rate.
Application Information (Continued)
LMH6504 GAIN CONTROL FUNCTION
In the plot, Gain vs. VG, we can see the gain as a function of
the control voltage. The “Gain (V/V)” plot, sometimes re-
ferred to as the S-curve, is the linear (V/V ) gain. This is a
hyperbolic tangent relationship and is given by Equation 3.
The “Gain (dB)” plots the gain in dB and is linear over a wide
range of gains. Because of this, the LMH6504 gain control is
referred to as “linear-in-dB.”
TRANSMISSION LINE MATCHING
One method for matching the characteristic impedance of a
transmission line is to place the appropriate resistor at the
input or output of the amplifier. Figure 5 shows a typical
circuit configuration for matching transmission lines.
For applications where the LMH6504 will be used at the
heart of a closed loop AGC circuit, the S-curve control char-
acteristic provides a broad linear (in dB) control range with
soft limiting at the highest gains where large changes in
control voltage result in small changes in gain. For applica-
tions requiring a fully linear (in dB) control characteristic, use
the LMH6504 at half gain and below (VG ≤ 1V).
AVOIDING OVERDRIVE OF THE LMH6504 GAIN
CONTROL INPUT
20084356
There is an additional requirement for the LMH6504 Gain
Control Input (VG): VG must not exceed +2.3V (with 5V
supplies). The gain control circuitry may saturate and the
gain may actually be reduced. In applications where VG is
being driven from a DAC, this can easily be addressed in the
software. If there is a linear loop driving VG, such as an AGC
loop, other methods of limiting the input voltage should be
implemented. One simple solution is to place a 2.2:1 resis-
tive divider on the VG input. If the device driving this divider
is operating off of 5V supplies as well, its output will not
exceed 5V and through the divider VG can not exceed 2.3V.
FIGURE 5. TRANSMISSION LINE MATCHING
The resistors RS, RI, RO, and RT are equal to the character-
istic impedance, ZO, of the transmission line or cable. Use
CO to match the output transmission line over a greater
frequency range. It compensates for the increase of the op
amp’s output impedance with frequency.
MINIMIZING PARASITIC EFFECTS ON SMALL SIGNAL
BANDWIDTH
The best way to minimize parasitic effects is to use surface
mount components and to minimize lead lengths and com-
ponent distance from the LMH6504. For designs utilizing
through-hole components, specifically axial resistors, resis-
tor self-capacitance should be considered. Example: the
average magnitude of parasitic capacitance of RN55D 1%
metal film resistors is about 0.15 pF with variations of as
much as 0.1 pF between lots. Given the LMH6504’s ex-
tended bandwidth, these small parasitic reactance variations
can cause measurable frequency response variations in the
highest octave. We therefore recommend the use of surface
mount resistors to minimize these parasitic reactance ef-
fects.
IMPROVING THE LMH6504 LARGE SIGNAL
PERFORMANCE
Figure
4
illustrates an inverting gain scheme for the
LMH6504.
RECOMMENDATIONS
Here are some recommendations to avoid problems and to
get the best performance:
•
Do not place a capacitor across RF. However, an appro-
priately chosen series RC combination could be used to
shape the frequency response.
20084354
•
•
Keep traces connecting RF separated and as short as
possible
FIGURE 4. Inverting Amplifier
Place a small resistor (20-50Ω) between the output and
CL
The input signal is applied through the RG resistor. The VIN
pin should be grounded through a 25Ω resistor. The maxi-
mum gain range of this configuration is given in the following
equation:
•
•
Cut away the ground plane, if any, under RG
Keep decoupling capacitors as close as possible to the
LMH6504.
•
Connect pin 2 through a minimum resistance of 25Ω.
ADJUSTING OFFSETS AND DC LEVEL SHIFTING
Offsets can be broken into two parts: an input-referred term
and an output-referred term. These errors can be trimmed
using the circuit in Figure 6. First set VG to 0V and adjust the
Eq. 5
The inverting slew rate of the LMH6504 is much higher than
that of the non-inverting slew rate. This 2X performance
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14
Application Information (Continued)
USING THE LMH6504 IN AGC APPLICATIONS
trim pot R4 to null the offset voltage at the output. This will
eliminate the output stage offsets. Next set VG to 2V and
adjust the trim pot R1 to null the offset voltage at the output.
This will eliminate the input stage offsets.
In AGC applications, the control loop forces the LMH6504 to
have a fixed output amplitude. The input amplitude will vary
over a wide range and this can be the issue that limits
dynamic range. At high input amplitudes, the distortion due
to the input buffer driving RG may exceed that which is
produced by the output amplifier driving the load. In the plot,
Distortion vs. Gain, total harmonic distortion (THD) is plotted
over a gain range of nearly 35 dB for a fixed output amplitude
of 0.25 VPP in the specified configuration, RF = 1k, RG
=
100Ω. When the gain is adjusted to -15 dB (i.e. 35 dB down
from AVMAX), the input amplitude would be 1.41 VPP and we
can see the distortion is at its worst at this gain. If the output
amplitude of the AGC were to be raised above 0.25 VPP, the
input amplitudes for gains 40 dB down from AVMAX would be
even higher and the distortion would degrade further. It is for
this reason that we recommend lower output amplitudes if
wide gain ranges are desired. Using a post-amp like the
LMH6714/ 6720/ 6722 family or LMH6702 would be the best
way to preserve dynamic range and yield output amplitudes
much higher than 100 mVPP. Another way of addressing
distortion performance and its limitations on dynamic range,
would be to raise the value of RG. Just like any other high-
speed amplifier, by increasing the load resistance, and
therefore decreasing the demanded load current, the distor-
tion performance will be improved in most cases. With an
increased RG, RF will also have to be increased to keep the
same AVMAX and this will decrease the overall bandwidth. It
may be possible to insert a series RC combination across RF
in order to counteract the negative effect on BW when a
large RF is used.
20084357
FIGURE 6. OFFSET ADJUST CIRCUIT
DIGITAL GAIN CONTROL
Digitally variable gain control can be easily realized by driv-
ing the LMH6504’s gain control input with a digital-to-analog
converter (DAC). Figure 7 illustrates such an application.
This circuit employs National Semiconductor’s eight-bit
DAC0830, the LMC8101 MOS input op-amp (Rail-to-Rail
Input/Output), and the LMH6504 VGA. With VREF set to 2V,
the circuit provides up to 80 dB of gain control in 256 steps
with up to 0.05% full scale resolution. The maximum gain of
this circuit is 20 dB.
AUTOMATIC GAIN CONTROL (AGC) #1
Fast Response AGC Loop
The AGC circuit shown in Figure 8 will correct a 6 dB input
amplitude step in 100 ns. The circuit includes a two op-amp
precision rectifier amplitude detector (U1 and U2), and an
integrator (U3) to provide high loop gain at low frequencies.
The output amplitude is set by R9. Some notes on building
fast AGC loops: Precision rectifiers work best with large
output signals. Accuracy is improved by blocking DC offsets,
as shown in Figure 8.
20084358
FIGURE 7. Digital Gain Control
15
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Application Information (Continued)
20084359
FIGURE 8. Automatic Gain Control Circuit #1
Signal frequencies must not reach the gain control port of the
LMH6504, or the output signal will be distorted (modulated
by itself). A fast settling AGC needs additional filtering be-
yond the integrator stage to block signal frequencies. This is
provided in Figure 8 by a simple R-C filter (R10 and C3);
better distortion performance can be achieved with a more
complex filter. These filters should be scaled with the input
signal frequency. Loops with slower response time (longer
integration time constants) may not need the R10 – C3 filter.
U2 is configured to provide negative feedback. U2 generates
a rectified gain control signal that works against an adjust-
able bias level which may be set by the potentiometer and
RB. CI integrates the bias and negative feedback. The result-
ant gain control signal is applied to the U1 gain control input
VG. The bias adjustment allows the U1 output to be set at an
arbitrary level less than the maximum output specification of
the amplifier. Rectification is accomplished in U2 by driving
both the amplifier input and the gain control input with the U1
output signal. The voltage divider that is formed by R1 and
R2, sets the rectifier gain.
Checking the loop stability can be done by monitoring the VG
voltage while applying a step change in input signal ampli-
tude. Changing the input signal amplitude can be easily
done with an arbitrary waveform generator.
AUTOMATIC GAIN CONTROL (AGC) #2
Figure 9 illustrates an automatic gain control circuit that
employs two LMH6504’s. In this circuit, U1 receives the input
signal and produces an output signal of constant amplitude.
www.national.com
16
Application Information (Continued)
20084360
FIGURE 9. Automatic Gain Control Circuit #2
CIRCUIT LAYOUT CONSIDERATIONS & EVALUATION
BOARD
the output (e.g. 100Ω and 39 pF in series tied between the
LMH6504 output and ground). CL can also be isolated from
the output by placing a small resistor in series with the output
(pin 6).
A good high frequency PCB layout including ground plane
construction and power supply bypassing close to the pack-
age are critical to achieving full performance. The amplifier is
sensitive to stray capacitance to ground at the I- input (pin 7);
keep node trace area small. Shunt capacitance across the
feedback resistor should not be used to compensate for this
effect. Capacitance to ground should be minimized by re-
moving the ground plane from under the body of RG. Para-
sitic or load capacitance directly on the output (pin 6) de-
grades phase margin leading to frequency response
peaking.
Component parasitics also influence high frequency results.
Therefore it is recommended to use metal film resistors such
as RN55D or leadless components such as surface mount
devices. High profile sockets are not recommended.
National Semiconductor suggests the following evaluation
board as a guide for high frequency layout and as an aid in
device testing and characterization:
Device
Package
Evaluation Board
Part Number
CLC730066
The LMH6504 is fully stable when driving a 100Ω load. With
reduced load (e.g. 1k.) there is a possibility of instability at
very high frequencies beyond 400 MHz especially with a
capacitive load. When the LMH6504 is connected to a light
load as such, it is recommended to add a snubber network to
LMH6504
SOIC
The evaluation board is shipped when a device sample
request is placed with National Semiconductor.
17
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Physical Dimensions inches (millimeters) unless otherwise noted
8-Pin SOIC
NS Package Number M08A
8-Pin MSOP
NS Package Number MUA08A
www.national.com
18
Notes
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National Semiconductor certifies that the products and packing materials meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification
(CSP-9-111S2) and contain no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
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Support Center
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Fax: +49 (0) 180-530 85 86
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Fax: 81-3-5639-7507
Email: new.feedback@nsc.com
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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