LMH0303SQ [NSC]
IC LINE DRIVER, QCC16, LLP-16, Line Driver or Receiver;
| 型号： | LMH0303SQ |
| 厂家： | 
National Semiconductor |
| 描述： | IC LINE DRIVER, QCC16, LLP-16, Line Driver or Receiver 驱动 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
August 7, 2008
LMH0303
3 Gbps HD/SD SDI Cable Driver with Cable Detect
General Description
Features
■
The LMH0303 3 Gbps HD/SD SDI Cable Driver with Cable
Detect is designed for use in SMPTE 424M, SMPTE 292M,
SMPTE 344M, and SMPTE 259M serial digital video appli-
cations. The LMH0303 drives 75Ω transmission lines (Belden
1694A, Belden 8281, or equivalent) at data rates up to 2.97
Gbps.
SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M compliant
Data rates to 2.97 Gbps
■
■
■
■
■
■
Supports DVB-ASI at 270 Mbps
Cable detect on output
Loss of signal detect at input
Output driver power down control
The LMH0303 includes intelligent sensing capabilities to im-
prove system diagnostics. The cable detect feature senses
near-end termination to determine if a cable is correctly at-
tached to the output BNC. Input loss of signal (LOS) detects
the presence of a valid signal at the input of the cable driver.
These sensing features may be used to alert the user of a
system fault and activate a deep power save mode, reducing
the cable driver's power consumption to 3 mW. These fea-
tures are accessible via an SMBus interface.
Typical power consumption: 130 mW in SD mode and
155 mW in HD mode
Power save mode typical power consumption: 4 mW
Single 3.3V supply operation
■
■
■
■
■
■
■
■
Differential input
75Ω differential output
Selectable slew rate
The LMH0303 provides two selectable slew rates for SMPTE
259M and SMPTE 424M / 292M compliance. The output am-
plitude is adjustable ±10% in 5 mV steps via the SMBus.
Industrial temperature range: −40°C to +85°C
16–pin LLP package
The LMH0303 is powered from a single 3.3V supply. Power
consumption is typically 130 mW in SD mode and 155 mW in
HD mode. The LMH0303 is available in a 16-pin LLP pack-
age.
Footprint compatible with the LMH0302
Applications
SMPTE 424M, SMPTE 292M, SMPTE 344M, and SMPTE
259M serial digital interfaces
■
The LMH0303 interfaces with National's LMH0356 for addi-
tional system control and power consumption savings (see
Typical Application).
Digital video routers and switches
■
■
Distribution amplifiers
Typical Application
30043203
© 2008 National Semiconductor Corporation
300432
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ESD Rating (HBM)
ESD Rating (MM)
ESD Rating (CDM)
8 kV
400V
2 kV
Absolute Maximum Ratings (Note 1)
Supply Voltage:
−0.5V to 3.6V
Input Voltage (all inputs)
Output Current
Storage Temperature Range
Junction Temperature
Lead Temperature
(Soldering 4 Sec)
−0.3V to VCC+0.3V
28 mA
−65°C to +150°C
+125°C
Recommended Operating
Conditions
Supply Voltage (VCC – VEE):
3.3V ±5%
Operating Free Air Temperature (TA)
+260°C
−40°C to +85°C
Package Thermal Resistance
ꢀθJA 16-pin LLP
ꢀθJC 16-pin LLP
+43°C/W
+7°C/W
DC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Notes 2, 3).
Symbol Parameter
VCMIN Input Common Mode Voltage
Conditions
Reference
Min
Typ
Max
Units
V
SDI, SDI
VCC –
1.6 +
VSDI/2
VSDI/2
VSDI
Input Voltage Swing
Differential
mVP−P
V
100
2200
VCMOUT Output Common Mode Voltage
SDO, SDO
VCC –
VSDO
VSDO
Output Voltage Swing
Single-ended, 75Ω load,
RREF = 750Ω 1%
mVP-P
720
2.0
800
880
VIH
VIL
ICC
Input Voltage High Level
InputVoltage Low Level
Supply Current
SD/HD,
ENABLE
V
V
0.8
57
SD/HD = 0,
SDO/SDO enabled
47
mA
SD/HD = 1,
SDO/SDO enabled
40
47
mA
mA
SDO/SDO disabled
1.3
2.5
SMBus DC Specifications
VSIL
VSIH
Data, Clock Input Low Voltage
0.8
V
V
VSDD
Data, Clock Input High Voltage
2.1
4
Current through pullup resistor or
current source
ISPULLUP
VOL = 0.4 V
mA
VSDD
Nominal Bus Voltage
3.0
−200
−10
3.6
200
10
V
ISLEAKB
ISLEAKP
CSI
Input Leakage per bus segment (Note 6)
Input Leakage per pin
µA
µA
pF
Capacitance for SDA and SCL
(Notes 6, 7)
10
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2
AC Electrical Characteristics
Over Supply Voltage and Operating Temperature ranges, unless otherwise specified (Note 3).
Symbol Parameter
Conditions
Reference
SDI, SDI
Min
Typ
Max
Units
Mbps
psP-P
psP-P
psP-P
ps
DRSDI
tjit
Input Data Rate
2970
Additive Jitter
2.97 Gbps
SDO, SDO
20
18
15
90
1.485 Gbps
270 Mbps
tr,tf
Output Rise Time, Fall Time
SD/HD = 0, 20% – 80%,
SD/HD = 1, 20% – 80%
130
800
30
400
ps
Mismatch in Rise/Fall Time
Duty Cycle Distortion
ps
SD/HD = 0, 2.97 Gbps,
(Note 4)
27
30
ps
ps
SD/HD = 0, 1.485 Gbps,
(Note 4)
SD/HD = 1, (Note 4)
100
10
8
ps
%
tOS
Output Overshoot
Output Return Loss
SD/HD = 0, (Note 4)
SD/HD = 1, (Note 4)
%
RLSDO
5 MHz - 1.5 GHz, (Note 5)
1.5 GHz - 3.0 GHz, (Note 5)
15
10
dB
dB
SMBus AC Specifications
fSMB Bus Operating Frequency
tBUF
10
100
kHz
µs
Bus free time between Stop and
Start Condition
4.7
tHD:STA
Hold time after (repeated) Start
Condition. After this period, the
first clock is generated.
At ISPULLUP = MAX
4.0
4.7
µs
µs
tSU:STA
Repeated Start Condition setup
time
tSU:STO
tHD:DAT
tSU:DAT
tLOW
tHIGH
tF
Stop Condition setup time
Data hold time
4.0
300
250
4.7
µs
ns
ns
µs
µs
ns
ns
Data setup time
Clock low period
Clock high period
Clock/Data Fall Time
Clock/Data Rise Time
4.0
50
300
tR
1000
tPOR
Time in which device must be
operational after power on
500
ms
Note 1: "Absolute Maximum Ratings" are those parameter values beyond which the life and operation of the device cannot be guaranteed. The stating herein of
these maximums shall not be construed to imply that the device can or should be operated at or beyond these values. The table of "Electrical Characteristics"
specifies acceptable device operating conditions.
Note 2: Current flow into device pins is defined as positive. Current flow out of device pins is defined as negative. All voltages are stated referenced to
VEE = 0 Volts.
Note 3: Typical values are stated for VCC = +3.3V and TA = +25°C.
Note 4: Specification is guaranteed by characterization.
Note 5: Output return loss is dependent on board design. The LMH0303 meets this specification on the SD303 evaluation board.
Note 6: Recommended value — Parameter not tested.
Note 7: Recommended maximum capacitive load per bus segment is 400 pF.
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Timing Diagram
30043206
SMBus Timing Parameters
Connection Diagram
30043205
The exposed die attach pad is a negative electrical terminal for this device. It should be connected to the negative power supply voltage.
16-Pin LLP
Order Number LMH0303SQ
See NS Package Number SQB16A
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4
Pin Descriptions
Pin
1
Name
Description
SDI
SDI
VEE
RREF
Serial data true input.
2
Serial data complement input.
Negative power supply (ground).
3
4
Bias resistor. Connect a 750Ω resistor to VCC
.
5
RSTI
Reset input.
H = Normal operation.
L = Device reset. The device operates with default register settings. Forcing RSTI low also forces
RSTO low.
6
7
ENABLE
SDA
Output driver enable (with internal pullup).
H = Normal operation.
L = Output driver powered off.
SMBus bidirectional data pin. When functioning as an output, it is open drain. This pin requires an
external pullup.
8
9
SCL
SMBus clock input. SCL is input only. This pin requires an external pullup.
Positive power supply (+3.3V).
VCC
10
SD/HD
Output slew rate control.
H = Output rise/fall time complies with SMPTE 259M.
L = Output rise/fall time complies with SMPTE 424M / 292M.
11
12
13
SDO
Serial data complement output.
Serial data true output.
SDO
FAULT
Fault open drain output flag. Requires external pullup resistor and may be wire ORed with multiple
cable drivers.
H = Normal operation.
L = Loss of signal or termination fault for any output.
14
15
16
NC
No connect. Not bonded internally.
No connect. Not bonded internally.
NC
RSTO
Reset output. RSTO is automatically set to 1 when register 0 is written. It can be reset back to zero
by forcing RSTI to zero to reset the device. Used to daisy chain multiple cable drivers on the same
SMBus.
DAP
VEE
Connect exposed DAP to negative power supply (ground).
5
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Device Operation
SMBus Interface
The System Management Bus (SMBus) is a two-wire inter-
face designed for the communication between various sys-
tem component chips. By accessing the control functions of
the circuit via the SMBus, pincount is kept to a minimum while
allowing a maximum amount of versatility. The LMH0303 has
several internal configuration registers which may be ac-
cessed via the SMBus.
INPUT INTERFACING
The LMH0303 accepts either differential or single-ended in-
put. For single-ended operation, the unused input must be
properly terminated.
OUTPUT INTERFACING
The LMH0303 uses current mode outputs. Single-ended out-
put levels are 800 mVP-P into 75Ω AC-coupled coaxial cable
with an RREF resistor of 750Ω. The RREF resistor is connected
between the RREF pin and VCC. The only resistor value that
should be used for RREF is 750Ω.
The RREF resistor should be placed as close as possible to
the RREF pin. In addition, the copper in the plane layers below
the RREF network should be removed to minimize parasitic
capacitance.
The 7-bit default address for the LMH0303 is 17h. The LSB
is set to 0b for a WRITE and 1b for a READ, so the 8-bit default
address for a WRITE is 2Eh and the 8-bit default address for
a READ is 2Fh. The SMBus address may be dynamically
changed.
In applications where there might be several LMH0303s, the
SDA, SCL, and FAULT pins can be shared. The SCL, SDA,
and FAULT pins are open drain and require external pullup
resistors. Multiple LMH0303s may have the FAULT pin wire
ORed. This signal becomes active when either loss of signal
is detected or any termination faults are detected. The regis-
ters may be read in order to determine the cause. Additionally,
each signal can be masked from the FAULT pin.
OUTPUT SLEW RATE CONTROL
The LMH0303 output rise and fall times are selectable for ei-
ther SMPTE 259M or SMPTE 424M / 292M compliance via
the SD/HD pin. For slower rise and fall times, or SMPTE 259M
compliance, SD/HD is set high. For faster rise and fall times,
or SMPTE 424M and SMPTE 292M compliance, SD/HD is
set low. SD/HD may also be controlled using the SMBus, pro-
vided the SD/HD pin is held low.
TRANSFER OF DATA VIA THE SMBus
During normal operation the data on SDA must be stable dur-
ing the time when SCL is High.
There are three unique states for the SMBus:
START: A High-to-Low transition on SDA while SCL is High
indicates a message START condition.
OUTPUT ENABLE
The SDO/SDO output driver can be enabled or disabled with
the ENABLE pin. When set low, the output driver is powered
off and the LMH0303 enters a deep power save mode. EN-
ABLE has an internal pullup.
STOP: A Low-to-High transition on SDA while SCL is High
indicates a message STOP condition.
IDLE: If SCL and SDA are both High for a time exceeding
tBUF from the last detected STOP condition or if they are High
for a total exceeding the maximum specification for tHIGH then
the bus will transfer to the IDLE state.
INPUT LOS OF SIGNAL DETECTION (LOS)
The LMH0303 detects when the input signal does not have a
video-like pattern. Self oscillation and low levels of noise are
rejected. This loss of signal detect allows a very sensitive in-
put stage that is robust against coupled noise without any
degradation of jitter performance.
SMBus TRANSACTIONS
The device supports WRITE and READ transactions. See
Register Description table for register address, type (Read/
Write, Read Only), default value and function information.
Via the SMBus, the loss of signal detect can either add an
input offset or mute the outputs. An offset is added by default.
Additionally, the loss of signal detect can be linked to the EN-
ABLE functionality so that when the LOS goes low, ENABLE
will also go low.
WRITING A REGISTER
To write a register, the following protocol is used (see SMBus
2.0 specification).
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
OUTPUT CABLE DETECTION
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives the 8-bit data byte.
6. The Device drives an ACK bit (“0”).
7. The Host drives a STOP condition.
The LMH0303 detects when an output is locally terminated.
When a video signal (or AC test signal) is present on SDI, the
device senses the SDO and SDO amplitudes. If the output is
not properly terminated (via a terminated cable or local ter-
mination), the amplitude will be higher than expected, and the
Termination Fault signal is asserted. The Termination Fault
signal is de-asserted when the proper termination is applied.
This feature allows the system designer the flexibility to react
to cable attachment and removal. Note that a long length of
cable will look like a proper termination at the device output.
The WRITE transaction is completed, the bus goes IDLE and
communication with other SMBus devices may now occur.
READING A REGISTER
To read a register, the following protocol is used (see SMBus
2.0 specification).
The cable driver must be enabled for the termination detection
to operate. If the Termination Fault will be used to power down
the LMH0303, then periodic polling (enabling) is recommend-
ed to monitor the output termination. For example, when a
Fault condition is triggered, ENABLE can be driven low to
power down the device. The LMH0303 should be re-enabled
periodically to check the status of the output termination. The
LMH0303 needs to be powered on for roughly 4 ms for Ter-
mination Fault detection to work.
1. The Host drives a START condition, the 7-bit SMBus
address, and a “0” indicating a WRITE.
2. The Device (Slave) drives the ACK bit (“0”).
3. The Host drives the 8-bit Register Address.
4. The Device drives an ACK bit (“0”).
5. The Host drives a START condition.
6. The Host drives the 7-bit SMBus Address, and a “1”
indicating a READ.
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7. The Device drives an ACK bit “0”.
Application Information
Figure 1 shows the application circuit for the LMH0303.
8. The Device drives the 8-bit data value (register contents).
9. The Host drives a NACK bit “1”indicating end of the
READ transfer.
10. The Host drives a STOP condition.
30043202
FIGURE 1. Application Circuit
COMMUNICATING WITH MULTIPLE LMH0303 CABLE
DRIVERS VIA THE SMBus
device. This signal acts as a “Enable / Reset” signal. Addi-
tional LMH0303s are controlled from the upstream device. In
this control scheme, multiple LMH0303s may be controlled
via the two-wire SMBus and the use of one GPO (General
Purpose Output) signal. Other SMBus devices may also be
connected to the two wires, assuming they have their own
unique SMBus addresses.
A common application for the LMH0303 will utilize multiple
cable driver devices. Even though the LMH0303 devices all
have the same default SMBus device ID (address), it is still
possible for them share the SMBus signals as shown in
Figure 2. A third signal is required from the host to the first
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30043207
FIGURE 2. SMBus Configuration for Multiple LMH0303 Cable Drivers
The RSTI pin of the first device is controlled by the system
with a GPO pin from the host. The first LMH0303 RSTO pin
is then daisy chained to the next device's RSTI pin. That
device’s RSTO pin is connected to the next device and so on.
the next LMH0303 in the chain will now respond to the
default address of 8’h2E (7’h17).
5. The process is repeated until all LMH0303 devices have
a unique address loaded.
The procedure at initialization is to:
6. Direct SMBus writes and reads may now take place
between the host and any addressed device.
1. Hold the host GPO pin Low in RESET, to the first device.
RSTO output default is also Low which holds the next
device in RESET in the chain.
The 7-bit address field allows for 128 unique addresses. The
above procedure allows for the reprogramming of the
LMH0303 devices such that multiple devices may share the
two-wire SMBus. Make sure all devices on the bus have
unique device IDs.
2. Raise the host GPO signal to LMH0303 #1 RSTI input
pin.
3. Write to Address 8’h2E (7’h17) Register 0 with the new
address value (e.g. 8’h2C (7’h16).
If power is toggled to the system, the SMBus address routine
needs to be repeated.
4. Upon writing Register 0 in LMH0303 #1, its RSTO signal
will switch High. Its new address is 8’h2C (7’h16), and
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SMBus Registers
TABLE 1. SMBus Registers
Default Description
Address R/W Name
Bits Field
00h
01h
R/W ID
7:1 DEVID
0010111 Device ID. Writing this register will force the RSTO pin high.
Further accesses to the device must use this 7-bit address.
Reserved as 0. Always write 0 to this bit.
0
RSVD
0
R
STATUS
7:3 RSVD
00000 Reserved.
2
1
0
7
TFN
TFP
LOS
SD
0
0
0
0
Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Termination Fault for SDI.
0: No Termination Fault Detected.
1: Termination Fault Detected.
Loss Of Signal (LOS) detect at input.
0: No Signal Detected.
1: Signal Detected.
02h
R/W MASK
SD Rate select bit. If the SD/HD pin is set to VCC, it overrides
this bit. With the SD/HD pin set to ground, this pin selects
the output edge rate as follows:
0: HD edge rate.
1: SD edge rate.
6
5
RSVD
PD
0
0
Reserved as 0. Always write 0 to this bit.
Power Down for SDO output stage. If the ENABLE pin is set
to ground, it overrides this bit. With the ENABLE pin set to
VCC, PD functions as follows:
0: SDO active.
1: SDO powered down.
4:3 RSVD
00
0
Reserved as 00. Always write 00 to these bits.
2
1
0
MTFN
MTFP
MLOS
Mask TFN from affecting FAULT pin.
0: TFN=1 will cause FAULT to be 0.
1: TFN=1 will not affect FAULT; the condition is masked off.
0
0
Mask TFP from affecting FAULT pin.
0: TFP=1 will cause FAULT to be 0.
1: TFP=1 will not affect FAULT; the condition is masked off.
Mask LOS from affecting FAULT pin.
0: LOS=0 will cause FAULT to be 0.
1: LOS=0 will not affect FAULT; the condition is masked off.
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Address R/W Name
03h R/W DIRECTION
Bits Field
Default Description
7
HDTFThreshLSB
1
Least Significant Bit for HDTFThresh detection threshold.
Combines with HDTFThresh bits in register 04h.
6
SDTFThreshLSB
1
Least Significant Bit for SDTFThresh detection threshold.
Combines with SDTFThresh bits in register 05h.
5:3 RSVD
000
0
Reserved as 000. Always write 000 to these bits.
2
1
0
DTFN
DTFP
DLOS
Direction of TFN that affects FAULT pin (when not masked).
0: TFN=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TFN=0 will cause FAULT to be 0 (when the condition is
not masked off).
0
0
Direction of TFP that affects FAULT pin (when not masked).
0: TFP=1 will cause FAULT to be 0 (when the condition is
not masked off).
1: TFP=0 will cause FAULT to be 0 (when the condition is
not masked off).
Direction of LOS that affects FAULT pin (when not masked).
0: LOS=0 will cause FAULT to be 0 (when the condition is
not masked off).
1: LOS=1 will cause FAULT to be 0 (when the condition is
not masked off).
04h
R/W OUTPUT
7:5 HDTFThresh
4:0 AMP
100
Sets the Termination Fault threshold for SDO, when SD is
set to HD rates (0). Combines with HDTFThreshLSB in
register 03h (default for combined value is 1001).
10000 SDO output amplitude in roughly 5 mV steps.
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Address R/W Name
Bits Field
Default Description
05h
R/W OUTPUTCTRL
7
6
RSVD
0
0
Reserved as 0. Always write 0 to this bit.
FLOSOF
Force LOS to always OFF in regard to its effect on the output
signal. This forces the device into either the mute or “add
offset” state. The LOS bit in register 01h still reflects the
correct state of LOS.
0: LOS operates normally, muting or adding offset as
specified by the MUTE bit.
1: Muting or adding offset is always in place as specified by
the MUTE bit.
5
4
FLOSON
0
0
Force LOS to always ON in regard to its effect on the output
signal. This prevents the device from muting or adding
offset. The LOS bit in register 01h still reflects the correct
state of LOS.
0: LOS operates normally, muting or adding offset as
specified in the MUTE bit.
1: Muting or adding offset never occurs.
LOSEN
Configures LOS to be combined with the ENABLE
functionality.
0: Only the PD bit and ENABLE pin affect the power down
state of the output drivers.
1: If the ENABLE pin is set to ground, it powers down the
output drivers regardless of the state of LOS or the PD bit.
With the ENABLE pin set to VCC, LOS=0 will power down
the output drivers, and LOS=1 will leave the power down
state dependent on the PD bit.
3
MUTE
0
Selects whether the device will MUTE when loss of signal
is detected or add an offset to prevent self oscillation. When
an input signal is detected (LOS=1), the device will operate
normally.
0: Loss of signal will force a small offset to prevent self
oscillation.
1: Loss of signal will force the channel to MUTE.
2:0 SDTFThresh
010
Sets the Termination Fault threshold for SDO, when SD is
set to SD rates (1). Combines with SDTFThreshLSB in
register 03h (default for combined value is 0101).
06h
07h
08h
R/W RSVD
R/W RSVD
R/W TEST
7:0 RSVD
00000000 Reserved as 00000000. Always write 00000000 to these
bits.
7:0 RSVD
00000000 Reserved as 00000000. Always write 00000000 to these
bits.
7:5 CMPCMD
000
Compare command. Determines whether the peak value or
the current value of the Termination Fault counters is read
in registers 0Ah and 0Bh.
000: Resets compare value to 00; registers 0Ah and 0Bh
show current counter values. Sets detection to look for MAX
peak values.
001: Capture counter 0. Register 0Ah shows peak value.
010: Capture counter 1. Register 0Bh shows peak value.
011, 100: Reserved.
101: Resets compare value to 1Fh. Sets detection to look
for MIN peak values.
110, 111: Reserved.
4:0 RSVD
00000 Reserved as 00000. Always write 00000 to these bits.
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Address R/W Name
Bits Field
7:5 RSVD
4:3 DIREV
2:0 PARTID
Default Description
09h
R
REV
000
10
Reserved.
Die Revision.
011
Part Identifier. Note that single output devices (LMH0303)
have the LSB=1. Dual output devices (LMH0307) have the
LSB=0.
0Ah
0Bh
R
R
TFPCOUNT
TFNCOUNT
7:5 RSVD
000
Reserved.
4:0 TFPCOUNT
00000 This is either the current value of TFP Counter, or the peak
value of the counter, depending on CMPCMD in register
08h.
7:5 RSVD
000
Reserved.
4:0 TFNCOUNT
00000 This is either the current value of TFN Counter, or the peak
value of the counter, depending on CMPCMD in register
08h.
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Physical Dimensions inches (millimeters) unless otherwise noted
16-Pin LLP
Order Number LMH0303SQ
NS Package Number SQB16A
13
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