LM5111-2M [NSC]
Dual 5A Compound Gate Driver; 双通道5A复合门驱动器
| 型号： | LM5111-2M |
| 厂家： | 
National Semiconductor |
| 描述： | Dual 5A Compound Gate Driver |
| 文件： | 总10页 (文件大小：204K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
July 2004
LM5111
Dual 5A Compound Gate Driver
n Independent inputs (TTL compatible)
n Fast propagation times (25 ns typical)
n Fast rise and fall times (14 ns/12 ns rise/fall with 2 nF
load)
n Available in dual non-inverting, dual inverting and
combination configurations
n Supply rail under-voltage lockout protection
n Pin compatible with industry standard gate drivers
General Description
The LM5111 Dual Gate Driver replaces industry standard
gate drivers with improved peak output current and effi-
ciency. Each “compound” output driver stage includes MOS
and bipolar transistors operating in parallel that together sink
more than 5A peak from capacitive loads. Combining the
unique characteristics of MOS and bipolar devices reduces
drive current variation with voltage and temperature. Under-
voltage lockout protection is also provided. The drivers can
be operated in parallel with inputs and outputs connected to
double the drive current capability. This device is available in
the SOIC-8 package.
Typical Applications
n Synchronous Rectifier Gate Drivers
n Switch-mode Power Supply Gate Driver
n Solenoid and Motor Drivers
Features
n Independently drives two N-Channel MOSFETs
n Compound CMOS and bipolar outputs reduce output
current variation
Package
n SOIC-8
n 5A sink/3A source current capability
n Two channels can be connected in parallel to double the
drive current
Pin Configurations
20112301
SOIC-8
© 2004 National Semiconductor Corporation
DS201123
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Ordering Information
Order Number
Package Type
NSC Package Drawing
Supplied As
Shipped in anti-static units, 95
Units/Rail
LM5111-1M
SOIC-8
M08A
LM5111-1MX
LM5111-2M
SOIC-8
SOIC-8
M08A
M08A
2500 shipped in Tape & Reel
Shipped in anti-static units, 95
Units/Rail
LM5111-2MX
LM5111-3M
SOIC-8
SOIC-8
M08A
M08A
2500 shipped in Tape & Reel
Shipped in anti-static units, 95
Units/Rail
LM5111-3MX
SOIC-8
M08A
2500 shipped in Tape & Reel
Block Diagram
20112303
Block Diagram of LM5111
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2
Pin Description
Pin
1
Name
NC
Description
No Connect
Application Information
TTL compatible thresholds.
2
IN_A
VEE
‘A’ side control input
3
Ground reference for both inputs
and outputs
Connect to power ground.
4
5
IN_B
‘B’ side control input
TTL compatible thresholds.
OUT_B
Output for the ‘B’ side driver.
Voltage swing of this output is from VCC to VEE.
The output stage is capable of sourcing 3A and
sinking 5A.
6
7
VCC
Positive output supply
Locally decouple to VEE.
OUT_A.
Output for the ‘A’ side driver.
Voltage swing of this output is from VCC to VEE
The output stage is capable of sourcing 3A and
sinking 5A.
.
8
NC
No Connect
Configuration Table
Part Number
“A” Output Configuration
“B” Output Configuration
Non-Inverting
Package
LM5111-1M
LM5111-2M
LM5111-3M
Non-Inverting
Inverting
SOIC- 8
SOIC- 8
SOIC- 8
Inverting
Inverting
Non-Inverting
3
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Absolute Maximum Ratings (Note 1)
Storage Temperature Range, (TSTG
Maximum Junction Temperature,
(TJ(max))
)
−55˚C to +150˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+150˚C
+125˚C
2kV
Operating Junction Temperature
ESD Rating
VCC to VEE
IN to VEE
−0.3V to 15V
−0.3V to 15V
Electrical Characteristics
TJ = −40˚C to +125˚C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.
Symbol
VCCR
VCCH
ICC
Parameter
VCC Operating Range
VCC Under Voltage Lockout
(rising)
Conditions
VCC−VEE
Min
Typ
Max
Units
3.5
14
V
VCC−VEE
2.3
2.9
3.5
V
VCC Under Voltage Lockout
Hysteresis
230
1
mV
VCC Supply Current (ICC
)
IN_A = IN_B = 0V (5111-1)
IN_A = IN_B = VCC
(5111-2)
2
2
1
mA
IN_A = VCC, IN_B = 0V
(5111-3)
1
2
CONTROL INPUTS
VIH
VIL
HYS
IIL
Logic High
1.75
1.35
400
2.2
V
V
Logic Low
0.8
−1
Input Hysteresis
Input Current Low
mV
IN_A=IN_B=VCC
0.1
1
(5111-1-2-3)
IIH
Input Current High
IN_B=VCC (5111-3)
IN_A=IN_B=VCC (5111-2)
IN_A=IN_B=VCC (5111-1)
IN_A=VCC (5111-3)
10
−1
10
-1
18
0.1
18
25
1
µA
25
1
0.1
OUTPUT DRIVERS
ROH
Output Resistance High
IOUT = −10 mA
30
50
Ω
Ω
ROL
Output Resistance Low
Peak Source Current
IOUT = + 10 mA
1.4
2.5
ISource
OUTA/OUTB = VCC/2,
200 ns Pulsed Current
OUTA/OUTB = VCC/2,
200 ns Pulsed Current
3
5
A
A
ISink
Peak Sink Current
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Electrical Characteristics (Continued)
TJ = −40˚C to +125˚C, VCC = 12V, VEE = 0V, No Load on OUT_A or OUT_B, unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
SWITCHING CHARACTERISTICS
td1
td2
tr
Propagation Delay Time Low to CLOAD = 2 nF, see Figure
High, IN rising (IN to OUT)
Propagation Delay Time High to CLOAD = 2 nF, see Figure
25
25
14
12
40
40
25
25
ns
ns
ns
ns
1
Low, IN falling (IN to OUT)
Rise Time
1
CLOAD = 2.0 nF, see Figure
1
tf
Fall Time
CLOAD = 2 nF, see Figure
1
LATCHUP PROTECTION
AEC - Q100, Method 004
TJ = 150˚C
500
mA
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Timing Waveforms
20112306
20112305
(b)
(a)
FIGURE 1. (a) Inverting, (b) Non-Inverting
5
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Typical Performance Characteristics
Supply Current vs Frequency
Supply Current vs Capacitive Load
20112311
20112310
Rise and Fall Time vs Supply Voltage
Rise and Fall Time vs Temperature
20112312
20112313
Rise and Fall Time vs Capacitive Load
Delay Time vs Supply Voltage
20112314
20112315
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Typical Performance Characteristics (Continued)
Delay Time vs Temperature
RDSON vs Supply Voltage
20112317
20112316
UVLO Thresholds and Hysteresis vs Temperature
20112318
operated as a single with inputs and output pins connected.
The drive current capability in parallel operation is precisely
2X the drive of an individual channel. Small differences in
switching speed between the driver channels will produce a
transient current (shoot-through) in the output stage when
two output pins are connected to drive a single load. The
efficiency loss for parallel operation has been characterized
at various loads, supply voltages and operating frequencies.
The power dissipation in the LM5111 increases be less than
1% relative to the dual driver configuration when operated as
a single driver with inputs/ outputs connected.
Detailed Operating Description
LM5111 dual gate driver consists of two independent and
identical driver channels with TTL compatible logic inputs
and high current totem-pole outputs that source or sink
current to drive MOSFET gates. The driver output consist of
a compound structure with MOS and bipolar transistor oper-
ating in parallel to optimize current capability over a wide
output voltage and operating temperature range. The bipolar
device provides high peak current at the critical threshold
region of the MOSFET VGS while the MOS devices provide
rail-to-rail output swing. The totem pole output drives the
MOSFET gate between the gate drive supply voltage VCC
and the power ground potential at the VEE pin.
An Under Voltage Lock Out (UVLO) circuit is included in the
LM5111 , which senses the voltage difference between VCC
and the chip ground pin, VEE. When the VCC to VEE voltage
difference falls below 2.8V both driver channels are disabled.
The UVLO hysteresis prevents chattering during brown-out
conditions and the driver will resume normal operation when
the VCC to VEE differential voltage exceeds approximately
3.0V.
The control inputs of the drivers are high impedance CMOS
buffers with TTL compatible threshold voltages. The LM5111
pinout was designed for compatibility with industry standard
gate drivers in single supply gate driver applications.
The two driver channels of the LM5111 are designed as
identical cells. Transistor matching inherent to integrated
circuit manufacturing ensures that the AC and DC pe-
formance of the channels are nearly identical. Closely
matched propagation delays allow the dual driver to be
The LM5111 is available in dual non-inverting (-1), dual
Inverting (-2) and the combination inverting plus non-
inverting (-3) configurations. All three configurations are of-
fered in the SOIC-8 plastic package.
7
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Layout Considerations
Attention must be given to board layout when using LM5111.
Some important considerations include:
1. A Low ESR/ESL capacitor must be connected close to
the IC and between the VCC and VEE pins to support
high peak currents being drawn from VCC during turn-on
of the MOSFET.
2. Proper grounding is crucial. The drivers need a very low
impedance path for current return to ground avoiding
inductive loops. The two paths for returning current to
ground are a) between LM5111 VEE pin and the ground
of the circuit that controls the driver inputs, b) between
LM5111 VEE pin and the source of the power MOSFET
being driven. All these paths should be as short as
possible to reduce inductance and be as wide as pos-
sible to reduce resistance. All these ground paths should
be kept distinctly separate to avoid coupling between the
high current output paths and the logic signals that drive
the LM5111. A good method is to dedicate one copper
plane in a multi-layered PCB to provide a common
ground surface.
20112307
FIGURE 2.
The schematic above shows a conceptual diagram of the
LM5111 output and MOSFET load. Q1 and Q2 are the
switches within the gate driver. RG is the gate resistance of
the external MOSFET, and CIN is the equivalent gate capaci-
tance of the MOSFET. The gate resistance Rg is usually very
small and losses in it can be neglected. The equivalent gate
capacitance is a difficult parameter to measure since it is the
combination of CGS (gate to source capacitance) and CGD
(gate to drain capacitance). Both of these MOSFET capaci-
tances are not constants and vary with the gate and drain
voltage. The better way of quantifying gate capacitance is
the total gate charge QG in coloumbs. QG combines the
charge required by CGS and CGD for a given gate drive
3. With the rise and fall times in the range of 10 ns to 30 ns,
care is required to minimize the lengths of current car-
rying conductors to reduce their inductance and EMI
from the high di/dt transients generated by the LM5111.
4. The LM5111 SOIC footprint is compatible with other
industry standard drivers including the TC4426/27/28
and UCC27323/4/5.
5. If either channel is not being used, the respective input
pin (IN_A or IN_B) should be connected to either VEE or
VCC to avoid spurious output signals.
voltage VGATE
.
Assuming negligible gate resistance, the total power dissi-
pated in the MOSFET driver due to gate charge is approxi-
mated by
Thermal Performance
PDRIVER = VGATE x QG x FSW
INTRODUCTION
Where
The primary goal of thermal management is to maintain the
integrated circuit (IC) junction temperature (TJ) below a
specified maximum operating temperature to ensure reliabil-
ity. It is essential to estimate the maximum TJ of IC compo-
nents in worst case operating conditions. The junction tem-
perature is estimated based on the power dissipated in the
IC and the junction to ambient thermal resistance θJA for the
IC package in the application board and environment. The
θJA is not a given constant for the package and depends on
the printed circuit board design and the operating environ-
ment.
FSW = switching frequency of the MOSFET.
For example, consider the MOSFET MTD6N15 whose gate
charge specified as 30 nC for VGATE = 12V.
The power dissipation in the driver due to charging and
discharging of MOSFET gate capacitances at switching fre-
quency of 300 kHz and VGATE of 12V is equal to
PDRIVER = 12V x 30 nC x 300 kHz = 0.108W.
If both channels of the LM5111 are operating at equal fre-
quency with equivalent loads, the total losses will be twice as
this value which is 0.216W.
DRIVE POWER REQUIREMENT CALCULATIONS IN
LM5111
In addition to the above gate charge power dissipation, -
transient power is dissipated in the driver during output
transitions. When either output of the LM5111 changes state,
current will flow from VCC to VEE for a very brief interval of
time through the output totem-pole N and P channel
MOSFETs. The final component of power dissipation in the
driver is the power associated with the quiescent bias cur-
rent consumed by the driver input stage and Under-voltage
lockout sections.
The LM5111 dual low side MOSFET driver is capable of
sourcing/sinking 3A/5A peak currents for short intervals to
drive a MOSFET without exceeding package power dissipa-
tion limits. High peak currents are required to switch the
MOSFET gate very quickly for operation at high frequencies.
Characterization of the LM5111 provides accurate estimates
of the transient and quiescent power dissipation compo-
nents. At 300 kHz switching frequency and 30 nC load used
in the example, the transient power will be 8 mW. The 1 mA
nominal quiescent current and 12V VGATE supply produce a
12 mW typical quiescent power.
Therefore the total power dissipation
PD = 0.216 + 0.008 + 0.012 = 0.236W.
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flow. If the ambient temperature (TA) is 60˚C, and the RD
-
Thermal Performance (Continued)
We know that the junction temperature is given by
S(on) of the LM5111 output at TJ(max) is 2.5Ω, this equation
yields ISINK(max) of 391mA which is much smaller than 5A
peak pulsed currents.
TJ = PD x θJA + TA
Similarly, the maximum continuous source current can be
calculated as
Or the rise in temperature is given by
TRISE = TJ − TA = PD x θJA
For SOIC-8 package θJA is estimated as 170˚C/W for the
conditions of natural convection.
Therefore TRISE is equal to
TRISE = 0.236 x 170 = 40.1˚C
where VDIODE is the voltage drop across hybrid output stage
which varies over temperature and can be assumed to be
about 1.1V at TJ(max) of 125˚C. Assuming the same param-
eters as above, this equation yields ISOURCE(max) of 347mA.
CONTINUOUS CURRENT RATING OF LM5111
The LM5111 can deliver pulsed source/sink currents of 3A
and 5A to capacitive loads. In applications requiring continu-
ous load current (resistive or inductive loads), package
power dissipation, limits the LM5111 current capability far
below the 5A sink/3A source capability. Rated continuous
current can be estimated both when sourcing current to or
sinking current from the load. For example when sinking, the
maximum sink current can be calculated as:
where RDS(on) is the on resistance of lower MOSFET in the
output stage of LM5111.
Consider TJ(max) of 125˚C and θJA of 170˚C/W for an SO-8
package under the condition of natural convection and no air
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Physical Dimensions inches (millimeters)
unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
1. STANDARD LEAD FINISH TO BE 200 MICROINCHES/5.08 MICROMETERS MINIMUM LEAD/TIN(SOLDER) ON
COPPER.
2. DIMENSION DOES NOT INCLUDE MOLD FLASH.
3. REFERENCE JEDEC REGISTRATION MS-012, VARIATION AA, DATED MAY 1990.
8-Lead SOIC Package
NS Package Number M08A
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