LM5046 [NSC]
Based Eighth Brick Reference Board Input operating range: 36V to 75V; 基于1/8砖参考板输入电压范围： 36V至75V
| 型号： | LM5046 |
| 厂家： | 
National Semiconductor |
| 描述： | Based Eighth Brick Reference Board Input operating range: 36V to 75V |
| 文件： | 总4页 (文件大小：581K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
National Semiconductor
Application Note 2126
Ajay Hari
LM5046 Based Eighth Brick
Reference Board
March 4, 2011
Introduction
Theory of Operation
The LM5046 reference board is designed based on the
phase-shifted full-bridge topology. This board is for reference
only and is intended to demonstrate the capability of the
LM5046. Hardware is not provided for evaluation. Please re-
fer to AN2115 for LM5046 evaluation board. The reference
board is in an industry standard eighth brick footprint.
The Phase-Shifted Full-Bridge (PSFB) topology is a deriva-
tive of the classic full-bridge topology. When tuned appropri-
ately the PSFB topology achieves zero voltage switching
(ZVS) of the primary FETs while maintaining constant switch-
ing frequency. The ZVS feature is highly desirable as it re-
duces both the switching losses and EMI emissions. Figure 1
illustrates the circuit arrangement for the PSFB topology. The
power transfer mode of the PSFB topology is similar to the
hard switching full-bridge i.e., when the FETs in the diagonal
of the bridge are turned-on (Q1 & Q3 or Q2 & Q4), it initiates
a power transfer cycle. At the end of the power transfer cycle,
PWM turns off the switch Q3 or Q4 depending on the phase
with a pulse width determined by the input and output voltages
and the transformer turns ratio. In the freewheel mode, unlike
the classic full-bridge where all the four primary FETs are off,
in the PSFB topology the primary of the power transformer is
shorted by activating either both the top FETs (Q1 and Q4) or
both the bottom FETs (Q2 and Q3) alternatively. In a PSFB
topology, the primary switches are turned on alternatively en-
ergizing the windings in such a way that the flux swings back
and forth in the first and the third quadrants of the B-H curve.
The use of two quadrants allows better utilization of the core
resulting in a smaller core volume compared to the single-
ended topologies. Further, the ZVS of the primary FETs re-
sults in low EMI compared to the conventional hard-switching
full-bridge topology.
The performance of the evaluation board is as follows:
•
•
•
•
•
•
•
•
•
Input operating range: 36V to 75V
Output voltage: 12V
Measured efficiency at 48V: 92% @ 10A
Frequency of operation: 420kHz
Board size: 2.28 x 0.89 x 0.4 inches
Load Regulation: 0.2%
Line Regulation: 0.1%
Line UVLO (34V/32V on/off)
Hiccup Mode Current Limit
The printed circuit board consists of 10 layers; 2 ounce copper
outer layers and 3 ounce copper inner layers on FR4 material
with a total thickness of 0.12 inches. The unit is designed for
continuous operation at rated load at <40°C and a minimum
airflow of 200 CFM.
A schematic for the reference board is shown on Page 3. Bill
of Materials and gerber files will be uploaded shortly.
30152401
Simplified Full-Bridge Converter
© 2011 National Semiconductor Corporation
301524
www.national.com
30152419
LM5046 Based Eighth Brick Reference Board
vent output voltage disturbances due to the difference in the
voltage drop between the body diode and the channel resis-
tance of the synchronous MOSFETs. Feedback from the
output is processed by an amplifier and reference, generating
an error voltage, which is coupled back to the primary side
control through an opto-coupler. The LM5046 evaluation
board employs peak current mode control and a standard
“type II” network is used for the compensator.
The secondary side employs synchronous rectification
scheme, which is controlled by the LM5046. In addition to the
basic soft-start already described, the LM5046 contains a
second soft-start function that gradually turns on the syn-
chronous rectifiers to their steady-state duty cycle. This func-
tion keeps the synchronous rectifiers off until the error
amplifier on the secondary side soft-starts, allowing a linear
start-up of the output voltage even into pre-biased loads.
Then the SR output duty cycle is gradually increased to pre-
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