LM5035MH [NSC]
PWM Controller with Integrated Half-Bridge and SyncFET Drivers; PWM控制器，集成半桥及SyncFET驱动程序
| 型号： | LM5035MH |
| 厂家： | 
National Semiconductor |
| 描述： | PWM Controller with Integrated Half-Bridge and SyncFET Drivers |
| 文件： | 总28页 (文件大小：919K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 2006
LM5035
PWM Controller with Integrated Half-Bridge and
SyncFET Drivers
General Description
Features
n 105V / 2A Half-Bridge Gate Drivers
n Synchronous Rectifier Control Outputs with
Programmable Delays
The LM5035 Half-Bridge Controller/Gate Driver contains all
of the features necessary to implement half-bridge topology
power converters using voltage mode control with line volt-
age feed-forward. The floating high-side gate driver is ca-
pable of operating with supply voltages up to 105V. Both the
high-side and low-side gate drivers are capable of 2A peak.
An internal high voltage startup regulator is included, along
with programmable line undervoltage lockout (UVLO) and
overvoltage protection (OVP). The oscillator is programmed
with a single resistor to frequencies up to 2MHz. The oscil-
lator can also be synchronized to an external clock. A current
sense input and a programmable timer provide cycle-by-
cycle current limit and adjustable hiccup mode overload
protection.
n High Voltage (105V) Start-up Regulator
n Voltage mode Control with Line Feed-Forward and Volt •
Second Limiting
n Resistor Programmed, 2MHz Capable Oscillator
n Patent Pending Oscillator Synchronization
n Programmable Line Under-Voltage Lockout
n Line Over-Voltage Protection
n Internal Thermal Shutdown Protection
n Adjustable Soft-Start
n Versatile Dual Mode Over-Current Protection with
Hiccup Delay Timer
n Cycle-by-Cycle Over-Current Protection
n Direct Opto-coupler Interface
n 5V Reference Output
Packages
n TSSOP-20EP (Thermally enhanced)
n LLP-24 (4mm x 5mm)
Simplified Application Diagram
20177501
© 2006 National Semiconductor Corporation
DS201775
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Connection Diagrams
Top View
20177502
20-Lead TSSOP EP
Top View
20177503
LLP-24 Package
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2
Ordering Information
Order Number
LM5035MH
Package Type
NSC Package Drawing
MXA20A
Supplied As
TSSOP-20EP
TSSOP-20EP
LLP-24
73 Units per Rail
2500 Units on Tape and Reel
Available Soon
LM5035MHX
LM5035SQ
MXA20A
SQA24B
LM5035SQX
LLP-24
SQA24B
Available Soon
Pin Descriptions
TSSOP
PIN
LLP
PIN
23
Name
Description
Application Information
1
RAMP
Modulator ramp signal
An external RC circuit from VIN sets the ramp slope. This pin
is discharged at the conclusion of every cycle by an internal
FET. Discharge is initiated by either the internal clock or the
Volt • Second clamp comparator.
2
24
UVLO
Line Under-Voltage Lockout
An external voltage divider from the power source sets the
shutdown and standby comparator levels. When UVLO
reaches the 0.4V threshold the VCC and REF regulators are
enabled. When UVLO reaches the 1.25V threshold, the SS pin
is released and the device enters the active mode. Hysteresis
is set by an internal current sink that pulls 23µA from the
external resistor divider.
3
4
2
3
OVP
Line Over-Voltage Protection
An external voltage divider from the power source sets the
shutdown levels. The threshold is 1.25V. Hysteresis is set by
an internal current source that sources 23µA into the external
resistor divider.
COMP
Input to the Pulse Width
Modulator
An external opto-coupler connected to the COMP pin sources
current into an internal NPN current mirror. The PWM duty
cycle is maximum with zero input current, while 1mA reduces
the duty cycle to zero. The current mirror improves the
frequency response by reducing the AC voltage across the
opto-coupler detector.
5
4
RT
Oscillator Frequency Control and Normally biased at 2V. An external resistor connected between
Sync Clock Input.
RT and AGND sets the internal oscillator frequency. The
internal oscillator can be synchronized to an external clock with
a frequency higher than the free running frequency set by the
RT resistor.
6
7
5
6
AGND
CS
Analog Ground
Connect directly to Power Ground.
Current Sense input for current
limit
If CS exceeds 0.25V the output pulse will be terminated,
entering cycle-by-cycle current limit. An internal switch holds
CS low for 50ns after HO or LO switches high to blank leading
edge transients.
8
9
7
8
SS
Soft-start Input
An internal 55 µA current source charges an external capacitor
to set the soft-start rate. During a current limit restart
sequence, the internal current source is reduced to 1.2µA to
increase the delay before retry.
DLY
Timing programming pin for the
LO and HO to SR1 and SR2
outputs.
An external resistor to ground sets the timing for the
non-overlap time of HO to SR1 and LO to SR2.
3
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Pin Descriptions (Continued)
TSSOP
PIN
LLP
PIN
9
Name
Description
Restart Timer
Application Information
10
RES
If cycle-by-cycle current limit is exceeded during any cycle, a
22µA current is sourced to the RES pin capacitor. If the RES
capacitor voltage reaches 2.5V, the soft-start capacitor will be
fully discharged and then released with a pull-up current of
>
1.2µA. After the first output pulse at LO (when SS COMP
offset, typically 1V), the SS pin charging current will revert to
55µA.
11
11
HB
Boost voltage for the HO driver
An external diode is required from VCC to HB and an external
capacitor is required from HS to HB to power the HO gate
driver.
12
13
14
12
13
14
HS
HO
LO
Switch node
Connection common to the transformer and both power
switches. Provides a return path for the HO gate driver.
Output of the high side PWM gate driver. Capable of sinking
2A peak current.
High side gate drive output.
Low side gate drive output.
Output of the low side PWM gate driver. Capable of sinking 2A
peak current.
15
16
15
16
PGND
VCC
Power Ground
Connect directly to Analog Ground.
Output of the high voltage
start-up regulator. The VCC
voltage is regulated to 7.6V.
Synchronous rectifier driver
output.
If an auxiliary winding raises the voltage on this pin above the
regulation setpoint, the Start-up Regulator will shutdown, thus
reducing the internal power dissipation.
Control output of the synchronous FET gate. Capable of 0.5A
peak current.
17
18
19
20
17
18
19
21
SR2
SR1
REF
VIN
Synchronous rectifier driver
output.
Control output of the synchronous FET gate. Capable of 0.5A
peak current.
Output of 5V Reference
Maximum output current is 20mA. Locally decoupled with a
0.1µF capacitor.
Input voltage source
Input to the Start-up Regulator. Operating input range is 13V to
100V with transient capability to 105V. For power sources
outside of this range, the LM5035 can be biased directly at
VCC by an external regulator.
EP
EP
EP
Exposed Pad, underside of
package
No electrical contact. Connect to system ground plane for
reduced thermal resistance.
1
NC
NC
NC
NC
No connection
No connection
No connection
No connection
No electrical contact.
10
20
22
No electrical contact.
No electrical contact.
No electrical contact.
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4
Absolute Maximum Ratings (Note 1)
All other inputs to GND
ESD Rating (Note 4)
Human Body Model
-0.3V to 7V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
2kV
Storage Temperature Range
Junction Temperature
-65˚C to 150˚C
150˚C
VIN to GND
-0.3V to 105V
-1V to 105V
-0.3V to 118V
-0.3V to 18V
-0.3V to 16V
-0.3V to 5.5V
10mA
HS to GND
HB to GND
Operating Ratings (Note 1)
VIN Voltage
HB to HS
13V to 105V
VCC to GND
CS, RT, DLY to GND
COMP Input Current
External Voltage Applied to VCC
Operating Junction Temperature
8V to 15V
-40˚C to +125˚C
Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C, and those with boldface
type apply over full Operating Junction Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ,
RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless otherwise stated. See (Note 2) and (Note 3).
Symbol
Parameter
Conditions
Min
Typ
Max
7.9
Units
Startup Regulator (VCC pin)
VVCC
VCC voltage
IVCC = 10mA
7.3
20
7.6
25
V
mA
V
IVCC(LIM)
VVCCUV
VCC current limit
VVCC = 7V
VCC Under-voltage threshold
(VCC increasing)
VIN = VCC, ∆VVCC from the regulation
setpoint
0.2
0.1
VCC decreasing
VCC – PGND
5.5
6.2
30
4
6.9
70
6
V
IVIN
Startup regulator current
Supply current into VCC from
external source
VIN = 90V, UVLO = 0V
Outputs & COMP open, VVCC = 10V,
Outputs Switching
µA
mA
Voltage Reference Regulator (REF pin)
VREF
REF Voltage
IREF = 0mA
4.85
15
5
5.15
V
REF Voltage Regulation
REF Current Limit
IREF = 0 to 10mA
REF = 4.5V
25
20
50
mV
mA
Under-Voltage Lock Out and shutdown (UVLO pin)
VUVLO
IUVLO
Under-voltage threshold
Hysteresis current
1.212
19
1.25 1.288
V
µA
V
UVLO pin sinking
23
0.3
0.4
27
Under-voltage Shutdown Threshold UVLO voltage falling
Under-voltage Standby Enable
Threshold
UVLO voltage rising
V
Over-Voltage Protection (OVP pin)
VOVP
IOVP
Over-Voltage threshold
Hysteresis current
1.212
19
1.25 1.288
23 27
V
OVP pin sourcing
µA
Current Sense Input (CS Pin)
VCS Current Limit Threshold
0.228
0.25 0.272
V
CS delay to output
CS from zero to 1V. Time for HO and LO
to fall to 90% of VCC. Output load = 0
pF.
80
ns
Leading edge blanking time at CS
CS sink impedance (clocked)
50
ns
Internal FET sink impedance
32
60
Ω
Current Limit Restart (RES Pin)
VRES
RES Threshold
2.4
16
8
2.5
22
12
2.6
28
16
V
Charge source current
Discharge sink current
VRES = 1.5V
VRES = 1V
µA
µA
5
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Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C, and those with boldface
type apply over full Operating Junction Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ,
RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless otherwise stated. See (Note 2) and (Note 3). (Continued)
Symbol
Soft-Start (SS Pin)
ISS Charging current in normal
Parameter
Conditions
VSS = 0
Min
40
Typ
55
Max
70
Units
µA
operation
Charging current during a hiccup
mode restart
VSS = 0
0.6
40
1.2
55
1.8
70
µA
Soft-stop Current Sink
VSS = 2.5V
µA
Oscillator (RT Pin)
FSW1 Frequency 1 (at HO, half oscillator RRT = 15 kΩ, TJ = 25˚C
frequency)
185
180
430
200
500
215
220
570
kHz
kHz
RRT = 15 kΩ, TJ = -40˚C to 125˚C
FSW2
Frequency 2 (at HO, half oscillator RRT = 5.49 kΩ
frequency)
DC level
2
3
V
V
Input Sync threshold
2.5
0.7
3.4
PWM Controller (Comp Pin)
Delay to output
80
1
ns
V
VPWM-OS
SS to RAMP offset
1.2
0
Minimum duty cycle
Small signal impedance
SS = 0V
%
Ω
ICOMP = 600µA, COMP current to PWM
voltage
5000
Main Output Drivers (HO and LO Pins)
Output high voltage
IOUT = 50mA, VHB - VHO, VVCC - VLO
IOUT = 100 mA
0.5
45
0.25
0.2
15
V
V
Output low voltage
0.5
Rise time
CLOAD = 1 nF
ns
ns
ns
A
Fall time
CLOAD = 1 nF
13
Deadtime, HO to LO, LO to HO
Peak source current
Peak sink current
VDLY = VREF, ICOMP = 0mA
VHO,LO = 0V, VVCC = 10V
VHO,LO = 10V, VVCC = 10V
70
100
1.25
2
A
Voltage Feed-Forward (RAMP Pin)
RAMP comparator threshold
Synchronous Rectifier Drivers (SR1, SR2)
Output high voltage
COMP current = 0
2.4
2.5
2.6
0.2
V
IOUT = 10mA, VVCC - VSR1, VVCC - VSR2
IOUT = 20 mA (sink)
0.25
0.1
0.08
40
V
V
Output low voltage
Rise time
CLOAD = 1 nF
ns
ns
A
Fall time
CLOAD = 1 nF
20
Peak source current
Peak sink current
VSR = 0, VVCC = 10V
VSR = VVCC, VVCC = 10V
0.5
0.5
40
A
T1
T2
Deadtime, SR1 falling to HO rising, RDLY = 10k
ns
ns
ns
ns
ns
ns
SR2 falling to LO rising
RDLY = 27.4k
RDLY = 100k
75
30
100
300
20
125
65
Deadtime, HO falling to SR1 rising, RDLY = 10k
LO falling to SR2 rising
RDLY = 27.4k
RDLY = 100k
45
140
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Electrical Characteristics Specifications with standard typeface are for TJ = 25˚C, and those with boldface
type apply over full Operating Junction Temperature range. VVIN = 48V, VVCC = 10V externally applied, RRT = 15.0 kΩ,
RDLY = 27.4kΩ, VUVLO = 3V, VOVP = 0V unless otherwise stated. See (Note 2) and (Note 3). (Continued)
Symbol
Thermal Shutdown
TSD Shutdown temperature
Hysteresis
Thermal Resistance
Parameter
Conditions
Min
Typ
Max
Units
165
20
˚C
˚C
θJA
Junction to ambient, 0 LFPM Air
TSSOP-20_EP package
TSSOP-20_EP package
40
4
˚C/W
˚C/W
Flow
θJC
Junction to Case (EP)Thermal
resistance
Note 1: Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device
is intended to be functional. For guaranteed specifications and test conditions, see the Electrical Characteristics.
Note 2: All limits are guaranteed. All electrical characteristics having room temperature limits are tested during production with T = 25˚C. All hot and cold limits are
A
guaranteed by correlating the electrical characteristics to process and temperature variations and applying statistical process control.
Note 3: Typical specifications represent the most likely parametric norm at 25˚C operation
Note 4: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. 2kV for all pins except HB, HO and HS which are rated
at 1.5kV.
7
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Typical Performance Characteristics
VVCC and VREF vs VVIN
VVCC vs IVCC
20177506
20177505
VREF vs IREF
Frequency vs RT
20177507
20177508
Oscillator Frequency vs Temperature
Soft-Start & Stop Current vs Temperature
20177509
20177510
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Typical Performance Characteristics (Continued)
Effective Comp Input Impedance
RDLY vs Deadtime
20177511
20177512
SR "T1" Parameter vs Temperature
SR "T2" Parameter vs Temperature
20177513
20177514
9
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Block Diagram
20177504
FIGURE 1.
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both the VCC and the VIN pins. The external bias must be
greater than 8.3V to exceed the VCC UVLO threshold and
less than the VCC maximum operating voltage rating (15V).
Functional Description
The LM5035 PWM controller contains all of the features
necessary to implement half-bridge voltage-mode controlled
power converters. The LM5035 provides two gate driver
outputs to directly drive the primary side power MOSFETs
and two signal level outputs to control secondary synchro-
nous rectifiers through an isolation interface. Secondary side
drivers, such as the LM5110, are typically used to provide
the necessary gate drive current to control the sync MOS-
FETs. Synchronous rectification allows higher conversion
efficiency and greater power density than conventional PN or
Schottky rectifier techniques. The LM5035 can be configured
to operate with bias voltages ranging from 8V to 105V.
Additional features include line under-voltage lockout, cycle-
by-cycle current limit, voltage feed-forward compensation,
hiccup mode fault protection with adjustable delays, soft-
start, a 2MHz capable oscillator with synchronization capa-
bility, precision reference, thermal shutdown and program-
mable volt•second clamping. These features simplify the
design of voltage-mode half-bridge DC-DC power convert-
ers. The Functional Block Diagram is shown in Figure 1.
Line Under-Voltage Detector
The LM5035 contains a dual level Under-Voltage Lockout
(UVLO) circuit. When the UVLO pin voltage is below 0.4V,
the controller is in a low current shutdown mode. When the
UVLO pin voltage is greater than 0.4V but less than 1.25V,
the controller is in standby mode. In standby mode the VCC
and REF bias regulators are active while the controller out-
puts are disabled. When the VCC and REF outputs exceed
the VCC and REF under-voltage thresholds and the UVLO
pin voltage is greater than 1.25V, the outputs are enabled
and normal operation begins. An external set-point voltage
divider from VIN to GND can be used to set the minimum
operating voltage of the converter. The divider must be
designed such that the voltage at the UVLO pin will be
greater than 1.25V when VIN enters the desired operating
range. UVLO hysteresis is accomplished with an internal
23uA current sink that is switched on or off into the imped-
ance of the set-point divider. When the UVLO threshold is
exceeded, the current sink is deactivated to quickly raise the
voltage at the UVLO pin. When the UVLO pin voltage falls
below the 1.25V threshold, the current sink is enabled caus-
ing the voltage at the UVLO pin to quickly fall. The hysteresis
of the 0.4V shutdown comparator is internally fixed at
100mV.
High-Voltage Start-up Regulator
The LM5035 contains an internal high voltage start-up regu-
lator that allows the input pin (VIN) to be connected directly
to a nominal 48 VDC input voltage. The regulator input can
withstand transients up to 105V. The regulator output at VCC
(7.6V) is internally current limited to 25 mA typical. When the
UVLO pin potential is greater than 0.4V, the VCC regulator is
enabled to charge an external capacitor connected to the
VCC pin. The VCC regulator provides power to the voltage
reference (REF) and the output drivers (LO, SR1 and SR2).
When the voltage on the VCC pin exceeds the UVLO thresh-
old of 7.6V, the internal voltage reference (REF) reaches its
regulation setpoint of 5V and the UVLO voltage is greater
than 1.25V, the controller outputs are enabled. The value of
the VCC capacitor depends on the total system design, and
its start-up characteristics. The recommended range of val-
ues for the VCC capacitor is 0.1µF to 100µF.
The UVLO pin can also be used to implement various re-
mote enable / disable functions. Turning off a converter by
forcing the UVLO pin to the standby condition provides a
controlled soft-stop. See the Soft Start section for more
details.
Line Over Voltage / Load Over
Voltage / Remote Thermal
Protection
The LM5035 provides a multipurpose OVP pin that supports
several fault protection functions. When the OVP pin voltage
exceeds 1.25V, the controller is held in standby mode which
immediately halts the PWM pulses at the HO and LO pins. In
standby mode, the VCC and REF bias regulators are active
while the controller outputs are disabled. When the OVP pin
voltage falls below the 1.25V OVP threshold, the outputs are
enabled and normal soft-start sequence begins. Hysteresis
is accomplished with an internal 23µA current source that is
switched on or off into the impedance of the OVP pin set-
point divider. When the OVP threshold is exceeded, the
current source is enabled to quickly raise the voltage at the
OVP pin. When the OVP pin voltage falls below the 1.25V
threshold, the current source is disabled causing the voltage
at the OVP pin to quickly fall.
The VCC under-voltage comparator threshold is lowered to
6.2V (typical) after VCC reaches the regulation set-point. If
VCC falls below this value, the outputs are disabled, and the
soft-start capacitor is discharged. If VCC increases above
7.6V, the outputs will be enabled and a soft-start sequence
will commence.
The internal power dissipation of the LM5035 can be re-
duced by powering VCC from an external supply. In typical
applications, an auxiliary transformer winding is connected
through a diode to the VCC pin. This winding must raise the
VCC voltage above 8.3V to shut off the internal start-up
regulator. Powering VCC from an auxiliary winding improves
efficiency while reducing the controller’s power dissipation.
The under-voltage comparator circuit will still function in this
mode, requiring that VCC never falls below 6.2V during the
start-up sequence.
Several examples of the use of this pin are provided in the
Application Information section.
During a fault mode, when the converter auxiliary winding is
inactive, external current draw on the VCC line should be
limited such that the power dissipated in the start-up regula-
tor does not exceed the maximum power dissipation of the
IC package.
Reference
The REF pin is the output of a 5V linear regulator that can be
used to bias an opto-coupler transistor and external house-
keeping circuits. The regulator output is internally current
limited to 20mA (typical).
An external DC bias voltage can be used instead of the
internal regulator by connecting the external bias voltage to
11
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current source causes the voltage at the RES pin to gradu-
ally increase. The LM5035 protects the converter with cycle-
by-cycle current limiting while the voltage at RES pin in-
creases. If the RES voltage reaches the 2.5V threshold, the
following restart sequence occurs (also see Figure 2):
Cycle-by-Cycle Current Limit
The CS pin is driven by a signal representative of the trans-
former primary current. If the voltage sensed at CS pin
exceeds 0.25V, the current sense comparator terminates the
HO or LO output driver pulse. If the high current condition
persists, the controller operates in a cycle-by-cycle current
limit mode with duty cycle determined by the current sense
comparator instead of the PWM comparator. Cycle-by-cycle
current limiting may trigger the hiccup mode restart cycle
depending on the configuration of the RES pin (see below).
•
The RES capacitor and SS capacitors are fully dis-
charged
•
•
The soft-start current source is reduced from 55µA to 1µA
The SS capacitor voltage slowly increases. When the SS
voltage reaches )1V, the PWM comparator will produce
the first narrow output pulse. After the first pulse occurs,
the SS source current reverts to the normal 55µA level.
The SS voltage increases at its normal rate, gradually
increasing the duty cycle of the output drivers
A small R-C filter connect to the CS pin and located near the
controller is recommended to suppress noise. An internal
32Ω MOSFET connected to the CS input discharges the
external current sense filter capacitor at the conclusion of
every cycle. The discharge MOSFET remains on for an
additional 50 ns after the HO or LO driver switches high to
blank leading edge transients in the current sensing circuit.
Discharging the CS pin filter each cycle and blanking leading
edge spikes reduces the filtering requirements and improves
the current sense response time.
•
•
If the overload condition persists after restart, cycle-by-
cycle current limiting will begin to increase the voltage on
the RES capacitor again, repeating the hiccup mode
sequence
If the overload condition no longer exists after restart, the
RES pin will be held at ground by the 12µA current sink
and normal operation resumes
The current sense comparator is very fast and responds to
short duration noise pulses. Layout considerations are criti-
cal for the current sense filter and sense resistor. The ca-
pacitor associated with the CS filter must be placed very
close to the device and connected directly to the CS and
AGND pins. If a current sense transformer is used, both
leads of the transformer secondary should be routed to the
filter network, which should be located close to the IC. If a
sense resistor located in the source of the main MOSFET
switch is used for current sensing, a low inductance type of
resistor is required. When designing with a current sense
resistor, all of the noise sensitive low power ground connec-
tions should be connected together near the AGND pin, and
a single connection should be made to the power ground
(sense resistor ground point).
The overload timer function is very versatile and can be
configured for the following modes of protection:
1. Cycle-by-cycle only: The hiccup mode can be com-
pletely disabled by connecting a zero to 50kΩ resistor from
the RES pin to AGND. In this configuration, the cycle-by-
cycle protection will limit the output current indefinitely and
no hiccup sequences will occur.
2. Hiccup only: The timer can be configured for immediate
activation of a hiccup sequence upon detection of an over-
load by leaving the RES pin open circuit.
3. Delayed Hiccup: Connecting a capacitor to the RES pin
provides a programmed interval of cycle-by-cycle limiting
before initiating a hiccup mode restart, as previously de-
scribed. The dual advantages of this configuration are that a
short term overload will not cause a hiccup mode restart but
during extended overload conditions, the average dissipa-
tion of the power converter will be very low.
Overload Protection Timer
The LM5035 provides a current limit restart timer to disable
the outputs and force a delayed restart (hiccup mode) if a
current limit condition is repeatedly sensed. The number of
cycle-by-cycle current limit events required to trigger the
restart is programmable by the external capacitor at the RES
pin. During each PWM cycle, the LM5035 either sources or
sinks current from the RES pin capacitor. If no current limit is
detected during a cycle, an 12µA discharge current sink is
enabled to pull the RES pin to ground. If a current limit is
detected, the 12µA sink current is disabled and a 22µA
4. Externally Controlled Hiccup: The RES pin can also be
used as an input. By externally driving the pin to a level
greater than the 2.5V hiccup threshold, the controller will be
forced into the delayed restart sequence. For example, the
external trigger for a delayed restart sequence could come
from an over-temperature protection circuit or an output
over-voltage sensor.
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Overload Protection Timer (Continued)
20177515
FIGURE 2. Current Limit Restart Circuit
20177516
FIGURE 3. Current Limit Restart Timing
13
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Overload Protection Timer (Continued)
20177517
FIGURE 4. Optocoupler to COMP Interface
achieve minimum controllable duty cycles. The loop error
signal is received from the external feedback and isolation
circuit is in the form of a control current into the COMP pin.
The COMP pin current is internally mirrored by a matched
pair of NPN transistors which sink current through a 5kΩ
resistor connected to the 5V reference. The resulting control
voltage passes through a 1V level shift before being applied
to the PWM comparator.
Soft-Start
The soft-start circuit allows the regulator to gradually reach a
steady state operating point, thereby reducing start-up
stresses and current surges. When bias is supplied to the
LM5035, the SS pin capacitor is discharged by an internal
MOSFET. When the UVLO, VCC and REF pins reach their
operating thresholds, the SS capacitor is released and
charged with a 55µA current source. The PWM comparator
control voltage is clamped to the SS pin voltage by an
internal amplifier. When the PWM comparator input reaches
1V, output pulses commence with slowly increasing duty
cycle. The voltage at the SS pin eventually increases to 5V,
while the voltage at the PWM comparator increases to the
value required for regulation as determined by the voltage
feedback loop.
An opto-coupler detector can be connected between the
REF pin and the COMP pin. Because the COMP pin is
controlled by a current input, the potential difference across
the optocoupler detector is nearly constant. The bandwidth
limiting phase delay which is normally introduced by the
significant capacitance of the opto-coupler is thereby greatly
reduced. Higher loop bandwidths can be realized since the
bandwidth-limiting pole associated with the opto-coupler is
now at a much higher frequency. The PWM comparator
polarity is configured such that with no current into the
COMP pin, the controller produces the maximum duty cycle
at the main gate driver outputs, HO and LO.
One method to shutdown the regulator is to ground the SS
pin. This forces the internal PWM control signal to ground,
reducing the output duty cycle quickly to zero. Releasing the
SS pin begins a soft-start cycle and normal operation re-
sumes. A second shutdown method is discussed in the
UVLO section.
Feed-Forward Ramp and Volt •
Second Clamp
Soft-Stop
An external resistor (RFF) and capacitor (CFF) connected to
VIN, AGND, and the RAMP pin are required to create the
PWM ramp signal. The slope of the signal at RAMP will vary
in proportion to the input line voltage. This varying slope
provides line feed-forward information necessary to improve
line transient response with voltage mode control. The
RAMP signal is compared to the error signal by the pulse
width modulator comparator to control the duty cycle of the
HO and LO outputs. With a constant error signal, the on-time
(TON) varies inversely with the input voltage (VIN) to stabilize
the Volt • Second product of the transformer primary signal.
The power path gain of conventional voltage-mode pulse
width modulators (oscillator generated ramp) varies directly
with input voltage. The use of a line generated ramp (input
voltage feed-forward) nearly eliminates this gain variation.
As a result, the feedback loop is only required to make very
small corrections for large changes in input voltage.
If the UVLO pin voltage falls below the 1.25V standby thresh-
old but above the 0.4V shutdown threshold, the 55µA SS pin
source current is disabled and a 55µA sink current dis-
charges the soft-start capacitor. As SS voltage falls and
clamps the PWM comparator input, the PWM duty cycle will
gradually fall to zero. The soft-stop feature produces a
gradual reduction of the power converter output voltage. This
soft-stop method of turning off the converter reduces energy
in the output capacitor before control of the main and syn-
chronous rectification MOSFETs is disabled. The PWM
pulses may cease before the SS voltage reduces the duty
cycle if the VCC or REF voltage drops below the respective
under-voltage thresholds during the soft-stop process.
PWM Comparator
The pulse width modulation (PWM) comparator compares
the voltage ramp signal at the RAMP pin to the loop error
signal. This comparator is optimized for speed in order to
In addition to the PWM comparator, a Volt • Second Clamp
comparator also monitors the RAMP pin. If the ramp ampli-
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14
frequency set by the RT resistor. If the external clock fre-
quency is less than the RT resistor programmed frequency,
the LM5035 will ignore the synchronizing pulses. The syn-
chronization pulse width at the RT pin must be a minimum of
15 ns wide. The clock signal should be coupled into the RT
pin through a 100pF capacitor or a value small enough to
ensure the pulse width at RT is less than 60% of the clock
period under all conditions. When the synchronizing pulse
transitions low-to-high (rising edge), the voltage at the RT pin
must be driven to exceed 3.2V volts from its nominal 2 VDC
level. During the clock signal’s low time, the voltage at the
RT pin will be clamped at 2 VDC by an internal regulator. The
output impedance of the RT regulator is approximately
100Ω. The RT resistor is always required, whether the oscil-
lator is free running or externally synchronized.
Feed-Forward Ramp and Volt •
Second Clamp (Continued)
tude exceeds the 2.5V threshold of the Volt • Second Clamp
comparator, the on-time is terminated. The CFF ramp capaci-
tor is discharged by an internal 32Ω discharge MOSFET
controlled by the V•S Clamp comparator. If the RAMP signal
does not exceed 2.5V before the end of the clock period,
then the internal clock will enable the discharge MOSFET to
reset capacitor CFF
.
By proper selection of RFF and CFF values, the maximum
on-time of HO and LO can be set to the desired duration.
The on-time set by the Volt • Second Clamp varies inversely
to the line voltage because the RAMP capacitor is charged
by a resistor (RFF) connected to VIN while the threshold of
the clamp is a fixed voltage (2.5V). An example will illustrate
the use of the Volt • Second Clamp comparator to achieve a
50% duty cycle limit at 200kHz with a 48V line input. A 50%
duty cycle at a 200kHz requires a 2.5µs on-time. To achieve
this maximum on-time clamp level:
Gate Driver Outputs (HO & LO)
The LM5035 provides two alternating gate driver outputs,
the floating high side gate driver HO and the ground refer-
enced low side driver LO. Each driver is capable of sourcing
1.25A and sinking 2A peak. The HO and LO outputs operate
in an alternating manner, at one-half the internal oscillator
frequency. The LO driver is powered directly by the VCC
regulator. The HO gate driver is powered from a bootstrap
capacitor connected between HB and HS. An external diode
connected between VCC (anode pin) and HB (cathode pin)
provides the high side gate driver power by charging the
bootstrap capacitor from VCC when the switch node (HS
pin) is low. When the high side MOSFET is turned on, HB
rises to a peak voltage equal to VVCC + VHS where VHS is the
switch node voltage.
The recommended capacitor value range for CFF is 100pF to
1000pF. 470pF is a standard value that can be paired with an
110kΩ to approximate the desired 51.4µs time constant. If
load transient response is slowed by the 10% margin, the
RFF value can be increased. The system signal-to-noise will
The HB and VCC capacitors should be placed close to the
pins of the LM5035 to minimize voltage transients due to
parasitic inductances since the peak current sourced to the
MOSFET gates can exceed 1.25A. The recommended value
of the HB capacitor is 0.01µF or greater. A low ESR / ESL
capacitor, such as a surface mount ceramic, should be used
to prevent voltage droop during the HO transitions.
be slightly decreased by increasing RFF x CFF
.
Oscillator, Sync Capability
The LM5035 oscillator frequency is set by a single external
resistor connected between the RT and AGND pins. To set a
desired oscillator frequency, the necessary RT resistor is
calculated from:
The maximum duty cycle for each output is limited to slightly
less than 50% due to the internally fixed deadtime. If the
COMP pin is open circuit, the outputs will operate at maxi-
mum duty cycle. The typical deadtime in this condition is
70ns which does not vary with operating frequency. The
maximum duty cycle for each output can be calculated with
the following equation:
For example, if the desired oscillator frequency is 400kHz
(HO and LO each switching at 200kHz) a 15kΩ resistor
would be the nearest standard one percent value.
Each output (HO, LO, SR1 and SR2) switches at half the
oscillator frequency. The voltage at the RT pin is internally
regulated to a nominal 2V. The RT resistor should be located
as close as possible to the IC, and connected directly to the
pins (RT and AGND). The tolerance of the external resistor,
and the frequency tolerance indicated in the Electrical Char-
acteristics, must be taken into account when determining the
worst case frequency range.
where TS is the period of one complete cycle for both HO
and LO outputs, and TD is the deadtime. For example, if the
oscillator frequency is 200 kHz, each output will cycle at 100
kHz (TS = 10µs). Using the nominal deadtime of 70ns, the
maximum duty cycle at this frequency is calculated to be
49.3%.
The LM5035 can be synchronized to an external clock by
applying a narrow pulse to the RT pin. The external clock
must be at least 10% higher than the free-running oscillator
15
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Gate Driver Outputs (HO & LO) (Continued)
20177521
FIGURE 5. HO, LO, SR1 and SR2 Timing Diagram
0.5A peak. Typically, the SR1 and SR2 signals control SR
MOSFET gate drivers through a pulse transformer. The ac-
tual gate sourcing and sinking currents are provided by the
secondary-side bias supply and gate drivers.
Synchronous Rectifier Control
Outputs (SR1 & SR2)
Synchronous rectification (SR) of the transformer secondary
provides higher efficiency, especially for low output voltage
converters. The reduction of rectifier forward voltage drop
(0.5V - 1.5V) to 10mV - 200mV VDS voltage for a MOSFET
significantly reduces rectification losses. In a typical applica-
tion, the transformer secondary winding is center tapped,
with the output power inductor in series with the center tap.
The SR MOSFETs provide the ground path for the energized
secondary winding and the inductor current. Figure 5 shows
that the SR2 MOSFET is conducting while HO enables
power transfer from the primary. The SR1 MOSFET must be
disabled during this period since the secondary winding
connected to the SR1 MOSFET drain is twice the voltage of
the center tap. At the conclusion of the HO pulse, the induc-
tor current continues to flow through the SR1 MOSFET body
diode. Since the body diode causes more loss than the SR
MOSFET, efficiency can be improved by minimizing the T2
period while maintaining sufficient timing margin over all
conditions (component tolerances, etc.) to prevent shoot-
through current. When LO enables power transfer from the
primary, the SR1 MOSFET is enabled and the SR2 MOSFET
is off.
The timing of SR1 and SR2 with respect to HO and LO is
shown in Figure 5. SR1 is configured out of phase with HO
and SR2 is configured out of phase with LO. The deadtime
between transitions is programmable by a resistor con-
nected from the DLY pin to the AGND pin. Typically, RDLY is
set in the range of 10kΩ to 100kΩ. The deadtime periods
can be calculated using the following formulae:
T1 = [RDLY x 2.8ps] + 20ns
T2 = [RDLY x 1.35ps] + 6ns
To set the minimum (propagation delays only) deadtime, the
DLY pin should be left open or connected to the REF pin.
Any resistor value above 300kΩ connected between the DLY
pin and AGND will also provide the minimum period (ap-
proximately 5 ns).
Thermal Protection
Internal Thermal Shutdown circuitry is provided to protect the
integrated circuit in the event the maximum rated junction
temperature is exceeded. When activated, typically at
165˚C, the controller is forced into a low power standby state
with the output drivers (HO, LO, SR1 and SR2), the bias
regulators (VCC and REF) disabled. This helps to prevent
catastrophic failures from accidental device overheating.
During thermal shutdown, the soft-start capacitor is fully
discharged and the controller follows a normal start-up se-
quence after the junction temperature falls to the operating
level (145˚C).
During the time that neither HO nor LO is active, the inductor
current is shared between both the SR1 and SR2 MOSFETs
which effectively shorts the transformer secondary and can-
cels the inductance in the windings. The SR2 MOSFET is
disabled before LO delivers power to the secondary to pre-
vent power being shunted to ground. The SR2 MOSFET
body diode continues to carry about half the inductor current
until the primary power raises the SR2 MOSFET drain volt-
age and reverse biases the body diode. Ideally, dead-time
T1 would be set to the minimum time that allows the SR
MOSFET to turn off before the SR MOSFET body diode
starts conducting.
The SR1 and SR2 outputs are powered directly by the VCC
regulator. Each output is capable of sourcing and sinking
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16
Applications Information
>
FOR APPLICATIONS 100V
The following information is intended to provide guidelines
for the power supply designer using the LM5035.
For applications where the system input voltage exceeds
100V or the IC power dissipation is of concern, the LM5035
can be powered from an external start-up regulator as
shown in Figure 7. In this configuration, the VIN and the VCC
pins should be connected together, which allows the
LM5035 to be operated below 13V. The voltage at the VCC
pin must be greater than 8.3V yet not exceed 15V. An
auxiliary winding can be used to reduce the power dissipa-
tion in the external regulator once the power converter is
active. The NPN base-emitter reverse breakdown voltage,
which can be as low as 5V for some transistors, should be
considered when selecting the transistor.
VIN
The voltage applied to the VIN pin, which may be the same
as the system voltage applied to the power transformer’s
primary (VPWR), can vary in the range of 13 to 105V. The
current into VIN depends primarily on the gate charge pro-
vided to the output drivers, the switching frequency, and any
external loads on the VCC and REF pins. It is recommended
the filter shown in Figure 6 be used to suppress transients
which may occur at the input supply. This is particularly
important when VIN is operated close to the maximum op-
erating rating of the LM5035.
CURRENT SENSE
When power is applied to VIN and the UVLO pin voltage is
greater than 0.4V, the VCC regulator is enabled and supplies
current into an external capacitor connected to the VCC pin.
When the voltage on the VCC pin reaches the regulation
point of 7.6V, the voltage reference (REF) is enabled. The
reference regulation set point is 5V. The HO, LO, SR1 and
SR2 outputs are enabled when the two bias regulators reach
their set point and the UVLO pin potential is greater than
1.25V. In typical applications, an auxiliary transformer wind-
ing is connected through a diode to the VCC pin. This
winding must raise the VCC voltage above 8.3V to shut off
the internal start-up regulator.
The CS pin needs to receive an input signal representative
of the transformer’s primary current, either from a current
sense transformer or from a resistor in series with the source
of the LO switch, as shown in Figure 8 and Figure 9. In both
cases, the sensed current creates a ramping voltage across
R1, and the RF/CF filter suppresses noise and transients.
R1, RF and CF should be located as close to the LM5035 as
possible, and the ground connection from the current sense
transformer, or R1, should be a dedicated track to the AGND
pin. The current sense components must provide greater
than 0.25V at the CS pin when an over-current condition
exists.
After the outputs are enabled and the external VCC supply
voltage has begun supplying power to the IC, the current into
VIN drops below 1 mA. VIN should remain at a voltage equal
to or above the VCC voltage to avoid reverse current through
protection diodes.
20177522
FIGURE 6. Input Transient Protection
17
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Applications Information (Continued)
20177523
>
FIGURE 7. Start-up Regulator for VPWR 100V
20177524
FIGURE 8. Current Sense Using Current Sense Transformer
20177525
FIGURE 9. Current Sense Using Current Sense Resistor (R1)
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18
Applications Information (Continued)
If the current sense resistor method is used, the over-current
condition will only be sensed while LO is driving the low-side
MOSFET. Over-current while HO is driving the high-side
MOSFET will not be detected. In this configuration, it will
take 4 times as long for continuous cycle-by-cycle current
limiting to initiate a restart event since each over-current
event during LO enables the 22µA RES pin current source
for one oscillator period, and then the lack of an over-current
event during HO enables the 12µA RES pin current sink for
one oscillator period. The time average of this toggling is
equivalent to a continuous 5µA current source into the RES
capacitor, increasing the delay by a factor of four. The value
of the RES capacitor can be reduced to decrease the time
before restart cycle is initiated.
PROGRAMMABLE DELAY (DLY)
The RDLY resistor programs the delays between the SR1 and
SR2 signals and the HO and LO driver outputs. Figure 5
shows the relationship between these outputs. The DLY pin
is nominally set at 2.5V and the current is sensed through
RDLY to ground. This current is used to adjust the amount of
deadtime before the HO and LO pulse (T1) and after the HO
and LO pulse (T2). Typically RDLY is in the range of 10kΩ to
100kΩ. The deadtime periods can be calculated using the
following formulae:
T1 = [RDLY x 2.8ps] + 20ns
T2 = [RDLY x 1.35ps] + 6ns
HO, HB, HS and LO
Attention must be given to the PC board layout for the
low-side driver and the floating high-side driver pins HO, HB
and HS. A low ESR/ESL capacitor (such as a ceramic sur-
face mount capacitor) should be connected close to the
LM5035, between HB and HS to provide high peak currents
during turn-on of the high-side MOSFET. The capacitor
should be large enough to supply the MOSFET gate charge
(Qg) without discharging to the point where the drop in gate
voltage affects the MOSFET RDS(ON). A value ten to twenty
times Qg is recommended.
T1 and T2 can be set to minimum by not connecting a
resistor to DLY, connecting a resistor greater than 300kΩ
from DLY to ground, or connecting DLY to the REF pin. This
may cause lower than optimal system efficiency if the delays
through the SR signal transformer network, the secondary
gate drivers and the SR MOSFETs are greater than the
delay to turn on the HO or LO MOSFETs. Should an SR
MOSFET remain on while the opposing primary MOSFET is
supplying power through the power transformer, the second-
ary winding will experience a momentary short circuit, caus-
ing a significant power loss to occur.
When choosing the RDLY value, worst case propagation
delays and component tolerances should be considered to
assure that there is never a time where both SR MOSFETs
are enabled AND one of the primary side MOSFETs is
enabled. The time period T1 should be set so that the SR
MOSFET has turned off before the primary MOSFET is
enabled. Conversely, T1 and T2 should be kept as low as
tolerances allow to optimize efficiency. The SR body diode
conducts during the time between the SR MOSFET turns off
and the power transformer begins supplying energy. Power
losses increase when this happens since the body diode
voltage drop is many times higher than the MOSFET chan-
nel voltage drop. The interval of body diode conduction can
be observed with an oscilloscope as a negative 0.7V to 1.5V
pulse at the SR MOSFET drain.
The diode (DBOOST) that charges CBOOST from VCC when
the low-side MOSFET is conducting should be capable of
withstanding the full converter input voltage range. When the
high-side MOSFET is conducting, the reverse voltage at the
diode is approximately the same as the MOSFET drain
voltage because the high-side driver is boosted up to the
converter input voltage by the HS pin, and the high side
MOSFET gate is driven to the HS voltage plus VCC. Since
the anode of DBOOST is connected to VCC, the reverse
potential across the diode is equal to the input voltage minus
the VCC voltage. DBOOST average current is less than 20mA
in most applications, so a low current ultra-fast recovery
diode is recommended to limit the loss due to diode junction
capacitance. Schottky diodes are also a viable option, par-
ticularly for lower input voltage applications, but attention
must be paid to leakage currents at high temperatures.
UVLO AND OVP VOLTAGE DIVIDER SELECTION FOR
R1, R2, AND R3
Two dedicated comparators connected to the UVLO and
OVP pins are used to detect under-voltage and over-voltage
conditions. The threshold value of these comparators, VUVLO
and VOVP, is 1.25V (typical). The two functions can be
programmed independently with two voltage dividers from
VIN to AGND as shown in Figure 10 and Figure 11, or with a
three-resistor divider as shown in Figure 12. Independent
UVLO and OVP pins provide greater flexibility for the user to
select the operational voltage range of the system. Hyster-
esis is accomplished by 23µA current sources (IUVLO and
IOVP), which are switched on or off into the sense pin resistor
dividers as the comparators change state.
The internal gate drivers need a very low impedance path to
the respective decoupling capacitors; the VCC cap for the
LO driver and CBOOST for the HO driver. These connections
should be as short as possible to reduce inductance and as
wide as possible to reduce resistance. The loop area, de-
fined by the gate connection and its respective return path,
should be minimized.
The high-side gate driver can also be used with HS con-
nected to PGND for applications other than a half bridge
converter (e.g. Push-Pull). The HB pin is then connected to
VCC, or any supply greater than the high-side driver under-
voltage lockout (approximately 6.5V). In addition, the high-
side driver can be configured for high voltage offline appli-
cations where the high-side MOSFET gate is driven via a
gate drive transformer.
When the UVLO pin voltage is below 0.4V, the controller is in
a low current shutdown mode. For a UVLO pin voltage
greater than 0.4V but less than 1.25V the controller is in
standby mode. Once the UVLO pin voltage is greater than
1.25V, the controller is fully enabled. Two external resistors
can be used to program the minimum operational voltage for
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For example, if the LM5035 is to be enabled when VPWR
reaches 34V, and disabled when VPWR is decreased to
32V, R1 should be 87kΩ, and R2 should be 3.54kΩ. The
voltage at the UVLO pin should not exceed 7V at any time.
Be sure to check both the power and voltage rating (0603
resistors can be rated as low as 50V) for the selected R1
resistor.
Applications Information (Continued)
the power converter as shown in Figure 10. When the UVLO
pin voltage falls below the 1.25V threshold, an internal 23 µA
current sink is enabled to lower the voltage at the UVLO pin,
thus providing threshold hysteresis. Resistance values for
R1 and R2 can be determined from the following equations.
where VPWR is the desired turn-on voltage and VHYS is the
desired UVLO hysteresis at VPWR
.
20177529
FIGURE 10. Basic UVLO Configuration
20177530
FIGURE 11. Basic Over-Voltage Protection
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20
Applications Information (Continued)
20177531
FIGURE 12. UVLO/OVP Divider
The impedance seen looking into the resistor divider from
the UVLO and OVP pins determines the hysteresis level.
UVLO and OVP enable and disable thresholds are calcu-
lated using the equations in the table below for the three-
resistor divider illustrated in Figure 12.
TABLE 1. UVO/OVP Divider Formulas
Outputs disabled due to VIN falling below UVLO threshold
Outputs enabled due to VIN rising above UVLO threshold
Outputs disabled due to VIN rising above OVP threshold
UVLOon = UVLOoff + (23µA x R1)
Outputs enabled due to VIN falling below OVP threshold
OVPon = OVPoff - [23µA x (R1 + R2)]
The typical operating ranges of undervoltage and overvolt-
age thresholds are calculated from the above equations. For
example, for resistor values R1 = 86.6kΩ, R2 = 2.10kΩ and
R3 = 1.40kΩ the computed thresholds are:
UVLO turn-off = 32.2V
UVLO turn-on = 34.2V
OVP turn-on = 78.4V
OVP turn-off = 80.5V
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Applications Information (Continued)
20177536
FIGURE 13. Remote Standby and Disable Control
To maintain the threshold’s accuracy, a resistor tolerance of
1% or better is recommended.
FAULT PROTECTION
The Over Voltage Protection (OVP) comparator of the
LM5035 can be configured for line or load fault protection or
thermal protection using an external temperature sensor or
thermistor. Figure 11 shows a line over voltage shutdown
application using a voltage divider between the input power
supply, VPWR, and AGND to monitor the line voltage.
The design process starts with the choice of the voltage
difference between the UVLO enabling and disabling thresh-
olds. This will also approximately set the difference between
OVP enabling and disabling regulation:
Figure 14 demonstrates the use of the OVP pin for latched
output over-voltage fault protection, using a zener and opto-
coupler. When VOUT exceeds the conduction threshold of
the opto-coupler diode and zener, the opto-coupler momen-
tarily turns on Q1 and the LM5035 enters standby mode,
disabling the drivers and enabling the hysteresis current
source on the OVP pin. Once the current source is enabled,
the OVP voltage will remain at 2.3V (23µA x 100kΩ) without
additional drive from the external circuit. If the opto-coupler
transistor emitter were directly connected to the OVP pin,
then leakage current in the zener diode amplified by the
opto-coupler’s gain could falsely trip the protection latch. R1
and Q1 are added reduce the sensitivity to low level currents
in the opto-coupler. Using the values of Figure 14, the opto-
coupler collector current must equal VBE(Q1) / R1 = 350µA
before OVP latches. Once the controller has switched to
standby mode, the outputs no longer switch but the VCC and
REF regulators continue functioning and supply bias to the
external circuitry. VCC must fall below 6.2V or the UVLO pin
must fall below 0.4V to clear the OVP latch.
Next, the combined resistance of R2 and R3 is calculated by
choosing the threshold for the UVLO disabling threshold:
Then R3 is determined by selecting the OVP disabling
threshold:
Finally, R3 is subtracted from RCOMBINED to give R2:
R2 = RCOMBINED - R3
Remote configuration of the controller’s operational modes
can be accomplished with open drain device(s) connected to
the UVLO pin as shown in Figure 13.
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22
Applications Information (Continued)
20177537
FIGURE 14. Latched Load Over-Voltage Protection
Figure 15 shows an application of the OVP comparator for
Remote Thermal Protection using a thermistor (or multiple
thermistors) which may be located near the main heat
sources of the power supply. The negative temperature co-
efficient (NTC) thermistor is nearly logarithmic, and in this
example a 100kΩ thermistor with the β material constant of
4500 kelvins changes to approximately 2kΩ at 130˚C. Set-
ting R1 to one-third of this resistance (665Ω) establishes
130˚C as the desired trip point (for VREF = 5V). In a tempera-
ture band from 20˚C below to 20˚C above the OVP thresh-
old, the voltage divider is nearly linear with 25mV per˚C
sensitivity.
R2 provides temperature hysteresis by raising the OVP com-
parator input by R2 x 23µA. For example, if a 22kΩ resistor
is selected for R2, then the OVP pin voltage will increase by
22kΩ x 23µA = 506mV. The NTC temperature must therefore
fall by 506mV / 25mV per˚C = 20˚C before the LM5035
switches from the standby mode to the normal mode.
20177538
FIGURE 15. Remote Thermal Protection
HICCUP MODE CURRENT LIMIT RESTART (RES)
The basic operation of the hiccup mode current limit restart
is described in the functional description. The delay time to
restart is programmed with the selection of the RES pin
capacitor CRES as illustrated in Figure 15.
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Applications Information (Continued)
20177516
FIGURE 16. Hiccup Over-Load Restart Timing
In the case of continuous cycle-by-cycle current limit detec-
tion at the CS pin, the time required for CRES to reach the
2.5V hiccup mode threshold is:
Printed Circuit Board Layout
The LM5035 Current Sense and PWM comparators are very
fast, and respond to short duration noise pulses. The com-
ponents at the CS, COMP, SS, OVP, UVLO, DLY and the RT
pins should be as physically close as possible to the IC,
thereby minimizing noise pickup on the PC board tracks.
Layout considerations are critical for the current sense filter.
If a current sense transformer is used, both leads of the
transformer secondary should be routed to the sense filter
components and to the IC pins. The ground side of the
transformer should be connected via a dedicated PC board
track to the AGND pin, rather than through the ground plane.
For example, if CRES = 0.01µF the time t1 is approximately
1.14 ms.
The cool down time, t2 is set by the soft-start capacitor (CSS
and the internal 1µA SS current source, and is equal to:
)
If the current sense circuit employs a sense resistor in the
drive transistor source, low inductance resistors should be
used. In this case, all the noise sensitive, low-current ground
tracks should be connected in common near the IC, and then
a single connection made to the power ground (sense resis-
tor ground point).
If CSS = 0.01 µF t2 is )10 ms.
The soft-start time t3 is set by the internal 55µA current
source, and is equal to:
The gate drive outputs of the LM5035 should have short,
direct paths to the power MOSFETs in order to minimize
inductance in the PC board traces. The SR control outputs
should also have minimum routing distance through the
pulse transformers and through the secondary gate drivers
to the sync FETs.
The two ground pins (AGND, PGND) must be connected
together with a short, direct connection, to avoid jitter due to
relative ground bounce.
If CSS = 0.01 µF t3 is )730µs.
The time t2 provides a periodic cool-down time for the power
converter in the event of a sustained overload or short
circuit. This off time results in lower average input current
and lower power dissipation within the power components. It
is recommended that the ratio of t2 / (t1 + t3) be in the range
of 5 to 10 to take advantage of this feature.
If the internal dissipation of the LM5035 produces high junc-
tion temperatures during normal operation, the use of mul-
tiple vias under the IC to a ground plane can help conduct
heat away from the IC. Judicious positioning of the PC board
within the end product, along with use of any available air
flow (forced or natural convection) will help reduce the junc-
tion temperatures. If using forced air cooling, avoid placing
the LM5035 in the airflow shadow of tall components, such
as input capacitors.
If the application requires no delay from the first detection of
a current limit condition to the onset of the hiccup mode (t1 =
0), the RES pin can be left open (no external capacitor). If it
is desired to disable the hiccup mode entirely, the RES pin
should be connected to ground (AGND).
www.national.com
24
iary winding on transformer T1 provides power to the
LM5035 VCC pin when the output is in regulation. The input
Application Circuit Example
The following schematic shows an example of a 100W half-
bridge power converter controlled by the LM5035. The op-
erating input voltage range (VPWR) is 36V to 75V, and the
output voltage is 3.3V. The output current capability is 30
Amps. Current sense transformer T2 provides information to
the CS pin for current limit protection. The error amplifier and
reference, U3 and U5 respectively, provide voltage feedback
via opto-coupler U4. Synchronous rectifiers Q4, Q5, Q6 and
Q7 minimize rectification losses in the secondary. An auxil-
voltage UVLO thresholds are )34V for increasing VPWR
,
and )32V for decreasing VPWR. The circuit can be shut
down by driving the ON/OFF input (J2) below 1.25V with an
open-collector or open-drain circuit. An external synchroniz-
ing frequency can be applied through a 100pF capacitor to
the RT input (U1 pin 5). The regulator output is current
limited at )34A.
25
www.national.com
www.national.com
26
Physical Dimensions inches (millimeters) unless otherwise noted
Molded TSSOP-20
NS Package Number MXA20A
24-Lead LLP Package
NS Package Number SQA24B
27
www.national.com
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
BANNED SUBSTANCE COMPLIANCE
National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products
Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain
no ‘‘Banned Substances’’ as defined in CSP-9-111S2.
Leadfree products are RoHS compliant.
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Support Center
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Fax: +49 (0) 180-530 85 86
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