LM3880MF-1AD [NSC]
Power Sequencer; 电源定序器
| 型号： | LM3880MF-1AD |
| 厂家： | 
National Semiconductor |
| 描述： | Power Sequencer |
| 文件： | 总12页 (文件大小：260K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
March 2007
LM3880
Power Sequencer
General Description
The LM3880 Power Sequencer offers the easiest method to
control power up and power down of multiple power supplies
(switchers or linear regulators). By staggering the startup se-
quence, it is possible to avoid latch conditions or large in-rush
currents that can affect the reliability of the system.
Features
Easiest method to sequence rails
■
■
■
■
■
■
■
Power up and power down control
Input voltage range of 2.7V to 5.5V
Small footprint SOT23-6
Low quiescent current of 25 µA
Available in a SOT23-6 package, the Power Sequencer con-
tains a precision enable pin and three open drain output flags.
Upon enabling the LM3880 the three output flags will sequen-
tially release, after individual time delays, permitting the con-
nected power supplies to startup. The output flags will follow
a reverse sequence during power down to avoid latch condi-
tions.
Standard timing options available
Customization of timing and sequence available through
factory programmability
Applications
Multiple supply sequencing
■
■
■
Standard timing option of 30ms is available.
Microprocessor / Microcontroller sequencing
EPROM capability allows every delay and sequence to be
fully adjustable. Contact National Semiconductor if a non-
standard configuration is required.
FPGA sequencing
Typical Application Circuit
20192601
© 2007 National Semiconductor Corporation
201926
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Connection Diagram
20192602
Top View
SOT23–6 Package
Pin Descriptions
Pin #
Name
VCC
Function
Input supply
Ground
1
2
3
4
5
6
GND
EN
Precision enable pin
Open drain output #3
Open drain output #2
Open drain output #1
FLAG3
FLAG2
FLAG1
Ordering Information
20192603
Sequence Designator Table
Sequence Number
Flag Order
Power Up
1 - 2 - 3
1 - 2 - 3
1 - 2 - 3
1 - 2 - 3
1 - 2 - 3
1 - 2 - 3
Power Down
3 - 2 - 1
1
2
3
4
5
6
3 - 1 - 2
2 - 3 - 1
2 - 1 - 3
1 - 3 - 2
1 - 2 - 3
See timing diagrams for more information
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2
Timing Designator Table
td3
Timing
td1
td2
td4
td5
td6
Designator
AA
AB
AC
AD
10ms
30ms
60ms
120ms
10ms
30ms
60ms
120ms
10ms
30ms
60ms
120ms
10ms
30ms
60ms
120ms
10ms
30ms
60ms
120ms
10ms
30ms
60ms
120ms
See timing diagrams for more information
LM3880 Ordering Information
Sequence
Timer settings
NSC
Package
Drawing
Order
Number
Package
Type
Package
Marking
Order
Supplied As
td1
td2
td3
td4
td5
td6
LM3880
MF-1AA
10ms
10ms
30ms
30ms
60ms
60ms
10ms
10ms
30ms
30ms
60ms
60ms
10ms
10ms
30ms
30ms
60ms
60ms
10ms
10ms
30ms
30ms
60ms
60ms
10ms
10ms
30ms
30ms
60ms
60ms
10ms
10ms
30ms
30ms
60ms
60ms
1
1
1
1
1
1
1
1
1k units T&R
3k units T&R
1k units T&R
3k units T&R
1k units T&R
3k units T&R
1k units T&R
3k units T&R
F20A
F20A
F21A
F21A
F22A
F22A
F23A
F23A
LM3880
MFX-1AA
LM3880
MF-1AB
LM3880
MFX-1AB
SOT23-6
MF06A
LM3880
MF-1AC
LM3880
MFX-1AC
LM3880
MF-1AD
120ms 120ms 120ms 120ms 120ms 120ms
120ms 120ms 120ms 120ms 120ms 120ms
LM3880
MFX-1AD
Non-standard parts are available upon request. Please contact National Semiconductor for more information.
3
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Absolute Maximum Ratings (Note 1)
Operating Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VCC to GND
2.7V to 5.5V
−0.3V to VCC + 0.3V
−40°C to +125°C
EN, FLAG1, FLAG2, FLAG3
Junction Temperature
VCC
−0.3V to +6.0V
−0.3V to 6.0V
50 mA
EN, FLAG1, FLAG2, FLAG3
Max Flag 'ON' Current
Storage Temperature Range
Junction Temperature
−65°C to +150°C
150°C
Lead Temperature (Soldering, 5
sec.)
Minimum ESD Rating
260°C
±2 kV
Electrical Characteristics Specifications with standard typeface are for TJ = 25°C, and those in bold face type
apply over the full Operating Temperature Range (TJ = -40°C to +125°C). Minimum and Maximum limits are guaranteed through
test, design or statistical correlation. Typical values represent the most likely parametric norm at TJ = 25°C and are provided for
reference purposes only. Unless otherwise specified VCC = 3.3V.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
(Note 3) (Note 4) (Note 3)
IQ
Operating Quiescent current
25
1
80
µA
Open Drain Flags
IFLAG
FLAGx Leakage Current
VFLAGx = 3.3V
20
nA
V
VOL
FLAGx Output Voltage Low
IFLAGx = 1.2mA
0.4
Power Up Sequence
td1
td2
td3
Timer delay 1 accuracy
Timer delay 2 accuracy
Timer delay 3 accuracy
-15
-15
-15
15
15
15
%
%
%
Power Down Sequence
td4
Timer delay 4 accuracy
-15
-15
-15
_
15
15
15
%
%
%
td5
td6
Timer delay 5 accuracy
Timer delay 6 accuracy
Timing Delay Error
(td(x) – 400 us) / td(x+1) Ratio of timing delays
For x = 1 or 4
For x = 2 or 5
95
95
105
105
%
%
td(x) / td(x+1)
ENABLE Pin
VEN
Ratio of timing delays
EN pin threshold
1.0
1.25
7
1.4
V
IEN
EN pin pull-up current
VEN = 0V
µA
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
intended to be functional, but does not guarantee specific performance limits. For guaranteed specifications and conditions, see the Electrical Characteristics.
Note 2: The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin.
Note 3: Limits are 100% production tested at 25°. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control
(SQC) methods. The limits are used to calculate National's Average Outgoing Quality Level (AOQL).
Note 4: Typical numbers are at 25°C and represent the most likely parametric norm.
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4
Typical Performance Characteristics
Quiescent Current vs VCC
Quiescent Current vs Temperature (VCC = 3.3V)
20192605
20192604
Enable Threshold vs Temperature
Time Delay (30ms) vs VCC
20192606
20192607
Time Delay Ratio vs Temperature
Time Delay (30ms) vs Temperature
20192609
20192608
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FLAG VOL vs VCC
FLAG Voltage vs Current
(RFLAG = 100 kΩ)
20192611
20192610
Block Diagram
Block Diagram
20192612
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Timing Diagrams (Sequence 1)
All standard options use this sequence for output flags rise and fall order.
20192613
Power Up Sequence
20192614
Power Down Sequence
Application Information
OVERVIEW
appropriate delays. The three timers that are used to control
the power down scheme can also be individually programmed
and are completely independent of the power up timers.
The LM3880 Power Sequencer provides an easy solution for
sequencing multiple rails in a controlled manner. Six inde-
pendent timers are integrated to control the timing sequence
(power up and power down) of three open drain output flags.
These flags permit connection to either a shutdown / enable
pin of linear regulators and switchers to control the power
supplies’ operation. This allows a complete power system to
be designed without worrying about large in-rush currents or
latch-up conditions that can occur.
Additional sequence patterns are also available in addition to
customizable timers. For more information see the custom
sequencer section.
PART OPERATION
The timing sequence of the LM3880 is controlled by the as-
sertion of the enable signal. The enable pin is designed with
an internal comparator, referenced to a bandgap voltage
(1.25V), to provide a precision threshold. This allows a de-
layed timing to be externally set using a capacitor or to start
the sequencing based on a certain event, such as a line volt-
age reaching 90% of nominal. For an additional delayed
sequence from the rail powering VCC, simply attach a ca-
pacitor to the EN pin as shown below.
The timing sequence of the LM3880 is controlled entirely by
the enable (EN) pin. Upon power up, all the flags are held low
until this precision enable is pulled high. After the EN pin is
asserted, the power up sequence will commence. An internal
counter will delay the first flag (FLAG1) from rising until a fixed
time period has expired. Upon the release of the first flag an-
other timer will begin to delay the release of the second flag
(FLAG2). This process repeats until all three flags have se-
quentially been released. The three timers that control the
delays are all independent of each other and can be individ-
ually programmed if needed. (See custom sequencer sec-
tion).
The power down sequence is the same as power-up, but in
reverse. When EN pin is de-asserted a timer will begin that
delays the third flag (FLAG3) from pulling low. The second
and first flag will then follow in a sequential manner after their
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A resistor divider can also be used to enable the LM3880
based on a certain voltage threshold. Care needs to be taken
when sizing the resistor divider to include the effects of the
internal current source.
One of the features of the enable pin is that it provides glitch
free operation. The first timer will start counting at a rising
threshold, but will always reset if the enable pin is de-asserted
before the first output flag is released. This can be shown in
the timing diagram below:
20192615
Cap Timing
Using the internal pull-up current source to charge the exter-
nal capacitor (CEN) the enable pin delay can be calculated by
the equation below:
20192617
EN Glitch
If the enable signal remains high for the entire power-up se-
quence, then the part will operate as shown in the standard
timing diagrams. However, if the enable signal is de-asserted
before the power-up sequence is completed the part will enter
a controlled shutdown. This allows the system to walk through
a controlled power cycling, preventing any latch conditions
from occuring. This state only occurs if the enable pin is de-
asserted after the completion of timer 1, but before the entire
power-up sequence is completed.
When this event occurs, the falling edge of enable pin resets
the current timer and will allow the remaining power-up cycle
to complete before beginning the power down sequence. The
power down sequence starts approximately 120ms after the
final power-up flag. This allows output voltages in the system
to stabilize before everything is shutdown. An example of this
operation can be seen below:
20192618
Incomplete Sequence
All the internal timers are generated by a master clock that
has an extremely low tempco. This allows for tight accuracy
across temperature and a consistent ratio between the indi-
vidual timers. There is a slight additional delay of approxi-
mately 400 µs to timers 1 and 4 which is a result of the
EPROM refresh. This refresh time is in addition to the pro-
grammed delay time and will be almost insignificant to all but
the shortest of timer delays.
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8
CUSTOM SEQUENCER
tity. Please contact National Semiconductor for more infor-
mation.
The LM3880 Power Sequencer is based on a CMOS process
utilizing an EPROM that has the capability to be custom pro-
grammed at the factory. Approximately 500,000,000 different
options are available allowing even the most complex system
to be simply sequenced. Because of the vast options that are
possible, customization is limited to orders of a certain quan-
The variables that can be programmed include the six delay
timers and the reverse sequence order. For the timers, each
can be individually selected from one of the timer selector
columns in the table shown below. However, all six time de-
lays must be from the same column.
Timer Options 1
Timer Options 2
Timer Options 3
Timer Options 4
0
0
0
0
8
2
4
6
4
8
12
18
24
30
36
42
48
54
60
66
72
78
84
90
16
24
32
40
48
56
64
72
80
88
96
104
112
120
6
12
16
20
24
28
32
36
40
44
48
52
56
60
8
10
12
14
16
18
20
22
24
26
28
30
All times listed are in milliseconds
The sequencing order for power up is always controlled by
layout. The flag number translates directly into the sequence
order during power up (ie FLAG1 will always be first). How-
ever, for some systems a different power down order could
be required. To allow flexibility for this aspect in a design, the
Power Sequencer incorporates six different options for con-
trolling the power down sequence. These options can be seen
in the timing diagrams on the next page. This ability can be
programmed in addition to the custom timers.
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20192619
Power Down Sequence Options
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10
Physical Dimensions inches (millimeters) unless otherwise noted
SOT23-6 Package
NS Package Number MF06A
11
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