LM3528_技术文档

August 3, 2008

LM3528

High Efficiency, Multi Display LED Driver with 128

Exponential Dimming Steps and Integrated OLED Power

Supply in a 1.2mm × 1.6mm µSMD Package

General Description

Features

The LM3528 current mode boost converter offers two sepa-

rate outputs. The first output (MAIN) is a constant current sink

for driving series white LED’s. The second output (SUB/FB)

is configurable as a constant current sink for series white LED

bias, or as a feedback pin to set a constant output voltage for

powering OLED panels.

128 Exponential Dimming Steps

■

Programmable Auto-Dimming Function

Up to 90% Efficient

Low Profile 12 Bump µ-SMD Package (1.2mm x 1.6mm x

0.6mm)

Integrated OLED Display Power Supply and LED Driver

■

As a dual output white LED bias supply, the LM3528 adap-

tively regulates the supply voltage of the LED strings to max-

imize efficiency and insure the current sinks remain in

regulation. The maximum current per output is set via a single

external low power resistor. An I²C compatible interface al-

lows for independent adjustment of the LED current in either

output from 0 to max current in 128 exponential steps. When

configured as a white LED + OLED bias supply the LM3528

can independently and simultaneously drive a string of up to

6 white LED’s and deliver a constant output voltage of up to

21V for OLED panels.

Programmable Pattern Generator Output for LED

Indicator Function

Drives up to 12 LED’s at 20mA

■

Drives up to 5 LED’s at 20mA and delivers 18V at 40mA

1% Accurate Current Matching Between Strings

Internal Soft-Start Limits Inrush Current

True Shutdown Isolation for LED’s

Wide 2.5V to 5.5V Input Voltage Range

22V Over-Voltage Protection

Output over-voltage protection shuts down the device if

V_OUTrises above 22V allowing for the use of small sized low

voltage output capacitors. Other features include a dedicated

general purpose I/O (GPIO) and a multi-function pin (HWEN/

PGEN/GPIO) which can be configured as a 32 bit pattern

generator, a hardware enable input, or as a GPIO. When

configured as a pattern generator, an arbitrary pattern is pro-

grammed via the I²C compatible interface and output at

HWEN/PGEN/GPIO for indicator LED flashing or for external

logic control. The LM3528 is offered in a tiny 12-bump µSMD

package and operates over the -40°C to +85°C temperature

range.

1.25MHz Fixed Frequency Operation

Dedicated Programmable General Purpose I/O

■

Active Low Hardware Reset

Applications

Dual Display LCD Backlighting for Portable Applications

■

Large Format LCD Backlighting

OLED Panel Power Supply

Display Backlighting with Indicator Light

30020563

Typical PCB Layout

30020501

Typical Application Circuit

300205

www.national.com

Connection Diagram

Top View

30020502

12-Bump (1.215mm × 1.615mm × 0.6mm) TMD12AAA

Ordering Information

Order Number

LM3528TME

LM3528TMX

Package Type

NSC Package Drawing Top Mark

Supplied As

12-Bump µSMD

TMD12AAA

SE

250 units, Tape-and-Reel, No Lead

3000 units, Tape-and-Reel, No Lead

Pin Descriptions/Functions

Name

Function

A1

OVP

Over-Voltage Protection Sense Connection. Connect OVP to the positive terminal of the output

capacitor.

A2

A3

B1

B2

B3

MAIN

SUB/FB

GPIO1

SCL

Main Current Sink Input.

Secondary Current Sink Input or 1.21V Feedback Connection for Constant Voltage Output.

Programmable General Purpose I/O.

Serial Clock Input

SET

LED Current Setting Connection. Connect a resistor from SET to GND to set the maximum LED

current into MAIN or SUB/FB (when in LED mode), where I_{LED_MAX}= 192×1.244V/R_SET

.

C1

HWEN/PGEN/ Active High Hardware Enable Input. Programmable Pattern Generator Output, and Programmable

GPIO

SDA

IN

General Purpose I/O.

C2

C3

Serial Data Input/Output

Input Voltage Connection. Connect IN to the input supply, and bypass to GND with a 1µF ceramic

capacitor.

D1

D2

D3

VIO

SW

Logic Voltage Level Input

Drain Connection for Internal NMOS Switch

Ground

GND

www.national.com

2

Absolute Maximum Ratings (Notes 1, 2)

Operating Ratings (Notes 1, 2)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

V_IN

2.5V to 5.5V

0V to 23V

V_SW, V_OVP

,

V_SUB/FB, V_MAIN

0V to 21V

V_IN

−0.3V to 6V

−0.3V to 25V

−0.3V to 23V

Junction Temperature Range

(T_J)(Note 4)

-40°C to +110°C

V_SW, V_OVP

,

V_SUB/FB, V_MAIN

Ambient Temperature Range

(T_A)(Note 5)

-40°C to +85°C

68°C/W

V_SCL, V_SDA, V_RESET\GPIO, V_IO

V_SET

Continuous Power Dissipation

,

−0.3V to 6V

Internally Limited

+150°C

Thermal Properties

Junction to Ambient Thermal

Junction Temperature (T_J-MAX

)

Storage Temperature Range

-65°C to +150°C

Resistance (θ_JA)(Note 6)

Maximum Lead Temperature

(Soldering, 10s)(Note 3)

ESD Rating(Note 10)

Human Body Model

+300°C

2.5kV

ESD Caution Notice

National Semiconductor recommends that all integrated cir-

cuits be handled with appropriate ESD precautions. Failure to

observe proper ESD handling techniques can result in dam-

age to the device.

Electrical Characteristics

Specifications in standard type face are for T_A= 25°C and those in boldface type apply over the Operating Temperature Range

of T_A= −40°C to +85°C. Unless otherwise specified V_IN= 3.6V, V_IO= 1.8V, V_RESET/GPIO= V_IN, V_SUB/FB= V_MAIN= 0.5V, R_SET

=

12.0kΩ, OLED = ‘0’, ENM = ENS = ‘1’, BSUB = BMAIN = Full Scale.(Notes 2, 7)

Symbol

Parameter

Conditions

Min

Typ

Max

22

Units

I_LED

Output Current Regulation UNI = ‘0’, or ‘1’,

MAIN or SUB/FB Enabled 2.5V < V_IN< 5.5V

18.5

20

Maximum Current Per

R_SET= 8.0kΩ

mA

30

Current Sink

I_LED-MATCH

I_MAINto I_SUB/FBCurrent

Matching

UNI = ‘1’,

2.5V < V_IN< 5.5V (Note 11)

0.15

1.244

192

1

%

V

V_SET

SET Pin Voltage

3.0V < V_IN< 5V

I_LED/I_SET

I_LEDCurrent to I_SETCurrent

Ratio

V_{REG_CS}

V_{REG_OLED}

V_HR

Regulated Current Sink

Headroom Voltage

500

1.21

300

mV

V

V_SUB/FBRegulation Voltage 2.5V < V_IN< 5.5V, OLED = ‘1’

in OLED Mode

1.170

1.237

Current Sink Minimum

Headroom Voltage

I_LED= 95% of nominal

mV

R_DSON

NMOS Switch On

Resistance

I_SW= 100mA

0.43

770

22

Ω

I_CL

NMOS Switch Current Limit 2.5V < V_IN< 5.5V

645

900

23

mA

V_OVP

Output Over-Voltage

Protection

ON Threshold,

2.5V < V_IN< 5.5V

20.6

V

OFF Threshold,

2.7V < V_IN< 5.5V

19.25

1.0

20.6

21.5

1.4

f_SW

Switching Frequency

Maximum Duty Cycle

Minimum Duty Cycle

1.27

90

MHz

%

D_MAX

D_MIN

10

%

3

www.national.com

Symbol

Parameter

Conditions

Min

Typ

Max

390

Units

I_Q

Quiescent Current, Device V_MAINand V_SUB/FB

Not Switching

>

V_{REG_CS}

,

350

BSUB = BMAIN = 0x00, 2.5V

< V_IN< 5.5V

µA

V_SUB/FB> V_{REG_OLED}

,

OLED=’1’, ENM=ENS=’0’,

R_SETOpen,

250

1.8

260

3

2.5V < V_IN< 5.5V

I_SHDN

Shutdown Current

ENM = ENS = OLED = '0',

2.5V < V_IN< 5.5V

µA

V

HWEN/PGEN/GPIO, GPIO1 Pin Voltage Specifications

V_IL

Input Logic Low

Input Logic High

Output Logic Low

2.5V < V_IN<5.5V, MODE bit

0.5

= 0

V_IH

V_OL

2.5V < V_IN< 5.5V, MODE bit

= 0

1.1

V

I_LOAD=3mA, MODE bit = 1

400

mV

I²C Compatible Voltage Specifications (SCL, SDA, VIO)

V_IO

V_IL

Serial Bus Voltage Level

Input Logic Low

2.5V < V_IN< 5.5V (Note 9)

2.5V < V_IN< 5.5V

I_LOAD= 3mA

V_IN

1.7

V

0.36×V_IO

V_IH

V_OL

Input Logic High

0.7×V_IO

V

Output Logic Low

400

mV

I²C Compatible Timing Specifications (SCL, SDA, VIO, see Figure 1) (Notes 8, 9)

t₁

t₂

SCL Clock Period

2.5

µs

ns

Data In Setup Time to SCL

High

100

t₃

Data Out Stable After SCL

Low

0

ns

SDA Low Setup Time to

SCL Low (Start)

t₄

100

t₅

SDA High Hold Time After

SCL High (Stop)

Note 1: Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the device is intended

to be functional, but device parameter specifications may not be guaranteed. For guaranteed specifications and test conditions, see the Electrical Characteristics.

Note 2: All voltages are with respect to the potential at the GND pin.

Note 3: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1112: Micro SMD Wafer LEvel Chip Scale

Package (AN-1112).

Note 4: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at T_J=+150°C (typ.) and disengages at

T_J=+140°C (typ.).

Note 5: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be

derated. Maximum ambient temperature (T_A-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = +105°C), the maximum power

dissipation of the device in the application (P_D-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θ_JA), as given by the

following equation: T_A-MAX= T_J-MAX-OP– (θ_JA× P_D-MAX).

Note 6: Junction-to-ambient thermal resistance (θ_JA) is taken from a thermal modeling result, performed under the conditions and guidelines set forth in the

JEDEC standard JESD51-7. The test board is a 4-layer FR-4 board measuring 114.3mm x 76.2mm x 1.6mm. The ground plane on the board is 113mm x 75mm.

Thickness of copper layers are 71.5µm/35µm/35µm/71.5µm (2oz/1oz/1oz/2oz). Ambient temperature in simulation is 22°C, still air. Power dissipation is 1W. For

more information on these topics, please refer to National Semiconductor Application Note 1112, and JEDEC Standard JESD51-7.

Note 7: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical (Typ) numbers are not guaranteed, but represent the most likely norm.

Note 8: SCL and SDA must be glitch-free in order for proper brightness control to be realized.

Note 9: SCL and SDA signals are referenced to VIO and GND for minimum VIO voltage testing. VIO limits indicate the minimum voltage at VIO at which the part

is operational.

Note 10: The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7).

Note 11: The matching specification between MAIN and SUB is calculated as 100 × ((I_MAINor I_SUB) - I_AVE) / I_AVE. This simplifies out to be

100 × (I_MAIN- I_SUB)/(I_MAIN+ I_SUB).

www.national.com

4

Timing Diagram

30020503

FIGURE 1. I²C Timing

5

www.national.com

Typical Performance Characteristics V_IN= 3.6V, LEDs are Nichia (NSSW008C), C_OUT= 1µF (LED

Mode), C_OUT= 2.2µF (OLED Mode), C_IN= 1µF, L = TDK VLF4012AT-100MR79, (R_L= 0.3Ω), R_SET= 12.1kΩ, UNI = '1', I_LED

=

I_SUB+ I_MAIN, T_A= +25°C unless otherwise specified.

2x6 LED Efficiency vs I_LED

(2 Strings of 6LEDs)

2x5 LED Efficiency vs I_LED

(2 Strings of 5LEDs)

30020508

30020509

2x4 LED Efficiency vs I_LED

(2 Strings of 4LEDs)

2x3 LED Efficiency vs I_LED

(2 Strings of 3LEDs)

30020510

30020511

www.national.com

6

2x2 LED Efficiency vs I_LED

(2 Strings of 2LEDs)

LED Efficiency vs V_IN

(L = TDK VLF3012AT-100MR92, R_L= 0.36Ω, I_SUB+ I_MAIN

40mA)

=

30020512

30020513

18V OLED Efficiency vs I_OUT

12V OLED Efficiency vs I_OUT

30020514

30020515

7

www.national.com

LED Line Regulation

(UNI = '0')

OLED Line Regulation

I_OLED= 60mA

30020516

30020517

OLED Line Regulation

I_OLED= 60mA

OLED Load Regulation

V_OLED= 18V

30020518

30020519

www.national.com

8

OLED Load Regulation

V_OLED= 12V

Peak Current Limit vs. V_IN

30020521

30020520

Over Voltage Limit vs. V_IN

Switch On-Resistance vs. V_IN

30020522

30020523

9

www.national.com

Switching Frequency vs. V_IN

Maximum Duty Cycle vs. V_IN

30020524

30020525

Shutdown Current vs. V_IN

Switching Supply Current vs. V_IN

30020526

30020527

www.national.com

10

LED Current Accuracy vs CODE

LED Current Matching vs. CODE (Note 11)

(UNI = '1', R_SET= 12kΩ, T_A= -40°C to +85°C)

(R_SET= 12kΩ±0.05%)

30020529

30020528

LED Current vs CODE

(I_MAIN, I_SUB, I_IDEAL, R_SET= 12kΩ±0.05%)

I_LEDvs Current Source Headroom Voltage

(V_IN= 3V, UNI = '0')

30020531

30020530

11

www.national.com

Start-Up Waveform (LED Mode)

(2 × 5 LEDs, 20mA per string)

Start-Up Waveform (OLED Mode)

(V_OUT= 18V, I_OUT= 60mA)

30020556

30020555

Channel 2: SDA (5V/div)

Channel 1: SDA (5V/div)

Channel 1: V_OUT(10V/div)

Channel 3: I_LED(20mA/div)

Channel 4: I_IN(200mA/div)

Time Base: 400µs/div

Channel 2: V_OUT(10V/div)

Channel 3: I_OUT(20mA/div)

Channel 4: I_IN(200mA/div)

Time Base: 400µs/div

Load Step (OLED Mode)

(V_OUT= 18V, C_OUT= 2.2µF)

Line Step (LED Mode)

(2 × 5 LEDs, 20mA per String, C_OUT= 1µF, V_INfrom 3V to 3.6V)

30020552

30020553

Channel 3: ISUB (5mA/div)

Channel 2: V_OUT(AC Coupled, 500mV/div)

Channel 4: IMAIN (5mA/div)

Channel 2: V_IN(AC Coupled, 500mV/div)

Time Base: 100µs/div

Channel 3: I_OUT(20mA/div)

Time Base: 200µs/div

www.national.com

12

Line Step (OLED Mode)

(V_OUT= 18V, C_OUT= 2.2µF, V_INfrom 3V to 3.6V)

HWEN Functionality

30020557

Channel 2: VOUT (AC Coupled, 100mV/div)

Channel 3: VIN (AC Coupled, 500mV/div)

Time Base: 200µs/div

30020551

Channel 4: I_SUB(20mA/div)

Channel 3: I_MAIN(20mA/div)

Channel 2: HWEN (5V/div)

Time Base: 200ns/div

GPIO1 Functionality

(GPIO1 Configured as OUTPUT, f_SCL= 360kHz)

Ramp Rate Functionality

(RMP1, RMP0 = '11')

30020554

30020558

Channel 1:SDA (2V/div)

Channel 2: GPIO (2V/div)

Channel 1: SCL (5V/div)

Channel 1:SDA (5V/div)

Time Base: 40µs/div

Channel 4: I_SUB(10mA/div)

Channel 3: ISUB (10mA/div)

Time Base: 400ms/div

13

www.national.com

Block Diagram

30020533

FIGURE 2. LM3528 Block Diagram

Operation Description

ramp while the output capacitor supplies power to the white

LED’s and/or OLED panel. The error signal at the output of

the error amplifier is compared against the sensed inductor

current. When the sensed inductor current equals the error

signal, or when the maximum duty cycle is reached, the

NMOS switch turns off causing the external Schottky diode to

pick up the inductor current. This allows the inductor current

to ramp down causing its stored energy to charge the output

capacitor and supply power to the load. At the end of the clock

period the PWM controller is again set and the process re-

peats itself.

The LM3528 Current Mode PWM boost converter operates

from a 2.7V to 5.5V input and provides two regulated outputs

for White LED and OLED display biasing. The first output,

MAIN, provides a constant current of up to 30mA to bias up

to 6 series white LED’s. The second output, SUB/FB, can be

configured as a current source for up to 6 series white LED’s

at at up to 30mA, or as a feedback voltage pin to regulate a

constant output voltage of up to 21V. When both MAIN and

SUB/FB are configured for white LED bias the current for each

LED string is controlled independently or in unison via an I²C

compatible interface. When MAIN is configured for white LED

bias and SUB/FB is configured as a feedback voltage pin, the

current into MAIN is controlled via the I²C compatible interface

and SUB/FB becomes the middle tap of a resistive divider

used to regulate the output voltage of the boost converter.

ADAPTIVE REGULATION

When biasing dual white led strings (White LED mode) the

LM3528 maximizes efficiency by adaptively regulating the

output voltage. In this configuration the 500mV reference is

connected to the non-inverting input of the error amplifier via

mux S2 (see Figure 2, Block Diagram). The lowest of either

V_MAINor V_SUB/FBis then applied to the inverting input of the

error amplifier via mux S1. This ensures that V_MAINand V_SUB/

The core of the LM3528 is a Current Mode Boost converter.

Operation is as follows. At the start of each switching cycle

the internal oscillator sets the PWM converter. The converter

turns the NMOS switch on, allowing the inductor current to

www.national.com

14

_FBare at least 500mV, thus providing enough voltage head-

room at the input to the current sinks for proper current

regulation.

conditions the output voltage will rise to the over voltage pro-

tection threshold. When this happens the controller will stop

switching causing V_OUTto droop. When the output voltage

drops below 19.7V (min) the device will resume switching. If

the device remains in an over voltage condition the LM3528

will repeat the cycle causing the output to cycle between the

high and low OVP thresholds. See waveform for OVP condi-

tion in the Typical Performance Characteristics.

In the instance when there are unequal numbers of LEDs or

unequal currents from string to string, the string with the high-

est voltage will be the regulation point.

UNISON/NON-UNISON MODE

Within White LED mode there are two separate modes of op-

eration, Unison and Non-Unison. Non-Unison mode provides

for independent current regulation, while Unison mode gives

up independent regulation for more accurate matching be-

tween LED strings. When in Non-Unison mode the LED cur-

rents I_MAINand I_SUB/FBare independently controlled via

registers BMAIN and BSUB respectively (see Brightness

Registers BMAIN and BSUB section). When in Unison mode

BSUB is disabled and both I_MAINand I_SUB/FBare controlled via

BMAIN only.

OUTPUT CURRENT ACCURACY AND CURRENT

MATCHING

The LM3528 provides both precise current accuracy (% error

from ideal value) and accurate current matching between the

MAIN and SUB/FB current sinks. Two modes of operation af-

fect the current matching between I_MAINand I_SUB/FB. The first

mode (Non-Unison mode) is set by writing a 0 to bit 2 of the

General Purpose register (UNI bit). Non-Unison mode allows

for independent programming of I_MAINand I_SUB/FBvia registers

BMAIN and BSUB respectively. In this mode typical matching

between current sinks is 1%.

START-UP

The LM3528 features an internal soft-start, preventing large

inrush currents during start-up that can cause excessive volt-

age ripple on the input. For the typical application circuits

when the device is brought out of shutdown the average input

current ramps from zero to 450mA in approximately 1.2ms.

See Start Up Plots in the Typical Performance Characteris-

tics.

Writing a 1 to UNI configures the device for Unison mode. In

Unison mode, BSUB is disabled and I_MAINand I_SUB/FBare both

controlled via register BMAIN. In this mode typical matching

is 0.15%.

LIGHT LOAD OPERATION

The LM3528 boost converter operates in three modes; con-

tinuous conduction, discontinuous conduction, and skip mode

operation. Under heavy loads when the inductor current does

not reach zero before the end of the switching period the de-

vice switches at a constant frequency. As the output current

decreases and the inductor current reaches zero before the

end of the switching cycle, the device operates in discontin-

uous conduction. At very light loads the LM3528 will enter skip

mode operation causing the switching period to lengthen and

the device to only switch as required to maintain regulation at

the output.

OLED MODE

When the LM3528 is configured for a single White LED bias

+ OLED display bias (OLED mode), the non-inverting input of

the error amplifier is connected to the internal 1.21V reference

via MUX S2. MUX S1 switches SUB/FB to the inverting input

of the error amplifier while disconnecting the internal current

sink at SUB/FB. The voltage at MAIN is not regulated in OLED

mode so when the application requires white LED + OLED

panel biasing, ensure that at least 300mV of headroom is

maintained at MAIN to guarantee proper regulation of I_MAIN

.

HARDWARE ENABLE/PATTERN GENERATOR/

GENERAL PURPOSE I/O (HWEN/PGEN/GPIO)

(see the Typical Performance Characteristics for a plot of

I_LEDvs Current Source Headroom Voltage)

HWEN/PGEN/GPIO can be configured for three different

modes of operation; Hardware Enable, Pattern Generation,

and General Purpose I/O. Register HPG at address 0x80

controls the functionality of this pin (see Table 6).

PEAK CURRENT LIMIT

The LM3528’s boost converter has a peak current limit for the

internal power switch of 770mA typical (650mA minimum).

When the peak switch current reaches the current limit the

duty cycle is terminated resulting in a limit on the maximum

output current and thus the maximum output power the

LM3528 can deliver. Calculate the maximum LED current as

a function of V_IN, V_OUT, L and I_PEAKas:

HARDWARE ENABLE (HWEN)

On initial power-up HWEN/PGEN/GPIO defaults to the Hard-

ware Enable (HWEN) state. In this mode HWEN/PGEN/GPIO

is an active high open-drain input enable to the device. When

in HWEN mode HWEN/PGEN/GPIO must be pulled up to at

least 0.7 × VIO to enable the device. In HWEN mode pulling

HWEN/PGEN/GPIO below 0.36 × VIO will shutdown the

LM3528, resetting all registers, and forcing MAIN, SUB/FB,

and SW high impedance. Bit 0 of the HPG register controls

the HWEN function. Writing a ‘0’ to this bit enables the HWEN

mode. Writing a ‘1’ to this bit disables the HWEN mode and

allows selection between the other two modes.

PATTERN GENERATOR (PGEN)

With bit 0 of the HPG register set to 1, HWEN/PGEN/GPIO

can be programmed as an open drain Pattern Generator Out-

put (PGEN). In PGEN mode a 32 bit pattern is output at

HWEN/PGEN/GPIO. This pattern can be programmed to re-

peat itself at 4 different frequencies and 6 different duty

cycles. The arbitrary pattern is programmed into four 8 bit

registers; PGEN0 (address 0x90), PGEN1 (address 0x91),

PGEN2 (address 0x92), and PGEN3 (address 0x93) (see

ƒ_SW= 1.27MHz. Typical values for efficiency and I_PEAKcan

be found in the efficiency and I_PEAKcurves in the Typical Per-

formance Characteristics.

OVER VOLTAGE PROTECTION

The LM3528's output voltage (V_OUT) is limited on the high end

by the Output Over-Voltage Protection Threshold (V_OVP) of

21.2V (min). In White LED mode during output open circuit

15

www.national.com

Figures 12 - 15). Figure 16 details an example of a 32 bit pat-

tern at a specific programmed duty cycle and frequency. A ‘1’

written to the PGEN_ registers forces HWEN/PGEN/GPIO

low. A ‘0’ causes HWEN/PGEN/GPIO to go open drain.

of the HPG register and their power-on-reset values. Note that

the logic output levels for the GPIO function of this pin are

inverted compared to the PGEN functions. For example, a 1

written to the PGEN registers cause the HWEN/PGEN/GPIO

pin to pull low while a 1 written to the bit 2 of the HPG register

causes the pin to go open drain.

Bits <5:3> in the HPG register have three functions; GPIO

enable, duty cycle select, and pattern latch. Any combination

of these bits other than ‘000’ or ’111’ puts HWEN/PGEN/GPIO

into PGEN mode at the specified duty cycle shown in Table

6. Writing a ‘111’ to bits <5:3> latches the 32 bit pattern pro-

grammed into the 4 pattern generator registers PGEN0,

PGEN1, PGEN2, PGEN3 into the internal shift register. When

bits <5:3> = ‘000’ the PGEN mode is off and HWEN/PGEN/

GPIO is configured as a GPIO.

GENERAL PURPOSE I/O (GPIO0)

The GPIO pin is a dedicated General Purpose I/O (open

drain) and is controlled via the GPIO register at address 0x81.

Bit 1 holds the logic data while bit 0 controls the logic direction

(Input or Output). Bits <7:2> are un-used and will always read

back as logic '1'. With bit 0 set to ‘0’ GPIO is configured as an

output. In this mode a ‘0’ written to bit 1 forces GPIO to a logic

low. Likewise, a ‘1’ written to bit 1 will force GPIO to logic high.

When bit 0 is set to ‘1’ GPIO is configured as a logic input. In

this mode when GPIO is externally pulled low a ‘0’ is written

to bit 1 of the GPIO register. Likewise, when GPIO is exter-

nally pulled high a ‘1’ is written to bit 2 of the HPG register.

Table 7 and Figure 11 detail the bit functions and power-on-

reset values of GPIO.

Bits <7:6> of the HPG register control the pattern frequency.

See Table 6 for the detailed breakdown of each available fre-

quency. Figure 16 details the pattern programming and figure

17 shows the pattern output at HWEN/PGEN/GPIO.

GENERAL PURPOSE I/O (GPIO1)

With bits <5:3> and bit 0 of the HPG register all set to ‘0’

HWEN/PGEN/GPIO functions as an open drain General Pur-

pose I/O. In this mode, bit 1 of the HPG register controls the

logic direction (Input or Output) and bit 2 holds the logic data.

With bit 1 set to ‘0’ HWEN/PGEN/GPIO is configured as an

output. In this mode a ‘0’ written to bit 2 forces HWEN/PGEN/

GPIO to logic low. Likewise, a ‘1’ written to bit 2 will force

HWEN/PGEN/GPIO open drain. When bit 1 is set to ‘1’

HWEN/PGEN/GPIO is configured as a logic input. In this

mode when HWEN/PGEN/GPIO is externally pulled low a ‘0’

is written to bit 2 of the HPG register. Likewise, when HWEN/

PGEN/GPIO is externally pulled high a ‘1’ is written to bit 2 of

the HPG register. Table 6 and Figure 10 detail the bit functions

During an initial GPIO write two I2C sequences (Slave I.D,

Register Address, Register Data) are required to change the

state of the GPIO pin. The first write configures the GPIO pin

as an output. The second write will change the state of the

GPIO output to the desired logic '1' or '0'.

THERMAL SHUTDOWN

The LM3528 offers a thermal shutdown protection. When the

die temperature reaches +140°C the device will shutdown

and not turn on again until the die temperature falls below

+120°C.

www.national.com

16

I²C COMPATIBLE INTERFACE

START condition and free after a STOP condition. During da-

ta transmission, the I²C master can generate repeated

START conditions. A START and a repeated START condi-

tions are equivalent function-wise. The data on SDA must be

stable during the HIGH period of the clock signal (SCL). In

other words, the state of SDA can only be changed when SCL

is LOW.

The LM3528 is controlled via an I²C compatible interface.

START and STOP conditions classify the beginning and the

end of the I²C session. A START condition is defined as SDA

transitioning from HIGH to LOW while SCL is HIGH. A STOP

condition is defined as SDA transitioning from LOW to HIGH

while SCL is HIGH. The I²C master always generates START

and STOP conditions. The I²C bus is considered busy after a

30020537

FIGURE 3. Start and Stop Sequences

I²C COMPATIBLE ADDRESS

WRITE and R/W = 1 indicates a READ. The second byte fol-

lowing the chip address selects the register address to which

the data will be written. The third byte contains the data for

the selected register.

The chip address for the LM3528 is 0110110 (36h). After the

START condition, the I²C master sends the 7-bit chip address

followed by a read or write bit (R/W). R/W= 0 indicates a

30020538

FIGURE 4. Chip Address

TRANSFERRING DATA

pulse. The LM3528 pulls down SDA during the 9th clock

pulse, signifying an acknowledge. An acknowledge is gener-

ated after each byte has been received. Figure 5 is an exam-

ple of a write sequence to the General Purpose register of the

LM3528.

Every byte on the SDA line must be eight bits long, with the

most significant bit (MSB) transferred first. Each byte of data

must be followed by an acknowledge bit (ACK). The acknowl-

edge related clock pulse (9th clock pulse) is generated by the

master. The master releases SDA (HIGH) during the 9th clock

30020539

FIGURE 5. Write Sequence to the LM3528

17

www.national.com

REGISTER DESCRIPTIONS

There are 4, 8 bit registers within the LM3528 as detailed in Table 1.

TABLE 1. LM3528 Register Descriptions

Register Name

General Purpose (GP)

Hex Address

0x10

Power -On-Value

0xC0

Brightness Main (BMAIN)

0xA0

0xE0

Brightness Sub (BSUB)

0xB0

0xE0

HWEN/PGEN/GPIO Control (HPG)

General Purpose I/O Control (GPIO)

Pattern Register 0 (PGEN0)

Pattern Register 1 (PGEN1)

Pattern Register 2 (PGEN2)

Pattern Register 3 (PGEN3)

0x80

0XF8

0x81

0xFC

0x90

0x00

0x91

0x00

0x92

0x00

0x93

0x00

GENERAL PURPOSE REGISTER (GP)

Description), and selects between White LED and OLED

mode. Figure 6 and Table 2 describes each bit available with-

in the General Purpose Register. Table 3 summarizes the

output state of the LM3528 for the different combinations of

General Purpose register settings.

The General Purpose register has four functions. It controls

the on/off state of MAIN and SUB/FB, it selects between Uni-

son or Non-Unison mode, provides for control over the rate of

change of the LED current (see Brightness Rate of Change

30020540

FIGURE 6. General Purpose Register Description

TABLE 2. General Purpose Register Bit Function

Bit

Name

Function

Power-On-Value

0

ENM

Enable MAIN. Writing a 1 to this bit enables the main current sink (MAIN).

Writing a 0 to this bit disables the main current sink and forces MAIN high

impedance.

0

1

2

ENS

UNI

Enable SUB/FB. Writing a 1 to this bit enables the secondary current sink (SUB/

FB). Writing a 0 to this bit disables the secondary current sink and forces SUB/

FB high impedance.

0

Unison Mode Select. Writing a 1 to this bit disables the BSUB register and

causes the contents of BMAIN to set the current in both the MAIN and SUB/

FB current sinks. Writing a 0 to this bit allows the current into MAIN and SUB/

FB to be independently controlled via the BMAIN and BSUB registers

respectively.

3

4

RMP0

RMP1

Brightness Rate of Change. Bits RMP0 and RMP1 set the rate of change of

the LED current into MAIN and SUB/FB in response to changes in the contents

of registers BMAIN and BSUB (see brightness rate of change description).

0

5

OLED

OLED = 0 places the LM3528 in White LED mode. In this mode both the MAIN

and SUB/FB current sinks are active. The boost converter ensures there is at

0

least 500mV at V_MAINand V_SUB/FB

.

OLED = 1 places the LM3528 in OLED mode. In this mode the boost converter

regulates V_SUB/FBto 1.244V. V_MAINis unregulated and must be > 400mV for

the MAIN current sink to maintain current regulation.

6

7

Don't Care

These are non-functional read only bits. They will always read back as a 1.

1

www.national.com

18

TABLE 3. Operational Truth Table

UNI

X

OLED

ENM

ENS

0

Result

0

1

LM3528 Disabled

1

X

MAIN and SUB/FB current sinks enabled. Current levels set by

contents of BMAIN.

1

0

1

X

1

0

1

MAIN and SUB/FB Disabled

SUB/FB current sink enabled. Current level set by BSUB.

MAIN current sink enabled. Current level set by BMAIN.

MAIN and SUB/FB current sinks enabled. Current levels set by

contents of BMAIN and BSUB respectively.

X

1

0

X

SUB/FB current sink disabled (SUB/FB configured as a feedback

pin). MAIN current sink enabled current level set by BMAIN.

SUB/FB current sink disabled (SUB/FB configured as a feedback

pin). MAIN current sink disabled.

* ENM ,ENS, or OLED high enables analog circuitry.

With the UNI bit (General Purpose register) set to 1 (Unison

mode), BSUB is disabled and BMAIN sets both I_MAINand I_SUB/

_FB. This prevents the independent control of I_MAINand I_SUB/

_FB, however matching between current sinks goes from typi-

cally 1%(with UNI = 0) to typically 0.15% (with UNI = 1). Figure

7 and Figure 8 show the register descriptions for the Bright-

ness MAIN and Brightness SUB registers. Table 4 and Figure

9 show I_MAINand/or I_SUB/FBvs. brightness data as a percent-

BRIGHTNESS REGISTERS (BMAIN and BSUB)

With the UNI bit (General Purpose register) set to 0 (Non-

Unison mode) both brightness registers (BMAIN and BSUB)

independently control the LED currents I_MAINand I_SUB/FBre-

spectively. BMAIN and BSUB are both 8 bit, but with only the

7 LSB’s controlling the current. The MSB’s is a don’t care. The

LED current control is designed to approximate an exponen-

tially increasing response of the LED current vs increasing

code in either BMAIN or BSUB (see Figure 9). Program

I_{LED_MAX}by connecting a resistor (RSET) from SET to GND,

where:

age of I_{LED_MAX}

.

30020542

FIGURE 7. Brightness MAIN Register Description

30020543

FIGURE 8. Brightness SUB Register Description

19

www.national.com

TABLE 4. I_LEDvs. Brightness Register Data

BMAIN or

BSUB

% of

I_{LED_MAX}

BMAIN or

BSUB

% of I_{LED_MAX}BMAIN or BSUB % of I_{LED_MAX}

Brightness Data

BMAIN or

BSUB

% of I_{LED_MAX}

Brightness

Data

Brightness

Data

Brightness

Data

0000000

0000001

0000010

0000011

0000100

0000101

0000110

0000111

0001000

0001001

0001010

0001011

0001100

0001101

0001110

0001111

0010000

0010001

0010010

0010011

0010100

0010101

0010110

0010111

0011000

0011001

0011010

0011011

0011100

0011101

0011110

0011111

0.000%

0.166%

0.175%

0.184%

0.194%

0.204%

0.214%

0.226%

0.237%

0.250%

0.263%

0.276%

0.291%

0.306%

0.322%

0.339%

0.356%

0.375%

0.394%

0.415%

0.436%

0.459%

0.483%

0.508%

0.535%

0.563%

0.592%

0.623%

0.655%

0.689%

0.725%

0.763%

0100000

0100001

0100010

0100011

0100100

0100101

0100110

0100111

0101000

0101001

0101010

0101011

0101100

0101101

0101110

0101111

0110000

0110001

0110010

0110011

0110100

0110101

0110110

0111011

0110111

0111000

0111001

0111010

0111011

0111100

0111101

0111111

0.803%

0.845%

0.889%

0.935%

0.984%

1.035%

1.089%

1.146%

1.205%

1.268%

1.334%

1.404%

1.477%

1.554%

1.635%

1.720%

1.809%

1.904%

2.003%

2.107%

2.217%

2.332%

2.454%

2.582%

2.716%

2.858%

3.007%

3.163%

3.328%

3.502%

3.684%

3.876%

1000000

1000001

1000010

1000011

1000100

1000101

1000110

1000111

1001000

1001001

1001010

1001011

1001100

1001101

1001110

1001111

1010000

1010001

1010010

1010011

1010100

1010101

1010110

1010111

1011000

1011001

1011010

1011011

1011100

1011101

1011110

1011111

4.078%

4.290%

4.514%

4.749%

4.996%

5.257%

5.531%

5.819%

6.122%

6.441%

6.776%

7.129%

7.501%

7.892%

8.303%

8.735%

9.191%

9.669%

10.173%

10.703%

11.261%

11.847%

12.465%

13.114%

13.797%

14.516%

15.272%

16.068%

16.905%

17.786%

18.713%

19.687%

1100000

1100001

1100010

1100011

1100100

1100101

1100110

1100111

1101000

1101001

1101010

1101011

1101100

1101101

1101110

1101111

1110000

1110001

1110010

1110011

1110100

1110101

1110110

1110111

1111000

1111001

1111010

1111011

1111100

1111101

1111110

1111111

20.713%

21.792%

22.928%

24.122%

25.379%

26.701%

28.092%

29.556%

31.096%

32.716%

34.420%

36.213%

38.100%

40.085%

42.173%

44.371%

46.682%

49.114%

51.673%

54.365%

57.198%

60.178%

63.313%

66.611%

70.082%

73.733%

77.574%

81.616%

85.868%

90.341%

95.048%

100.000%

www.national.com

20

30020544

FIGURE 9. I_MAINor I_SUBvs BMAIN or BSUB Data

BRIGHTNESS RATE OF CHANGE DESCRIPTION

Step 2: Write 1 to ENM (turning on MAIN)

RMP0 and RMP1 control the rate of change of the LED cur-

rent I_MAINand I_SUB/FBin response to changes in BMAIN and/

or BSUB. There are 4 user programmable LED current rates

of change settings for the LM3528 (see Table 5).

Step 3: I_MAINramps to 20mA with a rate set by RMP0 and

RMP1. (RMP0 and RMP1 bits set the duration spent at one

brightness code before incrementing to the next).

Step 4: ENM is set to 0 before 20mA is reached, thus the LED

current fades off at a rate given by RMP0 and RMP1 without

I_MAINgoing up to 20mA.

TABLE 5. Rate of Change Bits

RMP0

RMP1

Change Rate

(t_STEP

Example 2:

)

Step 1: ENM is 1, and BMAIN has been programmed with

code 0x01. This results in a small current into MAIN.

0

1

0

1

0

1

12.75µs/step

3.25ms/step

6.5ms/step

13ms/step

Step 2: BMAIN is programmed with 0x7F (full scale current).

This causes I_MAINto ramp toward full-scale at the rate select-

ed by RMP0 and RMP1.

Step 3: Before I_MAINreaches full-scale BMAIN is programmed

with 0x30. I_MAINwill continue to ramp to full scale.

For example, if R_SET= 12.1kΩ then I_{LED_MAX}= 20mA. With

the contents of BMAIN set to 0x7F (I_MAIN= 20mA), suppose

the contents of BMAIN are changed to 0x00 resulting in

(I_MAIN= 0mA). With RMP0 =1 and RMP1 = 1 (13ms/step),

I_MAINwill change from 20mA to 0mA in 127 steps with 13ms

elapsing between steps, excluding the step from 0x7F to

0x7E, resulting in a full scale current change in 1638ms. The

total time to transition from one brightness code to another is:

Step 4: When I_MAINhas reached full-scale value it will ramp

down to the current corresponding to 0x30 at a rate set by

RMP0 and RMP1.

Example 3:

Step 1: Write to BMAIN a value corresponding to I_MAIN= 20-

mA.

Step 2: Write a 1 to both RMP0 and RMP1.

Step 3: Write 1 to ENM (turning on MAIN).

Step 4: I_MAINramps toward 20mA with a rate set by RMP0 and

RMP1. (RMP0 and RMP1 bits set the duration spent at one

brightness code before incrementing to the next).

The following 3 additional examples detail possible scenarios

when using the brightness register in conjunction with the rate

of change bits and the enable bits.

Step 5: After 1.222s I_MAINhas ramped to 19.687% of

I_{LED_MAX}(0.19687 × 20mA = 3.9374mA). Simultaneously,

RMP0 and RMP1 are both programmed with 0.

Example 1:

Step 6: I_MAINcontinues ramping from 3.9374mA to 20mA, but

at a new ramp rate of 12.75µs/step.

Step 1: Write to BMAIN a value corresponding to I_MAIN= 20-

mA.

21

www.national.com

TABLE 6. HPG Register Function

Bits 7 – 6 Bits 5 - 3 (PGEN Bit 2 (GPIO Bit 1 (GPIO

Bit 0 (HWEN

Control)

Function

(PGEN Bit Enable/Disable

Data)

Data

Period)

and Duty Cycle

Selection)

Direction)

X

0

1

HWEN/PGEN/GPIO is configured as an

active high Hardware Enable Input (HWEN)

00 = 1.6µs/ 001 = 100%

bit (625kHz)

HWEN/PGEN/GPIO is configured as a

Pattern Generator Output with the frequency

set by bits <7:6> and the duty cycle set by bits

<5:3>. (See Figure 11.)

010 = 1/2

011 = 1/3

100 = 1/4

101 = 1/6

110 = 1/12

01 = 26ms/

bit (38Hz)

10 = 52ms/

bit (19Hz)

11 = 105ms/

bit (9.5Hz)

111 = Latch Pat-

tern Into Shift Reg-

ister

Note 1

Note 2

X

000

GPIO Read

Data

1

0

1

HWEN/PGEN/GPIO is configured as a GPIO

Input. Read data from bit 2.

000

GPIO Write

Data

HWEN/PGEN/GPIO is configured as a GPIO

Output. A ‘1’ written to bit 2 will force HWEN/

PGEN/GPIO high; a 0 written to bit 2 will force

HWEN/PGEN/GPIO low.

Note 1: This represents the amount of time each programmed

bit will be present at HWEN/PGEN/GPIO. The entire pattern

period will be 32 × Bit Period.

output once followed by a dead time (HWEN/PGEN/GPIO

high impedance) equal to 1×’s the pattern period (Deadtime

= 32 × Bit_Period × (1/DutyCycle -1). For the 100% duty cycle

setting the 32 bit pattern will repeat constantly with no dead-

time.

Note 2: This duty cycle indicates the fraction of time the pat-

tern is being output at HWEN/PGEN/GPIO. For example the

1/2 duty cycle (bits <5:3> = 010) will have the 32 bit pattern

30020546

FIGURE 10. HPG Register Description

www.national.com

22

GPIO Register Function

Bits 7 - 2

GPIO Data

(Bit 1)

Data

Function

Direction

(Bit 0)

X

0

GPIO is

configured as

a GPIO input

with the input

data read

back via bit

[1]. This is the

default power

on state.

X

1

GPIO is

configured as

a logic output.

The output

logic voltage

is written to bit

[1].

30020564

FIGURE 11. GPIO Register Description

Figures 12 – 15 detail the Pattern Generator Data Registers.

These hold the 32 bit data that is output at HWEN/PGEN/

GPIO in PGEN mode. The data is output LSB first (Bit 0 of

PGEN0) and MSB last (Bit 7 of PGEN3).

30020565

FIGURE 12. PGEN0 Register Description

30020566

FIGURE 13. PGEN1 Register Description

23

www.national.com

30020567

FIGURE 14. PGEN2 Register Description

30020568

FIGURE 15. PGEN3 Register Description

Figure 16 shows a write sequence to the pattern generator

programmed to output the waveform in Figure 17. In this ex-

ample HPG register bits <7:6> = 01 (for 26ms/bit) and bits

<5:3> = 010 (for 1/2 duty cycle). The pattern data in registers

(PGEN0 – PGEN2) are all loaded with 0xAC. A ‘1’ will force

the HWEN/PGEN/GPIO output low while a ‘0’ will force

HWEN/PGEN/GPIO open drain. When set for a 26ms/bit pe-

riod the pattern will be output LSB first (PGEN0, bit 0) and

repeat every

When set for ½ duty cycle there will be a dead time (HWEN/

PGEN/GPIO high impedance) between each pattern and

equal to the pattern period. In applications where HWEN/

PGEN/GPIO is used to pull current through an indicator LED

a ‘1’ corresponds to the LED on and a ‘0’ corresponds to the

LED off.

www.national.com

24

30020569

FIGURE 16. Pattern Generation Write Sequence

30020570

FIGURE 17. Pattern Generation Output

SHUTDOWN AND OUTPUT ISOLATION

the SUB/FB current sink and force SUB/FB high impedance.

Writing a 1 to ENM or ENS turns on the MAIN and SUB/FB

current sinks respectively. When in shutdown the leakage

current into MAIN or SUB/FB is typically 1.8µA. See Typical

Performance Plots for start-up responses of the LM3528 us-

ing the ENM and ENS bits in White LED and OLED modes.

The LM3528 provides a true shutdown for either MAIN or

SUB/FB when configured as a White LED bias supply. Write

a 0 to ENM (bit 1) of the General Purpose register to turn off

the MAIN current sink and force MAIN high impedance. Write

a 0 to ENS (bit 2) of the General Purpose register to turn off

25

www.national.com

INPUT CAPACITOR SELECTION

Application Information

Choosing the correct size and type of input capacitor helps

minimize the input voltage ripple caused by the switching of

the LM3528’s boost converter. For continuous inductor cur-

rent operation the input voltage ripple is composed of 2 pri-

mary components, the capacitor discharge (delta V_Q) and the

capacitor’s equivalent series resistance (delta V_ESR). These

ripple components are found by:

LED CURRENT SETTING/MAXIMUM LED CURRENT

Connect a resistor (R_SET) from SET to GND to program the

maximum LED current (I_{LED_MAX}) into MAIN or SUB/FB. The

R_SETto I_{LED_MAX}relationship is:

where SET provides the constant 1.244V output.

OUTPUT VOLTAGE SETTING (OLED MODE)

Connect Feedback resistors from the converters output to

SUB/FB to GND to set the output voltage in OLED mode (see

R1 and R2 in the Typical Application Circuit (OLED Panel

Power Supply). First select R2 < 100kΩ then calculate R1

such that:

In the typical application circuit a 1µF ceramic input capacitor

works well. Since the ESR in ceramic capacitors is typically

less than 5mΩ and the capacitance value is usually small, the

input voltage ripple is primarily due to the capacitive dis-

charge. With larger value capacitors such as tantalum or

aluminum electrolytic the ESR can be greater than 0.5Ω. In

this case the input ripple will primarily be due to the ESR.

In OLED mode the MAIN current sink continues to regulate

the current through MAIN, however, V_MAINis no longer regu-

lated. To avoid dropout and ensure proper current regulation

the application must ensure that V_MAIN> 0.3V.

OUTPUT CAPACITOR SELECTION

The LM3528’s output capacitor supplies the LED current dur-

ing the boost converters on time. When the switch turns off

the inductor energy is discharged through the diode supplying

power to the LED’s and restoring charge to the output capac-

itor. This causes a sag in the output voltage during the on time

and a rise in the output voltage during the off time. The output

capacitor is therefore chosen to limit the output ripple to an

acceptable level depending on LED or OLED panel current

requirements and input/output voltage differentials. For prop-

er operation ceramic output capacitors ranging from 1µF to

2.2µF are required.

Table 7 lists different manufacturers for various capacitors

and their case sizes that are suitable for use with the LM3528.

When configured as a dual output LED driver a 1µF output

capacitor is adequate. In OLED mode for output voltages

above 12V a 2.2µF output capacitor is required (see Low

Output Voltage Operation (OLED) Section).

As with the input capacitor, the output voltage ripple is com-

posed of two parts, the ripple due to capacitor discharge (delta

V_Q) and the ripple due to the capacitors ESR (delta V_ESR). For

continuous conduction mode, the ripple components are

found by:

www.national.com

26

TABLE 7. Recommended Output Capacitors

Manufacturer

TDK

Part Number

Value

1µF

Case Size

0603

Voltage Rating

C1608X5R1E105M

25V

Murata

TDK

GRM39X5R105K25D539

C2012X5R1E225M

1µF

0603

2.2µF

0805

Murata

GRM219R61E225KA12

0805

INDUCTOR SELECTION

The LM3528 is designed for use with a 10µH inductor, how-

ever 22µH are suitable providing the output capacitor is in-

creased 2×. When selecting the inductor ensure that the

saturation current rating (I_SAT) for the chosen inductor is high

enough and the inductor is large enough such that at the

maximum LED current the peak inductor current is less than

the LM3528’s peak switch current limit. This is done by choos-

ing:

Values for I_PEAKcan be found in the plot of peak current limit

vs. V_INin the Typical Performance Characteristics graphs.

Table 8 shows possible inductors, as well as their corre-

sponding case size and their saturation current ratings.

TABLE 8. Recommended Inductors

Manufactur

er

Part Number

Value

Dimensions

I_SAT

DC Resistance

TDK

Coilcraft

TDK

VLF3012AT-100MR49

LPS3008-103ML

10µH

2.6mm×2.8mm×1mm

2.95mm×2.95mm×0.8mm

3.5mm×3.7mm×1.2mm

3.9mm×3.9mm×1.1mm

3.8mm×3.8mm×1.8mm

490mA

800mA

700mA

580mA

0.36Ω

0.65Ω

0.3Ω

VLF4012AT-100MR79

LPS4012-103ML

Coilcraft

TOKO

0.35Ω

0.18Ω

A997AS-100M

DIODE SELECTION

The output diode must have a reverse breakdown voltage

greater than the maximum output voltage. The diodes aver-

age current rating should be high enough to handle the

LM3528’s output current. Additionally, the diodes peak cur-

rent rating must be high enough to handle the peak inductor

current. Schottky diodes are recommended due to their lower

forward voltage drop (0.3V to 0.5V) compared to (0.6V to

0.8V) for PN junction diodes. If a PN junction diode is used,

ensure it is the ultra-fast type (trr < 50ns) to prevent excessive

loss in the rectifier. For Schottky diodes the B05030WS (or

equivalent) work well for most designs. See Table 9 for a list

of other Schottky Diodes with similar performance.

27

www.national.com

TABLE 9. Recommended Schottky Diodes

Manufacturer

Part Number

Package

Reverse

Breakdown

Voltage

Average

Current

Rating

On Semiconductor

On Semicondcuctor

On Semiconductor

Diodes Inc.

NSR0230P2T5G

NSR0230M2T5G

RB521S30T1

SDM20U30

SOD-923 (0.8mm×0.6mm×0.4mm)

SOD-723 (1mm×0.6mm×0.52mm)

SOD-523 (1.2mm×0.8mm×0.6mm)

SOD-323 (1.6mm×1.2mm×1mm)

30V

20V

200mA

0.5A

Diodes Inc.

B05030WS

Philips

BAT760

1A

OUTPUT CURRENT RANGE (OLED MODE)

OUTPUT VOLTAGE RANGE (OLED MODE)

The maximum output current the LM3528 can deliver in OLED

mode is limited by 4 factors (assuming continuous conduc-

tion); the peak current limit of 770mA (typical), the inductor

value, the input voltage, and the output voltage. Calculate the

maximum output current (I_{OUT_MAX}) using the following equa-

tion:

The LM3528's output voltage is constrained by 2 factors. On

the low end it is limited by the minimum duty cycle of 10%

(assuming continuous conduction) and on the high end it is

limited by the over voltage protection threshold (V_OVP) of 22V

(typical). In order to maintain stability when operating at dif-

ferent output voltages the output capacitor and inductor must

be changed. Refer to Table 10 for different V_OUT, C_OUT, and

L combinations.

TABLE 10. Component Values for Output Voltage

Selection

V_OUT

18V

15V

12V

9V

C_OUT

2.2µF

4.7µF

10µF

22µF

L

V_INRange

2.7V to 5.5V

2.7V to 4.5V

10µH

4.7µH

For the typical application circuit with V_OUT= 18V and assum-

ing 70% efficiency, the maximum output current at V_IN= 2.7V

will be approximately 70mA. At 4.2V due to the shorter on

times and lower average input currents the maximum output

current (at 70% efficiency) jumps to approximately 105mA.

Figure 11 shows a plot of I_{OUT_MAX}vs. V_INusing the above

equation, assuming 80% efficiency. In reality, factors such as

current limit and efficiency will vary over V_IN, temperature, and

component selection. This can cause the actual I_{OUT_MAX}to

be higher or lower.

7V

5V

30020562

FIGURE 18. Typical Maximum Output Current in OLED

Mode (assumed 80% efficiency)

www.national.com

28

APPLICATION CIRCUITS

30020561

FIGURE 19. LED Backlight + OLED Power Supply

to the PGND pin on the LM3528. This minimizes the induc-

tance in series with the output capacitor and reduces the

noise present at VOUT and at the PGND connection. This is

important due to the large di/dt into and out of COUT. The

returns for both CIN and COUT should terminate directly to

the PGND pin.

LAYOUT CONSIDERATIONS

Refer to AN-1112 for µSMD package soldering

The high switching frequencies and large peak currents in the

LM3528 make the PCB layout a critical part of the design. The

proceeding steps should be followed to ensure stable opera-

tion and proper current source regulation.

4, Connect the inductor on the top layer close to the SW pin.

There should be a low impedance connection from the induc-

tor to SW due to the large DC inductor current, and at the

same time the area occupied by the SW node should be small

so as to reduce the capacitive coupling of the high dV/dt

present at SW that can couple into nearby traces.

1, C_INshould be located on the top layer and as close to the

device as possible. The input capacitor supplies the driver

currents during MOSFET switching and can have relatively

large spikes. Connecting the capacitor close to the device will

reduce the inductance between CIN and the LM3528 and

eliminate much of the noise that can disturb the internal ana-

log circuitry.

5, Route the traces for R_SETand the feedback divider away

from the SW node to minimize the capacitance between these

nodes that can couple the high dV/dt present at SW into them.

Furthermore, the feedback divider and R_SETshould have ded-

icated returns that terminate directly to the PGND pin of the

device. This will minimize any shared current with COUT or

CIN that can lead to instability. Avoide routing the SUB/FB

node close to other traces that can see high dV/dt such as the

I2C pins. The capacitive coupling on the PCB between FB

and these nodes can disturb the output voltage and cause

large voltage spikes at VOUT.

2, Connect the anode of the Schottky diode as close to the

SW pin as possible. This reduces the inductance between the

internal MOSFET and the diode and minimizes the noise gen-

erated from the discontinuous diode current and the PCB

trace inductance that will add ringing at the SW node and filter

through to VOUT. This is especially important in VOUT mode

when designing for a stable output voltage.

3, C_OUTshould be located on the top layer to minimize the

trace lengths between the diode and PGND. Connect the

positive terminal of the output capacitor (COUT+) as close as

possible to the cathode of the diode. Connect the negative

terminal of the output capacitor (COUT-) as close as possible

6, Do not connect any external capacitance to the SET pin.

7, Refer to the LM3528 Evaluation Board as a guide for proper

layout.

29

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

12 Bump µSMD

For Ordering, Refer to Ordering Information Table

NS Package Number TMD12

X1 = 1.215mm (±0.1mm), X2 = 1.615mm (±0.1mm), X3 = 0.6mm

www.national.com

30

Notes

31

www.national.com

Notes

For more National Semiconductor product information and proven design tools, visit the following Web sites at:

Products

www.national.com/amplifiers

Design Support

Amplifiers

WEBENCH

www.national.com/webench

www.national.com/AU

Audio

www.national.com/audio

www.national.com/timing

www.national.com/adc

Analog University

App Notes

Clock Conditioners

Data Converters

Displays

www.national.com/appnotes

www.national.com/contacts

www.national.com/quality/green

www.national.com/packaging

Distributors

www.national.com/displays

www.national.com/ethernet

www.national.com/interface

www.national.com/lvds

Green Compliance

Packaging

Ethernet

Interface

Quality and Reliability www.national.com/quality

LVDS

Reference Designs

Feedback

www.national.com/refdesigns

www.national.com/feedback

Power Management

Switching Regulators

LDOs

www.national.com/power

www.national.com/switchers

www.national.com/ldo

LED Lighting

PowerWise

www.national.com/led

www.national.com/powerwise

Serial Digital Interface (SDI) www.national.com/sdi

Temperature Sensors

Wireless (PLL/VCO)

www.national.com/tempsensors

www.national.com/wireless

THE CONTENTS OF THIS DOCUMENT ARE PROVIDED IN CONNECTION WITH NATIONAL SEMICONDUCTOR CORPORATION

(“NATIONAL”) PRODUCTS. NATIONAL MAKES NO REPRESENTATIONS OR WARRANTIES WITH RESPECT TO THE ACCURACY

OR COMPLETENESS OF THE CONTENTS OF THIS PUBLICATION AND RESERVES THE RIGHT TO MAKE CHANGES TO

SPECIFICATIONS AND PRODUCT DESCRIPTIONS AT ANY TIME WITHOUT NOTICE. NO LICENSE, WHETHER EXPRESS,

IMPLIED, ARISING BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS

DOCUMENT.

TESTING AND OTHER QUALITY CONTROLS ARE USED TO THE EXTENT NATIONAL DEEMS NECESSARY TO SUPPORT

NATIONAL’S PRODUCT WARRANTY. EXCEPT WHERE MANDATED BY GOVERNMENT REQUIREMENTS, TESTING OF ALL

PARAMETERS OF EACH PRODUCT IS NOT NECESSARILY PERFORMED. NATIONAL ASSUMES NO LIABILITY FOR

APPLICATIONS ASSISTANCE OR BUYER PRODUCT DESIGN. BUYERS ARE RESPONSIBLE FOR THEIR PRODUCTS AND

APPLICATIONS USING NATIONAL COMPONENTS. PRIOR TO USING OR DISTRIBUTING ANY PRODUCTS THAT INCLUDE

NATIONAL COMPONENTS, BUYERS SHOULD PROVIDE ADEQUATE DESIGN, TESTING AND OPERATING SAFEGUARDS.

EXCEPT AS PROVIDED IN NATIONAL’S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, NATIONAL ASSUMES NO

LIABILITY WHATSOEVER, AND NATIONAL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY RELATING TO THE SALE

AND/OR USE OF NATIONAL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR

PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY

RIGHT.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR

SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF THE CHIEF EXECUTIVE OFFICER AND GENERAL

COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:

Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b) support or sustain life and

whose failure to perform when properly used in accordance with instructions for use provided in the labeling can be reasonably expected

to result in a significant injury to the user. A critical component is any component in a life support device or system whose failure to perform

can be reasonably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.

National Semiconductor and the National Semiconductor logo are registered trademarks of National Semiconductor Corporation. All other

brand or product names may be trademarks or registered trademarks of their respective holders.

For the most current product information visit us at www.national.com

National Semiconductor

Americas Technical

Support Center

Email: support@nsc.com

Tel: 1-800-272-9959

National Semiconductor Europe

Technical Support Center

Email: europe.support@nsc.com

German Tel: +49 (0) 180 5010 771

English Tel: +44 (0) 870 850 4288

National Semiconductor Asia

Pacific Technical Support Center

Email: ap.support@nsc.com

National Semiconductor Japan

Technical Support Center

Email: jpn.feedback@nsc.com

www.national.com


型号：	LM3528
厂家：	National Semiconductor
描述：	High Efficiency, Multi Display LED Driver with 128 Exponential Dimming Steps and Integrated OLED Power Supply in a 1.2mm × 1.6mm μSMD Package 高效率，多显示屏LED驱动器，带有一个1.2毫米× 1.6毫米μSMD套餐128指数调光步骤和集成OLED电源供应器驱动器
文件：	总32页 (文件大小：821K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

LM3528 [NSC]

相关型号：

LM3528TME

LM3528TME/NOPB

LM3528TMX

LM3528TMX/NOPB

LM353

LM3530

LM3530

LM3530TME-40/NOPB

LM3530TMX-40

LM3530TMX-40/NOPB

LM3530UME-25A/NOPB

LM3530UME-25ANOPB