LM1851 [NSC]
Ground Fault Interrupter; 接地故障断路器
| 型号： | LM1851 |
| 厂家： | 
National Semiconductor |
| 描述： | Ground Fault Interrupter |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1992
LM1851 Ground Fault Interrupter
General Description
Features
Y
Y
Y
Y
Y
Internal power supply shunt regulator
The LM1851 is designed to provide ground fault protection
for AC power outlets in consumer and industrial environ-
ments. Ground fault currents greater than a presettable
threshold value will trigger an external SCR-driven circuit
breaker to interrupt the AC line and remove the fault condi-
tion. In addition to detection of conventional hot wire to
ground faults, the neutral fault condition is also detected.
Externally programmable fault current threshold
Externally programmable fault current integration time
Direct interface to SCR
Operates under line reversal; both load vs line and hot
vs neutral
Y
Detects neutral line faults
Full advantage of the U.S. UL943 timing specification is tak-
en to insure maximum immunity to false triggering due to
line noise. Special features include circuitry that rapidly re-
sets the timing capacitor in the event that noise pulses intro-
duce unwanted charging currents and a memory circuit that
allows firing of even a sluggish breaker on either half-cycle
of the line voltage when external full-wave rectification is
used.
Block and Connection Diagram
TL/H/5177–1
Order Number LM1851M or LM1851N
See NS Package Number M08A or N08E
C
1995 National Semiconductor Corporation
TL/H/5177
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Soldering Information
Dual-In-Line Package (10 sec.)
Small Outline Package
Vapor Phase (60 sec.)
Infrared (15 sec.)
260 C
§
215 C
§
Supply Current
19 mA
220 C
§
Power Dissipation (Note 1)
Operating Temperature Range
Storage Temperature Range
1250 mW
See AN-450 ‘‘Surface Mounting and Their Effects on Prod-
uct Reliability’’ for other methods of soldering surface
mount devices.
b
a
40 C to 70 C
§
55 C to 150 C
§
§
b
a
§
e
e
5 mA
DC Electrical Characteristics T 25 C, I
§
A
SS
Parameter
Conditions
Min
Typ
Max
Units
Power Supply Shunt
Regulator Voltage
Pin 8, Average Value
22
26
30
V
Latch Trigger Voltage
Pin 7
15
6
17.5
7
20
8.2
2.4
240
V
V
Sensitivity Set Voltage
Output Drive Current
Pin 8 to Pin 6
Pin 1, With Fault
Pin 1, Without Fault
Pin 1, Without Fault
Pin 1, Without Fault,
0.5
1
mA
mV
X
Output Saturation Voltage
Output Saturation Resistance
100
100
Output External Current
Sinking Capability
2.0
2.0
5
mA
V
pin 1
Held to 0.3V (Note 4)
Noise Integration
Sink Current Ratio
Pin 7, Ratio of Discharge
Currents Between No Fault
and Fault Conditions
2.8
3.6
mA/mA
e
e
5 mA
AC Electrical Characteristics T 25 C, I
§
A
SS
Parameter
Conditions
Figure 1 (Note 3)
Min
Typ
Max
Units
Normal Fault Current
Sensitivity
3
5
7
mA
Normal Fault Trip Time
500X Fault,Figure 2 (Note 2)
18
18
ms
ms
Normal Fault with
Grounded Neutral Fault
Trip Time
500X Normal Fault,
2X Neutral,Figure 2 (Note 2)
Note 1: For operation in ambient temperatures above 25 C, the device must be derated based on a 125 C maximum junction temperature and a thermal resistance
§
§
of 80 C/W junction to ambient for the DIP and 162 C/W for the SO Package.
§
Note 2: Average of 10 trials.
§
Note 3: Required UL sensitivity tolerance is such that external trimming of LM1851 sensitivity will be necessary.
Note 4: This externally applied current is in addition to the internal ‘‘output drive current’’ source.
TL/H/5177–2
FIGURE 1. Normal Fault Sensitivity Test Circuit
2
Internal Schematic Diagram
TL/H/5177–3
3
Typical Performance Characteristics
Average Trip Time vs
Fault Current
Normal Fault Current
Threshold vs R
SET
s
TL/H/5177–4
Circuit Description
(Refer to Block and Connection Diagram)
The LM1851 operates from 26V as set by an internal shunt
extracts I . The presence of I during either half-cycle will
f f
cause V to go high, which in turn changes I from 3I to
e
regulator, D3. In the absence of a fault (I 0) the feedback
path status signal (V ) is correspondingly zero. Under these
f
S
1
TH
I
. Although I
TH
discharges the timing capacitor during
S
TH
conditions the capacitor discharge current, I , sits quies-
1
both half-cycles of the line, I only charges the capacitor
f
cently at three times its threshold value, I , so that noise
TH
induced charge on the timing capacitor will be rapidly re-
during the half-cycle in which I exits pin 2. Thus during one
f
half-cycle I –I
f
charges the timing capacitor, while during
TH
moved. When a fault current, I , is induced in the secondary
f
of the external sense transformer, the operational amplifier,
A1, uses feedback to force a virtual ground at the input as it
the other half-cycle I
discharges it. When the capacitor
TH
voltage reaches 17.5V, the latch engages and turns off Q3
permitting I to drive the gate of an SCR.
2
4
Application Circuits
A typical ground fault interrupter circuit is shown in Figure 2.
It is designed to operate on 120 V line voltage with 5 mA
AC
normal fault sensitivity.
start-up (S1 closure) with both a heavy normal fault and a
2X groundedneutralfaultpresent.Thissituationisshowndia-
gramatically below.
A full-wave rectifier bridge and a 15k/2W resistor are used
to supply the DC power required by the IC. A 1 mF capacitor
at pin 8 used to filter the ripple of the supply voltage and is
also connected across the SCR to allow firing of the SCR on
either half-cycle. When a fault causes the SCR to trigger,
the circuit breaker is energized and line voltage is removed
from the load. At this time no fault current flows and the IC
discharge current increases from I
to 3I
(see Circuit
TH
TH
Description and Block Diagram). This quickly resets both
the timing capacitor and the output latch. At this time the
circuit breaker can be reset and the line voltage again sup-
plied to the load, assuming the fault has been removed. A
1000:1 sense transformer is used to detect the normal fault.
The fault current, which is basically the difference current
between the hot and neutral lines, is stepped down by 1000
and fed into the input pins of the operational amplifier
through a 10 mF capacitor. The 0.0033 mF capacitor be-
tween pin 2 and pin 3 and the 200 pF between pins 3 and 4
are added to obtain better noise immunity. The normal fault
sensitivity is determined by the timing capacitor discharging
TL/H/5177–5
s
UL943 specifies 25 ms average trip time under these con-
ditions. Calculation of C based upon charging currents due
t
to normal fault only is as follows:
s
25 ms Specification
b
b
3 ms GFI turn-on time (15k and 1 mF)
8 ms Potential loss of one half-cycle due to fault current
sense of half-cycles only
current, I . I can be calculated by:
TH TH
7V
b
e
d
2
4 ms Time required to open a sluggish circuit breaker
I
(1)
TH
R
SET
At the decision point, the average fault current just equals
the threshold current, I
s
10 ms Maximum integration time that could be allowed
8 ms Value of integration time that accommodates com-
ponent tolerances and other variables
.
TH
I
f(rms)
2
e
c
c
I
0.91
(2)
I
T
TH
e
C
t
(5)
V
where I
is the rms input fault current to the operational
f(rms)
amp and the factor of 2 is due to the fact that I charges the
e
where T
V
integration time
f
e
threshold voltage
timing capacitor only during one half-cycle, while I
TH
dis-
charges the capacitor continuously. The factor 0.91 con-
verts the rms value to an average value. Combining equa-
tions (1) and (2) we have
e
I
average fault current into C
t
120 V
R
N
AC(rms)
e
c
I
7V
a
R
N
R
R
G
e
#
J
#
J
R
(3)
B
SET
c
I
0.91
f(rms)
X
ä
Y
current generated
X ä Y
For example, to obtain 5 mA(rms) sensitivity for the circuit in
Figure 2 we have:
heavy fault
portion of
fault current
shunted
7V
(swamps I
)
TH
e
e
R
1.5M X
(4)
SET
c
5 mA 0.91
around GFI
1000
1 turn
1000 turns
ä
1
2
The correct value for R
can also be determined from the
SET
c
c
c
(0.91)
(6)
characteristic curve that plots equation (3). Note that this is
an approximate calculation; the exact value of R de-
#
JY # J
X
XäY
on half-
X ä Y
average
SET
pends on the specific sense transformer used and LM1851
tolerances. Inasmuch as UL943 specifies a sensitivity ‘‘win-
dow’’ of 4 mA–6 mA, provision should be made to adjust
current
C charging
t
rms to
division of
input sense
transformer
cycles only
conversion
R
on a per-product basis.
SET
Independent of setting sensitivity, the desired integration
time can be obtained through proper selection of the timing
capacitor, C . Due to the large number of variables involved,
therefore:
t
proper selection of C is best done empirically. The following
t
design example, then should only be used as a guideline.
120
500
0.4
1
1
c
c
c
c
c
0.0008
(0.91)
a
1.6 0.4
1000
2
Ð# J #
J # J # J
(
e
e
C
C
(7)
t
t
17.5
Assume the goal is to meet UL943 timing requirements.
Also assume that worst case timing occurs during GF1
0.01 mF
5
Application Circuits (Continued)
in practice, the actual value of C1 will have to be modified to
include the effects of the neutral loop upon the net charging
current. The effect of neutral loop induced currents is diffi-
cult to quantize, but typically they sum with normal fault cur-
rents, thus allowing a larger value of C1.
For those GFI standards not requiring grounded neutral de-
tection, a still larger value capacitor can be used and better
noise immunity obtained. The larger capacitor can be ac-
commodated because R and R are not present, allowing
N
G
the full fault current, I, to enter the GFI.
For UL943 requirements, 0.015 mF has been found to be
the best compromise between timing and noise.
In Figure 2, grounded neutral detection is accomplished by
feeding the neutral coil with 120 Hz energy continuously and
allowing some of the energy to couple into the sense trans-
former during conditions of neutral fault.
Typical Application
*Adjust R
for desired sensitivity
TL/H/5177–6
SET
FIGURE 2. 120 Hz Neutral Transformer Approach
6
Definition of Terms
Normal Fault: An unintentional electrical path, R , between
the load terminal of the hot line and the ground, as shown
by the dashed lines.
Normal Fault plus Grounded Neutral Fault: The combina-
tion of the normal fault and the grounded neutral fault, as
shown by the dashed lines.
B
TL/H/5177–7
TL/H/5177–9
Grounded Neutral Fault: An unintentional electrical path
between the load terminal of the neutral line and the
ground, as shown by the dashed lines.
TL/H/5177–8
7
Physical Dimensions inches (millimeters)
Molded Dual-In-Line Package (N)
Order Number LM1851N
NS Package Number N08E
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