LM12L458_06 [NSC]
12-Bit + Sign Data Acquisition System with Self-Calibration; 12位+符号位数据采集系统具有自校准
| 型号： | LM12L458_06 |
| 厂家： | 
National Semiconductor |
| 描述： | 12-Bit + Sign Data Acquisition System with Self-Calibration |
| 文件： | 总29页 (文件大小：885K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 2006
LM12L458
12-Bit + Sign Data Acquisition System with
Self-Calibration
General Description
Key Specifications
The LM12L458 is a highly integrated 3.3V Data Acquisition
System. It combines a fully-differential self-calibrating (cor-
recting linearity and zero errors) 13-bit (12-bit + sign) analog-
to-digital converter (ADC) and sample-and-hold (S/H) with
extensive analog functions and digital functionality. Up to 32
consecutive conversions, using two’s complement format,
can be stored in an internal 32-word (16-bit wide) FIFO data
buffer. An internal 8-word RAM can store the conversion
sequence for up to eight acquisitions through the
LM12L458’s eight-input multiplexer. The LM12L458 can also
operate with 8-bit + sign resolution and in a supervisory
“watchdog” mode that compares an input signal against two
programmable limits. Programmable acquisition times and
conversion rates are possible through the use of internal
clock-driven timers.
(fCLK = 6 MHz)
n Resolution
n Single supply
12-bit + sign or 8-bit + sign
+3V to +5.5V
n 13-bit conversion time
n 9-bit conversion time
n 13-bit Through-put rate
n Comparison time (“watchdog” mode)
n ILE
7.3 µs
3.5 µs
106k samples/s (min)
1.8 µs (max)
1 LSB (max)
15 mW (max)
5 µW (typ)
n Power Consumption
n Stand-by mode
Features
n Three operating modes: 12-bit + sign, 8-bit + sign, and
“watchdog”
All registers, RAM, and FIFO are directly addressable
through the high speed microprocessor interface to either an
8-bit or 16-bit data bus. The LM12L458 includes a direct
memory access (DMA) interface for high-speed conversion
data transfer.
n Single-ended or differential inputs
n Built-in Sample-and-Hold
n Instruction RAM and event sequencer
n 8-channel multiplexer
n 32-word conversion FIFO
Additional applications information can be found in applica-
tions notes AN-906, AN-947 and AN-949.
n Programmable acquisition times and conversion rates
n Self-calibration and diagnostic mode
n 8- or 16-bit wide data bus microprocessor or DSP
interface
n CMOS compatible I/O
Applications
n Data Logging
n Process Control
n Energy Management
n Medical Instrumentation
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2006 National Semiconductor Corporation
DS011711
www.national.com
Connection Diagram
01171101
*Pin names in ( ) apply to the obsolete LM12L454, shown for reference only.
Order Number LM12L458CIV See NS Package Number V44A
Functional Diagram
LM12L458
01171103
Ordering Information
Guaranteed
Clock Freq
6 MHz
Guaranteed
Order
See NS
Linearity Error (max)
Part Number
LM12L458CIV
Package Number
V44A (PLCC)
1.0 LSB
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2
Absolute Maximum Ratings
Operating Ratings (Notes 1, 2)
(Notes 1, 2)
Temperature Range
Supply Voltage - VA+, VD+
|VA+ − VD+|
−40˚C ≤ TA ≤ 85˚C
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
+3.0V to +5.5V
≤100 mV
VIN+ Input Range
VIN− Input Range
VREF+ Input Voltage
VREF− Input Voltage
VREF+ − VREF−
GND ≤ VIN+ ≤ VA+
GND ≤ VIN− ≤ VA+
1V ≤ VREF+ ≤ VA+
0V ≤ VREF− ≤ VREF+ − 1V
1V ≤ VREF ≤ VA+
Supply Voltage (VA+ and VD+)
Voltage at Input and Output Pins,
except analog inputs
6.0V
−0.3V to (V+ + 0.3V)
− 5V to (V+ + 5V)
300 mV
Voltage at Analog Inputs
|(VA+) − (VD+)|
VREF Common Mode
Range (Note 16)
TJ(MAX)
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
Power Consumption (TA = 25˚C)
(Note 4)
5 mA
+
+
0.1 VA ≤ VREFCM ≤ 0.6 VA
150˚C
20 mA
875 mW
Storage Temperature
−65˚C to +150˚C
Lead Temperature,
Reliability Information - Transistor
Count
Infrared, 15 sec.
+300˚C
1.5 kV
ESD Susceptibility (Note 5)
Device
Number
12,232
15,457
4
See AN-450 “Surface Mounting Methods and Their Effect on
Product Reliability” for other methods of soldering surface
mount devices.
P-Chan MOS Transistor
N-Chan MOS Transistor
Parasitic Vertical Bipolar Junction Transistor
Parasitic Lateral Bipolar Junction Transistor
TOTAL Transistors
2
Package Thermal Resistances
27,695
Package
θJA
44-Lead PLCC
50˚C / W
Converter Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK
=
6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode volt-
age, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C. (Notes 6, 7, 8, 9)
Typical
(Note 10)
1/2
Limits
(Note 11)
1
Symbol
Parameter
Integral Linearity Error
Conditions
Units
ILE
After Auto-Cal (Notes 12, 17)
After Auto-Cal (Note 12)
After Auto-Cal (Note 12)
After Auto-Cal
LSB (max)
LSB
TUE
Total Unadjusted Error
1
Resolution with No Missing Codes
Differential Non-Linearity
Zero Error
13
1
Bits (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
LSB (max)
DNL
After Auto-Cal (Notes 13, 17)
After Auto-Cal (Notes 12, 17)
After Auto-Cal (Notes 12, 17)
(Note 14)
1/4
1/2
1/2
2
1
Positive Full-Scale Error
Negative Full-Scale Error
DC Common Mode Error
8-Bit + Sign and “Watchdog” Mode
Integral Linearity Error
3
3
4
ILE
(Note 12)
1/2
3/4
9
LSB (max)
LSB (max)
Bits (max)
LSB (max)
LSB (max)
LSB (max)
8-Bit + Sign and “Watchdog” Mode
Total Unadjusted Error
TUE
After Auto-Zero
1/2
8-Bit + Sign and “Watchdog” Mode
Resolution with No Missing Codes
8-Bit + Sign and “Watchdog” Mode
Differential Non-Linearity
8-Bit + Sign and “Watchdog” Mode
Zero Error
DNL
1
After Auto-Zero
1/2
1/2
8-Bit + Sign and “Watchdog” Full-Scale
Error
3
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Converter Characteristics (Continued)
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK
=
6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed 1.25V common-mode volt-
age, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C. (Notes 6, 7, 8, 9)
Typical
(Note 10)
Limits
(Note 11)
Symbol
Parameter
Conditions
Units
LSB
8-Bit + Sign and “Watchdog” Mode DC
Common Mode Error
1/8
Multiplexer Channel-to-Channel
Matching
0.05
LSB
GND
VA+
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
V (min)
V (max)
LSB (max)
LSB (max)
LSB
VIN+
Non-Inverting Input Range
GND
VA+
VIN−
Inverting Input Range
+
−VA
VIN+ − VIN−
Differential Input Voltage Range
Common Mode Input Voltage Range
VA+
GND
VA+
1.75
2
Zero Error
VA+ = VD+ = +3.3V 10%
VREF+ = 2.5V, VREF− = GND
0.2
0.4
0.2
85
Power Supply
Sensitivity
PSS
Full-Scale Error
Linearity Error
(Note 15)
CREF
CIN
VREF+/VREF− Input Capacitance
Selected Multiplexer Channel Input
Capacitance
pF
75
pF
Converter AC Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, 12-bit + sign conversion mode, fCLK
=
6.0 MHz, RS = 25Ω, source impedance for VREF+ and VREF− ≤ 25Ω, fully-differential input with fixed +1.25V common-mode
voltage, and minimum acquisition time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other
limits TA = TJ = 25˚C. (Notes 6, 7, 8, 9)
Typical
(Note 10)
Limits
(Note 11)
40
Symbol
Parameter
Clock Duty Cycle
Conditions
Units
% (min)
% (max)
50
60
13-Bit Resolution, Sequencer
State S5 (Figure 15)
44 (tCLK
)
)
44 (tCLK) + 50 ns
21 (tCLK) + 50 ns
9 (tCLK) + 50 ns
2 (tCLK) + 50 ns
(max)
(max)
(max)
(max)
tC
Conversion Time
Acquisition Time
9-Bit Resolution, Sequencer State
S5 (Figure 15)
21 (tCLK
Sequencer State S7 (Figure 15)
Built-in minimum for 13-Bits
Built-in minimum for 9-Bits and
“Watchdog” mode
9 (tCLK
2 (tCLK
)
tA
)
tZ
Auto-Zero Time
Sequencer State S2 (Figure 15)
Sequencer State S2 (Figure 15)
76 (tCLK
)
76 (tCLK) + 50 ns
4944 (tCLK) + 50 ns
106
(max)
(max)
tCAL
Full Calibration Time
Throughput Rate (Note 18)
“Watchdog” Mode Comparison
Time
4944 (tCLK
107
)
kHz (min)
tWD
Sequencer States S6, S4, and S5
11 (tCLK
)
11 (tCLK) + 50 ns
(max)
(Figure 15)
tPU
Power-Up Time
10
10
ms
ms
tWU
Wake-Up Time
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4
DC Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, fCLK = 6.0 MHz and minimum acquisi-
tion time unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes
6, 7, 8)
Typical
(Note 10)
0.4
Limits
(Note 11)
1.0
Symbol
ID+
Parameter
Conditions
Units
VD+ Supply Current
VA+ Supply Current
Stand-By Supply Current (ID+ +
IA+)
CS = “1”
CS = “1”
mA (max)
mA (max)
µA (max)
µA (max)
IA+
2.25
3.5
Clock Stopped
6 MHz Clock
1.5
4.5
Power-Down
IST
Mode Selected
30
ON-Channel = 3.6V
OFF-Channel = 0V
ON-Channel = 0V
OFF-Channel = 3.6V
ON-Channel = 3.6V
OFF-Channel = 0V
ON-Channel = 0V
OFF-Channel = 3.6V
0.1
0.1
0.1
0.3
0.3
0.3
µA (max)
µA (max)
µA (max)
Multiplexer ON-Channel
Leakage Current
VA+ = +3.6V
VA+ = +3.6V
Multiplexer OFF-Channel
Leakage Current
0.1
0.3
µA (max)
VIN = +3.3V
VIN = +1.65V
VIN = 0V
850
1500
2000
1500
3.0%
3.0%
3.0%
Ω
Ω
Ω
Ω
Ω
Ω
RON
Multiplexer ON-Resistance
1300
830
VIN = +3.3V
VIN = +1.65V
VIN = 0V
1.0%
1.0%
1.0%
Multiplexer
Channel-to-Channel
RON matching
Digital Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, unless otherwise specified. Boldface limits apply for TA = TJ
TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 6, 7, 8)
=
Typical
(Note 10)
Limits
(Note 11)
2.0
Symbol
VIN(1)
VIN(0)
Parameter
Logical “1” Input Voltage
Logical “0” Input Voltage
Conditions
Units
VA+ = VD+ = +3.6V
VA+ = VD+ = +3.0V
ALE, Pin 22
V (min)
V (max)
0.7
0.6
1.0
µA (max)
µA (max)
µA (max)
µA (max)
pF
IIN(1)
IIN(0)
CIN
Logical “1” Input Current
VIN = +3.3V
VIN = 0V
0.005
2.0
−1.0
−2.0
Logical “0” Input Current
−0.005
6
D0–D15 Input Capacitance
VA+ = VD+ = 3.0V
IOUT = −360 µA
IOUT = −10 µA
VA+ = VD+ = +3.0V
IOUT = 1.6 mA
IOUT = 10 µA
VOUT(1)
Logical “1” Output Voltage
2.4
V (min)
V (min)
2.85
VOUT(0)
Logical “0” Output Voltage
0.4
0.1
V (max)
V (max)
µA (max)
µA (max)
VOUT = 0V
−0.01
0.01
−3.0
3.0
IOUT
TRI-STATE® Output Leakage Current
VOUT = +3.3V
5
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Digital Timing Characteristics
The following specifications apply for VA+ = VD+ = +3.3V, tr = tf = 3 ns, and CL = 100 pF on data I/O, INT and DMARQ lines
unless otherwise specified. Boldface limits apply for TA = TJ = TMIN to TMAX; all other limits TA = TJ = 25˚C. (Notes 6, 7, 8)
Symbol (See
Figures 10, 11, 12)
Typical
(Note 10)
Limits
(Note 11)
Parameter
Conditions
Units
CS or Address Valid to ALE Low Set-Up
Time
1, 3
2, 4
40
20
ns (min)
ns (min)
CS or Address Valid to ALE Low Hold
Time
5
6
ALE Pulse Width
45
35
20
100
100
20
60
75
140
40
30
10
70
10
110
10
95
20
20
10
10
60
10
60
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
ns (max)
ns (min)
ns (min)
ns (min)
ns (min)
ns (max)
ns (min)
ns (max)
RD High to Next ALE High
ALE Low to RD Low
7
8
RD Pulse Width
9
RD High to Next RD or WR Low
ALE Low to WR Low
10
11
12
13
14
15
WR Pulse Width
WR High to Next ALE High
WR High to Next RD or WR Low
Data Valid to WR High Set-Up Time
Data Valid to WR High Hold Time
16
17
18
RD Low to Data Bus Out of TRI-STATE
RD High to TRI-STATE
30
30
30
RL = 1 kΩ
RD Low to Data Valid (Access Time)
20
21
19
Address Valid or CS Low to RD Low
Address Valid or CS Low to WR Low
Address Invalid from RD or WR High
22
23
INT High from RD Low
30
30
DMARQ Low from RD Low
Electrical Characteristics
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed
specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test
conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
<
>
(V + or V +)), the current at that pin should be limited to 5 mA.
Note 3: When the input voltage (V ) at any pin exceeds the power supply rails (V
GND or V
IN
IN
IN
A
D
The 20 mA maximum package input current rating allows the voltage at any four pins, with an input current of 5 mA, to simultaneously exceed the power supply
voltages.
Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
(maximum junction temperature), θ (package junction
JA
Jmax
to ambient thermal resistance), and T (ambient temperature). The maximum allowable power dissipation at any temperature is PD
= (T
− T )/θ or the
A
max
Jmax A JA
number given in the Absolute Maximum Ratings, whichever is lower.
Note 5: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 6: Two on-chip diodes are tied to each analog input through a series resistor, as shown below. Input voltage magnitude up to 5V above V + or 5V below GND
A
will not damage the LM12L458. However, errors in the A/D conversion can occur if these diodes are forward biased by more than 100 mV. As an example, if V +
A
is 3.0 V , full-scale input voltage must be ≤3.1 V
to ensure accurate conversions.
DC
DC
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Electrical Characteristics (Continued)
01171104
+
Note 7: V + and V + must be connected together to the same power supply voltage and bypassed with separate capacitors at each V pin to assure
A
D
conversion/comparison accuracy.
Note 8: Accuracy is guaranteed when operating at f
= 6 MHz.
CLK
Note 9: With the test condition for V
= V
− V
given as +2.5V, the 12-bit LSB is 305 µV and the 8-bit/“Watchdog” LSB is 4.88 mV.
REF−
REF
REF+
Note 10: Typical figures are at T = 25˚C and represent most likely parametric norm.
A
Note 11: Limits are guaranteed to National’s AOQL (Average Output Quality Level).
Note 12: Positive integral linearity error is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive
full-scale and zero. For negative integral linearity error the straight line passes through negative full-scale and zero. (See Figures 7, 8).
Note 13: Zero error is a measure of the deviation from the mid-scale voltage (a code of zero), expressed in LSB. It is the worst-case value of the code transitions
between −1 to 0 and 0 to +1 (see Figure 9).
Note 14: The DC common-mode error is measured with both inputs shorted together and driven from 0V to +2.5V. The measured value is referred to the resulting
output value when the inputs are driven with a 1.25V signal.
Note 15: Power Supply Sensitivity is measured after Auto-Zero and/or Auto-Calibration cycle has been completed with V + and V + at the specified extremes.
A
D
Note 16: V
(Reference Voltage Common Mode Range) is defined as (V
+ V
)/2.
REF−
REFCM
REF+
Note 17: The LM12L458’s self-calibration technique ensures linearity and offset errors as specified, but noise inherent in the self-calibration process will result in
a repeatability uncertainty of 0.10 LSB.
Note 18: The Throughput Rate is for a single instruction repeated continuously. Sequencer states 0 (1 clock cycle), 1 (1 clock cycle), 7 (9 clock cycles) and 5 (44
clock cycles) are used (see Figure 15). One additional clock cycle is used to read the conversion result stored in the FIFO, for a total of 56 clock cycles per
conversion. The Throughput Rate is f
(MHz)/N, where N is the number of clock cycles/conversion.
CLK
Test Circuits and Waveforms
01171115
01171117
01171116
01171118
FIGURE 1. TRI-STATE Test Circuits and Waveforms
7
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Input and Reference Range
01171105
V
V
= V
− V
IN−
REF
REF+
REF−
= V
− V
IN+
IN
GND ≤ V
GND ≤ V
≤ V +
IN+
IN−
A
≤ V +
A
FIGURE 2. The General Case of Output Digital Code vs. the Operating Input Voltage Range
01171106
V
V
− V
= 2.5V
REF−
REF+
= V
− V
IN−
IN
IN+
GND ≤ V
GND ≤ V
≤ V +
IN+
IN−
A
≤ V +
A
FIGURE 3. Specific Case of Output Digital Code vs. the Operating Input Voltage Range for VREF = 2.5V
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Input and Reference Range (Continued)
01171107
FIGURE 4. The General Case of the VREF Operating Range
01171108
FIGURE 5. The Specific Case of the VREF Operating Range for VA+ = 3.3V
9
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Transfer Characteristic and Static
Errors
01171109
FIGURE 6. Transfer Characteristic
01171110
FIGURE 7. Simplified Error Curve vs. Output Code without Auto-Calibration or Auto-Zero Cycles
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Transfer Characteristic and Static Errors (Continued)
01171111
FIGURE 8. Simplified Error Curve vs. Output Code after Auto-Calibration Cycle
01171112
FIGURE 9. Offset or Zero Error Voltage
11
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Typical Performance Characteristics The following curves apply for 12-bit + sign mode after auto-
calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25˚C, and fCLK = 6 MHz unless otherwise specified.
The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (Note 9)
Linearity Error Change
vs. Clock Frequency
Linearity Error Change
vs. Temperature
01171134
01171136
01171138
01171135
01171137
01171139
Linearity Error Change
vs. Reference Voltage
Linearity Error Change
vs. Supply Voltage
Full-Scale Error Change
vs. Clock Frequency
Full-Scale Error Change
vs. Temperature
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Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25˚C, and fCLK = 6 MHz unless otherwise
specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (Note 9) (Continued)
Full-Scale Error Change
vs. Reference Voltage
Full-Scale Error
vs. Supply Voltage
01171140
01171142
01171144
01171141
01171143
01171145
Zero Error Change
vs. Clock Frequency
Zero Error Change
vs. Temperature
Zero Error Change
vs. Reference Voltage
Zero Error Change
vs. Supply Voltage
13
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Typical Performance Characteristics The following curves apply for 12-bit + sign mode after
auto-calibration with VA+ = VD+ = +3.3V, VREF+ = +2.5V, VREF− = 0V, TA = 25˚C, and fCLK = 6 MHz unless otherwise
specified. The performance for 8-bit + sign and “watchdog” modes is equal to or better than shown. (Note 9) (Continued)
Analog Supply Current
vs. Temperature
Digital Supply Current
vs. Clock Frequency
01171146
01171147
Digital Supply Current
vs. Temperature
01171148
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Timing Diagrams VA+ = VD+ = +3.3V, tR = tF
= 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15
outputs.
01171119
FIGURE 10. Multiplexed Data Bus
1, 3: CS or Address valid to ALE low set-up time.
2, 4: CS or Address valid to ALE low hold time.
5: ALE pulse width
11: WR pulse width
12: WR high to next ALE high
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
6: RD high to next ALE high
7: ALE low to RD low
8: RD pulse width
9: RD high to next RD or WR low
10: ALE low to WR low
18: RD low to data valid (access time)
15
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Timing Diagrams VA+ = VD+ = +3.3V, tR = tF = 3 ns, CL = 100 pF for the INT, DMARQ, D0–D15
outputs. (Continued)
01171120
FIGURE 11. Non-Multiplexed Data Bus (ALE = 1)
8: RD pulse width
16: RD low to data bus out of TRI-STATE
17: RD high to TRI-STATE
9: RD high to next RD or WR low
11: WR pulse width
18: RD low to data valid (access time)
13: WR high to next WR or RD low
14: Data valid to WR high set-up time
15: Data valid to WR high hold time
19: Address invalid from RD or WR high (hold time)
20: CS low or address valid to RD low
21: CS low or address valid to WR low
VA+ = VD+ = +3.3V, tR = tF = 3 ns, CL = 100 pF for the INT,
DMARQ, D0–D15 outputs.
01171121
FIGURE 12. Interrupt and DMARQ
22: INT high from RD low
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23: DMARQ low from RD low
16
SYNC
Synchronization input/output. When used as an
output, it is designed to drive capacitive loads of
100 pF or less. External buffers are necessary for
driving higher load capacitances. SYNC is an
input if the Configuration register’s “I/O Select” bit
is low. A rising edge on this pin causes the inter-
nal S/H to hold the input signal. The next rising
clock edge either starts a conversion or makes a
comparison to a programmable limit depending
on which function is requested by a programming
instruction. This pin will be an output if “I/O Se-
lect” is set high. The SYNC output goes high
when a conversion or a comparison is started and
low when completed. (See Section 2.2). An inter-
nal reset after power is first applied to the
LM12L458 automatically sets this pin as an input.
Pin Descriptions
VA+, VD+ Analog and digital supply voltage pins. The
LM12L458’s supply voltage operating range is
+3.0V to +5.5V. Accuracy is guaranteed only if
VA+ and VD+ are connected to the same power
supply. Each pin should have a parallel combina-
tion of 10 µF (electrolytic or tantalum) and 0.1 µF
(ceramic) bypass capacitors connected between
it and ground.
D0–D15 The internal data input/output TRI-STATE buffers
are connected to these pins. These buffers are
designed to drive capacitive loads of 100 pF or
less. External buffers are necessary for driving
higher load capacitances. These pins allows the
user a means of instruction input and data output.
With a logic high applied to the BW pin, data lines
D8–D15 are placed in a high impedance state
and data lines D0–D7 are used for instruction
input and data output when the LM12L458 is
connected to an 8-bit wide data bus. A logic low
on the BW pin allows the LM12L458 to exchange
information over a 16-bit wide data bus.
BW
INT
Bus Width input pin. This input allows the
LM12L458 to interface directly with either an 8- or
16-bit data bus. A logic high sets the width to 8
bits and places D8–D15 in a high impedance
state. A logic low sets the width to 16 bits.
Active low interrupt output. This output is de-
signed to drive capacitive loads of 100 pF or less.
External buffers are necessary for driving higher
load capacitances. An interrupt signal is gener-
ated any time a non-masked interrupt condition
takes place. There are eight different conditions
that can cause an interrupt. Any interrupt is reset
by reading the Interrupt Status register. (See Sec-
tion 2.3.)
RD
WR
CS
Input for the active low READ bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when RD and CS are both low. This
allows the LM12L458 to transmit information onto
the data bus.
Input for the active low WRITE bus control signal.
The data input/output TRI-STATE buffers, as se-
lected by the logic signal applied to the BW pin,
are enabled when WR and CS are both low. This
allows the LM12L458 to receive information from
the data bus.
DMARQ Active high Direct Memory Access Request out-
put. This output is designed to drive capacitive
loads of 100 pF or less. External buffers are
necessary for driving higher load capacitances. It
goes high whenever the number of conversion
results in the conversion FIFO equals a program-
mable value stored in the Interrupt Enable regis-
ter. It returns to a logic low when the FIFO is
empty.
Input for the active low Chip Select control signal.
A logic low should be applied to this pin only
during
a READ or WRITE access to the
LM12L458. The internal clocking is halted and
conversion stops while Chip Select is low. Con-
version resumes when the Chip Select input sig-
nal returns high.
GND
Ground connection. It should be connected to a
low resistance and inductance analog ground re-
turn that connects directly to the system power
supply ground.
ALE
Address Latch Enable input. It is used in systems
containing a multiplexed data bus. When ALE is
asserted high, the LM12L458 accepts informa-
tion on the data bus as a valid address. A high-
to-low transition will latch the address data on
A0–A4 and the logic state on the CS input. Any
changes on A0–A4 and CS while ALE is low will
not affect the LM12L458. See Figure 10. When a
non-multiplexed bus is used, ALE is continuously
asserted high. See Figure 11.
IN0–IN7 These are the eight analog inputs. A given chan-
nel is selected through the instruction RAM. Any
of the channels can be configured as an indepen-
dent single-ended input. Any pair of channels,
whether adjacent or non-adjacent, can operate as
a fully differential pair.
VREF−
This is the negative reference input. The
LM12L458 operates with 0V ≤ VREF− ≤ VREF+
.
This pin should be bypassed to ground with a
parallel combination of 10 µF and 0.1 µF (ce-
ramic) capacitors.
CLK
External clock input pin. The LM12L458 operates
with an input clock frequency in the range of
0.05 MHz to 8 MHz.
VREF+
Positive reference input. The LM12L458 operate
with 0V ≤ VREF+ ≤ VA+. This pin should be by-
passed to ground with a parallel combination of
10 µF and 0.1 µF (ceramic) capacitors.
A0–A4
The LM12L458’s address lines. They are used to
access all internal registers, Conversion FIFO,
and Instruction RAM.
N.C.
This is a no connect pin.
17
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operates in the single-ended mode. Fully differential analog
input channels are formed by pairing any two channels
together.
1.0 Functional Description
The LM12L458 is a multi-functional Data Acquisition System
that includes
a fully differential 12-bit-plus-sign self-
The LM12L458’s internal S/H is designed to operate at its
minimum acquisition time (1.5 µs, 12 bits) when the source
calibrating analog-to-digital converter (ADC) with a two’s-
complement output format, an 8-channel analog multiplexer,
a first-in-first-out (FIFO) register that can store 32 conversion
results, and an Instruction RAM that can store as many as
eight instructions to be sequentially executed. All of this
circuitry operates on only a single +3.3V power supply.
<
impedance, RS, is ≤ 80Ω (fCLK ≤ 6 MHz). When 80Ω RS
≤
5.56 kΩ, the internal S/H’s acquisition time can be increased
to a maximum of 6.5 µs (12 bits, fCLK = 6 MHz). See Section
2.1 (Instruction RAM “00”) Bits 12–15 for more information.
Microprocessor overhead is reduced through the use of the
internal conversion FIFO. Thirty-two consecutive conver-
sions can be completed and stored in the FIFO without any
microprocessor intervention. The microprocessor can, at any
time, interrogate the FIFO and retrieve its contents. It can
also wait for the LM12L458 to issue an interrupt when the
FIFO is full or after any number (≤32) of conversions have
been stored.
The LM12L458 has three modes of operation:
12-bit + sign with correction
8-bit + sign without correction
8-bit + sign comparison mode (“watchdog” mode)
The fully differential 12-bit-plus-sign ADC uses a charge
redistribution topology that includes calibration capabilities.
Charge re-distribution ADCs use a capacitor ladder in place
of a resistor ladder to form an internal DAC. The DAC is used
by a successive approximation register to generate interme-
diate voltages between the voltages applied to VREF− and
VREF+. These intermediate voltages are compared against
the sampled analog input voltage as each bit is generated.
The number of intermediate voltages and comparisons
equals the ADC’s resolution. The correction of each bit’s
accuracy is accomplished by calibrating the capacitor ladder
used in the ADC.
Conversion sequencing, internal timer interval, multiplexer
configuration, and many other operations are programmed
and set in the Instruction RAM.
A diagnostic mode is available that allows verification of the
LM12L458’s operation. This mode internally connects the
voltages present at the VREF+, VREF−, and GND pins to the
internal VIN+ and VIN− S/H inputs. This mode is activated by
setting the Diagnostic bit (Bit 11) in the Configuration register
to a “1”. More information concerning this mode of operation
can be found in Section 2.2.
Two different calibration modes are available; one compen-
sates for offset voltage, or zero error, while the other corrects
both offset error and the ADC’s linearity error.
2.0 Internal User-Programmable
Registers
When correcting offset only, the offset error is measured
once and a correction coefficient is created. During the full
calibration, the offset error is measured eight times, aver-
aged, and a correction coefficient is created. After comple-
tion of either calibration mode, the offset correction coeffi-
cient is stored in an internal offset correction register.
2.1 INSTRUCTION RAM
The instruction RAM holds up to eight sequentially execut-
able instructions. Each 48-bit long instruction is divided into
three 16-bit sections. READ and WRITE operations can be
issued to each 16-bit section using the instruction’s address
and the 2-bit “RAM pointer” in the Configuration register. The
eight instructions are located at addresses 0000 through
0111 (A4–A1, BW = 0) when using a 16-bit wide data bus or
at addresses 00000 through 01111 (A4–A0, BW = 1) when
using an 8-bit wide data bus. They can be accessed and
programmed in random order.
The LM12L458’s overall linearity correction is achieved by
correcting the internal DAC’s capacitor mismatch. Each ca-
pacitor is compared eight times against all remaining smaller
value capacitors and any errors are averaged. A correction
coefficient is then created and stored in one of the thirteen
internal linearity correction registers. An internal state ma-
chine, using patterns stored in an internal 16 x 8-bit ROM,
executes each calibration algorithm.
Any Instruction RAM READ or WRITE can affect the se-
quencer’s operation:
Once calibrated, an internal arithmetic logic unit (ALU) uses
the offset correction coefficient and the 13 linearity correction
coefficients to reduce the conversion’s offset error and lin-
earity error, in the background, during the 12-bit + sign
conversion. The 8-bit + sign conversion and comparison
modes use only the offset coefficient. The 8-bit + sign mode
performs a conversion in less than half the time used by the
12-bit + sign conversion mode.
The Sequencer should be stopped by setting the RESET bit
to a “1” or by resetting the START bit in the Configuration
Register and waiting for the current instruction to finish ex-
ecution before any Instruction RAM READ or WRITE is
initiated. Bit 0 of the Configuration Register indicates the
Sequencer Status. See paragraph 2.2 for information on the
Configuration Register.
The LM12L458’s “watchdog” mode is used to monitor a
single-ended or differential signal’s amplitude. Each
sampled signal has two limits. An interrupt can be generated
if the input signal is above or below either of the two limits.
This allows interrupts to be generated when analog voltage
inputs are “inside the window” or, alternatively, “outside the
window”. After a “watchdog” mode interrupt, the processor
can then request a conversion on the input signal and read
the signal’s magnitude.
A soft RESET should be issued by writing a “1” to the
Configuration Register’s RESET bit after any READ or
WRITE to the Instruction RAM.
The three sections in the Instruction RAM are selected by
the Configuration Register’s 2-bit “RAM Pointer”, bits D8 and
D9. The first 16-bit Instruction RAM section is selected with
the RAM Pointer equal to “00”. This section provides multi-
plexer channel selection, as well as resolution, acquisition
time, etc. The second 16-bit section holds “watchdog” limit
#1, its sign, and an indicator that shows that an interrupt can
be generated if the input signal is greater or less than the
programmed limit. The third 16-bit section holds “watchdog”
The analog input multiplexer can be configured for any com-
bination of single-ended or fully differential operation. Each
input is referenced to ground when a multiplexer channel
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18
in the inverting mode. A code of “000” selects ground as the
inverting input for single ended operation.
2.0 Internal User-Programmable
Registers (Continued)
limit #2, its sign, and an indicator that shows that an interrupt
can be generated if the input signal is greater or less than the
programmed limit.
Bit 8 is the SYNC bit. Setting Bit 8 to “1” causes the Se-
quencer to suspend operation at the end of the internal S/H’s
acquisition cycle and to wait until a rising edge appears at
the SYNC pin. When a rising edge appears, the S/H ac-
quires the input signal magnitude and the ADC performs a
conversion on the clock’s next rising edge. When the SYNC
pin is used as an input, the Configuration register’s “I/O
Select” bit (Bit 7) must be set to a “0”. With SYNC configured
as an input, it is possible to synchronize the start of a
conversion to an external event. This is useful in applications
such as digital signal processing (DSP) where the exact
timing of conversions is important.
Instruction RAM “00”
Bit 0 is the LOOP bit. It indicates the last instruction to be
executed in any instruction sequence when it is set to a “1”.
The next instruction to be executed will be instruction 0.
Bit 1 is the PAUSE bit. This controls the Sequencer’s opera-
tion. When the PAUSE bit is set (“1”), the Sequencer will stop
after reading the current instruction, but before executing it
and the start bit, in the Configuration register, is automati-
cally reset to a “0”. Setting the PAUSE also causes an
interrupt to be issued. The Sequencer is restarted by placing
a “1” in the Configuration register’s Bit 0 (Start bit).
When the LM12L458 is used in the “watchdog” mode with
external synchronization, two rising edges on the SYNC
input are required to initiate two comparisons. The first rising
edge initiates the comparison of the selected analog input
signal with Limit #1 (found in Instruction RAM “01”) and the
second rising edge initiates the comparison of the same
analog input signal with Limit #2 (found in Instruction RAM
“10”).
After the Instruction RAM has been programmed and the
RESET bit is set to “1”, the Sequencer retrieves Instruction
000, decodes it, and waits for a “1” to be placed in the
Configuration’s START bit. The START bit value of “0” “over-
rides” the action of Instruction 000’s PAUSE bit when the
Sequencer is started. Once started, the Sequencer executes
Instruction 000 and retrieves, decodes, and executes each
of the remaining instructions. No PAUSE Interrupt (INT 5) is
generated the first time the Sequencer executes Instruction
000 having a PAUSE bit set to “1”. When the Sequencer
encounters a LOOP bit or completes all eight instructions,
Instruction 000 is retrieved and decoded. A set PAUSE bit in
Instruction 000 now halts the Sequencer before the instruc-
tion is executed.
Bit 9 is the TIMER bit. When Bit 9 is set to “1”, the Se-
quencer will halt until the internal 16-bit Timer counts down
to zero. During this time interval, no “watchdog” comparisons
or analog-to-digital conversions will be performed.
Bit 10 selects the ADC conversion resolution. Setting Bit 10
to “1” selects 8-bit + sign and when reset to “0” selects 12-bit
+ sign.
Bit 11 is the “watchdog” comparison mode enable bit. When
operating in the “watchdog” comparison mode, the selected
analog input signal is compared with the programmable
values stored in Limit #1 and Limit #2 (see Instruction RAM
“01” and Instruction RAM “10”). Setting Bit 11 to “1” causes
two comparisons of the selected analog input signal with the
two stored limits. When Bit 11 is reset to “0”, an 8-bit + sign
or 12-bit + sign (depending on the state of Bit 10 of Instruc-
tion RAM “00”) conversion of the input signal can take place.
Bits 2–4 select which of the eight input channels (“000” to
“111” for IN0–IN7) will be configured as non-inverting inputs
to the LM12L458’s ADC. (See Table 1.)
Bits 5–7 select which of the seven input channels (“001” to
“111” for IN1 to IN7) will be configured as inverting inputs to
the LM12L458’s ADC. (See Table 1.) Fully differential opera-
tion is created by selecting two multiplexer channels, one
operating in the non-inverting mode and the other operating
19
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20
A4 A3 A2 A1 A0
Purpose
Type
D7
D6
D5
D4
D3
D2
D1
D0
0
0
to
1
0
0
0
0
0
0
0
0
1
0
1
0
1
R/W
VIN−
VIN+
Pause Loop
1
0
1
0
Instruction RAM
(RAM Pointer = 00)
0
Watch-
dog
to
1
R/W
R/W
R/W
R/W
R/W
Acquisition Time
8/12
Timer
Sync
Sign
1
0
1
0
0
to
1
Comparison Limit #1
1
0
1
0
Instruction RAM
(RAM Pointer = 01)
0
> <
/
to
1
Don’t Care
1
0
1
0
0
to
1
Comparison Limit #2
1
0
1
0
Instruction RAM
(RAM Pointer = 10)
0
> <
to
1
Don’t Care
/
Sign
Start
1
0
1
0
Auto
Chan
Mask
Stand-
by
Auto-
Zero
Test
= 0
1
1
1
0
0
0
0
1
0
R/W I/O Sel
R/W
Full Cal
DIAG
INT3
Reset
Zeroec
Configuration
Register
0
0
0
1
Don’t Care
RAM Pointer
INT1 INT0
Don’t
Care
R/W
INT7
INT5
INT4
INT2
Interrupt Enable
Register
Number of Conversions in Conversion FIFO to
Generate INT2
Sequencer Address to
Generate INT1
1
1
0
0
0
1
1
0
1
0
R/W
R
INST7
“0”
INST5
INST4
INST3
INST2 INST1 INST0
Address of Sequencer
Instruction being
Interrupt Status
Register
Actual Number of Conversions Results in
Conversion FIFO
1
0
1
0
1
R
Executed
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
Timer
R/W
R/W
R
Timer Preset: Low Byte
Timer Preset: High Byte
Conversion Data: LSBs
Register
Conversion
FIFO
R
Address or Sign
Sign
Conversion Data: MSBs
R
Limit #1 Status
Limit #2 Status
Limit Status
Register
R
FIGURE 14. LM12L458 Memory Map for 8-Bit Wide Data Bus (BW = “1” and Test Bit = “0”)
Bits 12–15 are used to store the user-programmable acqui-
sition time. The Sequencer keeps the internal S/H in the
acquisition mode for a fixed number of clock cycles (nine
clock cycles, for 12-bit + sign conversions and two clock
cycles for 8-bit + sign conversions or “watchdog” compari-
sons) plus a variable number of clock cycles equal to twice
the value stored in Bits 12–15. Thus, the S/H’s acquisition
time is (9 + 2D) clock cycles for 12-bit + sign conversions
and (2 + 2D) clock cycles for 8-bit + sign conversions or
“watchdog” comparisons, where D is the value stored in Bits
12–15. The minimum acquisition time compensates for the
typical internal multiplexer series resistance of 2 kΩ, and any
additional delay created by Bits 12–15 compensates for
source resistances greater than 80Ω. (For this acquisition
time discussion, numbers in ( ) are shown for the LM12L458
operating at 6 MHz.) The necessary acquisition time is de-
termined by the source impedance at the multiplexer input. If
<
the source resistance (RS) 80Ω and the clock frequency is
6 MHz, the value stored in bits 12–15 (D) can be 0000. If RS
>
80Ω, the following equations determine the value that
should be stored in bits 12–15.
D = 0.45 x RS x fCLK
for 12-bits + sign
D = 0.36 x RS x fCLK
for 8-bits + sign and “watchdog”
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A reset signal is internally generated when power is first
applied to the part. No operation should be started until the
RESET bit is “0”.
2.0 Internal User-Programmable
Registers (Continued)
Writing a “1” to Bit 2 initiates an auto-zero offset voltage
calibration. Unlike the eight-sample auto-zero calibration
performed during the full calibration procedure, Bit 2 initiates
a “short” auto-zero by sampling the offset once and creating
RS is in kΩ and fCLK is in MHz. Round the result to the next
higher integer value. If D is greater than 15, it is advisable to
lower the source impedance by using an analog buffer be-
tween the signal source and the LM12L458’s multiplexer
inputs.
a
correction coefficient (full calibration averages eight
samples of the converter offset voltage when creating a
correction coefficient). If the Sequencer is running when Bit 2
is set to “1”, an auto-zero starts immediately after the con-
clusion of the currently running instruction. Bit 2 is reset
automatically to a “0” and an interrupt flag (Bit 3, in the
Interrupt Status register) is set at the end of the auto-zero
(76 clock cycles). After completion of an auto-zero calibra-
tion, the Sequencer fetches the next instruction as pointed to
by the Instruction RAM’s pointer and resumes execution. If
the Sequencer is stopped, an auto-zero is performed imme-
diately at the time requested.
Instruction RAM “01”
The second Instruction RAM section is selected by placing a
“01” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #1. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12L458 performs a “watch-
dog” comparison of the sampled analog input signal with the
limit #1 value first, followed by a comparison of the same
sampled analog input signal with the value found in limit #2
(Instruction RAM “10”).
Bit 8 holds limit #1’s sign.
Writing a “1” to Bit 3 initiates a complete calibration process
that includes a “long” auto-zero offset voltage correction (this
calibration averages eight samples of the comparator offset
voltage when creating a correction coefficient) followed by
an ADC linearity calibration. This complete calibration is
started after the currently running instruction is completed if
the Sequencer is running when Bit 3 is set to “1”. Bit 3 is
reset automatically to a “0” and an interrupt flag (Bit 4, in the
Interrupt Status register) will be generated at the end of the
calibration procedure (4944 clock cycles). After completion
of a full auto-zero and linearity calibration, the Sequencer
fetches the next instruction as pointed to by the Instruction
RAM’s pointer and resumes execution. If the Sequencer is
stopped, a full calibration is performed immediately at the
time requested.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #1 to generate an interrupt, while a “0” causes a voltage
less than limit #1 to generate an interrupt.
Bits 10–15 are not used.
Instruction RAM “10”
The third Instruction RAM section is selected by placing a
“10” in Bits 8 and 9 of the Configuration register.
Bits 0–7 hold “watchdog” limit #2. When Bit 11 of Instruction
RAM “00” is set to a “1”, the LM12L458 performs a “watch-
dog” comparison of the sampled analog input signal with the
limit #1 value first (Instruction RAM “01”), followed by a
comparison of the same sampled analog input signal with
the value found in limit #2.
Bit 4 is the Standby bit. Writing a “1” to Bit 4 immediately
places the LM12L458 in Standby mode. Normal operation
returns when Bit 4 is reset to a “0”. The Standby command
(“1”) disconnects the external clock from the internal circuitry,
decreases the LM12L458’s internal analog circuitry power
supply current, and preserves all internal RAM contents.
After writing a “0” to the Standby bit, the LM12L458 returns
to an operating state identical to that caused by exercising
the RESET bit. A Standby completion interrupt is issued after
a power-up completion delay that allows the analog circuitry
to settle. The Sequencer should be restarted only after the
Standby completion is issued. The Instruction RAM can still
be accessed through read and write operations while the
LM12L458 are in Standby Mode.
Bit 8 holds limit #2’s sign.
Bit 9’s state determines the limit condition that generates a
“watchdog” interrupt. A “1” causes a voltage greater than
limit #2 to generate an interrupt, while a “0” causes a voltage
less than limit #2 to generate an interrupt.
Bits 10–15 are not used.
2.2 CONFIGURATION REGISTER
The Configuration register, 1000 (A4–A1, BW = 0) or 1000x
(A4–A0, BW = 1) is a 16-bit control register with read/write
capability. It acts as the LM12L458’s “control panel” holding
global information as well as start/stop, reset, self-
calibration, and stand-by commands.
Bit 5 is the Channel Address Mask. If Bit 5 is set to a “1”, Bits
13–15 in the conversion FIFO will be equal to the sign bit (Bit
12) of the conversion data. Resetting Bit 5 to a “0” causes
conversion data Bits 13 through 15 to hold the instruction
pointer value of the instruction to which the conversion data
belongs.
Bit 0 is the START/STOP bit. Reading Bit 0 returns an
indication of the Sequencer’s status. A “0” indicates that the
Sequencer is stopped and waiting to execute the next in-
struction. A “1” shows that the Sequencer is running. Writing
a “0” halts the Sequencer when the current instruction has
finished execution. The next instruction to be executed is
pointed to by the instruction pointer found in the status
register. A “1” restarts the Sequencer with the instruction
currently pointed to by the instruction pointer. (See Bits 8–10
in the Interrupt Status register.)
Bit 6 is used to select a “short” auto-zero correction for every
conversion. The Sequencer automatically inserts an auto-
zero before every conversion or “watchdog” comparison if
Bit 6 is set to “1”. No automatic correction will be performed
if Bit 6 is reset to “0”.
The LM12L458’s offset voltage, after calibration, has a typi-
cal drift of 0.1 LSB over a temperature range of −40˚C to
+85˚C. This small drift is less than the variability of the
change in offset that can occur when using the auto-zero
correction with each conversion. This variability is the result
of using only one sample of the offset voltage to create a
correction value. This variability decreases when using the
Bit 1 is the LM12L458’s system RESET bit. Writing a “1” to
Bit 1 stops the Sequencer (resetting the Configuration reg-
ister’s START/STOP bit), resets the Instruction pointer to
“000” (found in the Interrupt Status register), clears the Con-
version FIFO, and resets all interrupt flags. The RESET bit
will return to “0” after two clock cycles unless it is forced high
by writing a “1” into the Configuration register’s Standby bit.
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22
mode. Two sequential comparisons are made when the
LM12L458 are executing a “watchdog” instruction. Depend-
ing on the logic state of Bit 9 in the Instruction RAM’s second
and third sections, an interrupt will be generated either when
the input signal’s magnitude is greater than or less than the
programmable limits. (See the Instruction RAM, Bit 9 de-
scription.) The Limit Status register will indicate which pro-
grammed limit, #1 or #2 and which instruction was executing
when the limit was crossed.
2.0 Internal User-Programmable
Registers (Continued)
full calibration mode because eight samples of the offset
voltage are taken, averaged, and used to create a correction
value.
Bit 7 is used to program the SYNC pin (29) to operate as
either an input or an output. The SYNC pin becomes an
output when Bit 7 is a “1” and an input when Bit 7 is a “0”.
With SYNC programmed as an input, the rising edge of any
logic signal applied to pin 29 will start a conversion or
“watchdog” comparison. Programmed as an output, the logic
level at pin 29 will go high at the start of a conversion or
“watchdog” comparison and remain high until either have
finished. See Instruction RAM “00”, Bit 8.
Interrupt 1 is generated when the Sequencer reaches the
instruction counter value specified in the Interrupt Enable
register’s bits 8–10. This flag appears before the instruc-
tion’s execution.
Interrupt 2 is activated when the Conversion FIFO holds a
number of conversions equal to the programmable value
stored in the Interrupt Enable register’s Bits 11–15. This
value ranges from 0001 to 1111, representing 1 to 31 con-
versions stored in the FIFO. A user-programmed value of
0000 has no meaning. See Section 3.0 for more FIFO infor-
mation.
Bits 8 and 9 form the RAM Pointer that is used to select
each of a 48-bit instruction’s three 16-bit sections during
read or write actions. A “00” selects Instruction RAM section
one, “01” selects section two, and “10” selects section three.
Bit 10 activates the Test mode that is used only during
production testing. Leave this bit reset to “0”.
The completion of the short, single-sampled auto-zero cali-
bration generates Interrupt 3.
Bit 11 is the Diagnostic bit and is available only in the
LM12L458. It can be activated by setting it to a “1” (the Test
bit must be reset to a “0”). The Diagnostic mode, along with
a correctly chosen instruction, allows verification that the
LM12L458’s ADC is performing correctly. When activated,
the inverting and non-inverting inputs are connected as
shown in Table 1. As an example, an instruction with “001”
for both VIN+ and VIN− while using the Diagnostic mode
typically results in a full-scale output.
The completion of
calibration generates Interrupt 4.
a full auto-zero and linearity self-
Interrupt 5 is generated when the Sequencer encounters an
instruction that has its Pause bit (Bit 1 in Instruction RAM
“00”) set to “1”.
Interrupt 7 is issued after a short delay (10 ms typ) while the
LM12L458 returns from Standby mode to active operation
using the Configuration register’s Bit 4. This short delay
allows the internal analog circuitry to settle sufficiently, en-
suring accurate conversion results.
2.3 INTERRUPTS
The LM12L458 has eight possible interrupts, all with the
same priority. Any of these interrupts will cause a hardware
interrupt to appear on the INT pin (31) if they are not masked
(by the Interrupt Enable register). The Interrupt Status reg-
ister is then read to determine which of the eight interrupts
has been issued.
2.4 INTERRUPT ENABLE REGISTER
The Interrupt Enable register at address location 1001
(A4–A1, BW = 0) or 1001x (A4–A0, BW = 1) has READ/
WRITE capability. An individual interrupt’s ability to produce
an external interrupt at pin 31 (INT) is accomplished by
placing a “1” in the appropriate bit location. Any of the
internal interrupt-producing operations will set their corre-
sponding bits to “1” in the Interrupt Status register regardless
of the state of the associated bit in the Interrupt Enable
register. See Section 2.3 for more information about each of
the eight internal interrupts.
TABLE 1. LM12L458 Input Multiplexer
Channel Configuration Showing Normal
Mode and Diagnostic Mode
Channel
Normal Mode
Diagnostic Mode
Selection
Data
000
Bit 0 enables an external interrupt when an internal “watch-
dog” comparison limit interrupt has taken place.
VIN+
VIN−
VIN+
VIN−
Bit 1 enables an external interrupt when the Sequencer has
reached the address stored in Bits 8–10 of the Interrupt
Enable register.
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
GND
IN1
IN2
IN3
IN4
IN5
IN6
IN7
001
VREF+
IN2
VREF−
IN2
010
Bit 2 enables an external interrupt when the Conversion
FIFO’s limit, stored in Bits 11–15 of the Interrupt Enable
register, has been reached.
011
IN3
IN3
100
IN4
IN4
Bit 3 enables an external interrupt when the single-sampled
auto-zero calibration has been completed.
101
IN5
IN5
110
IN6
IN6
Bit 4 enables an external interrupt when a full auto-zero and
linearity self-calibration has been completed.
111
IN7
IN7
Bit 5 enables an external interrupt when an internal Pause
interrupt has been generated.
The Interrupt Status register, 1010 (A4–A1, BW = 0) or
1010x (A4–A0, BW = 1) must be cleared by reading it after
writing to the Interrupt Enable register. This removes any
spurious interrupts on the INT pin generated during an Inter-
rupt Enable register access.
Bit 6 is a “Don’t Care”.
Bit 7 enables an external interrupt when the LM12L458
return from power-down to active mode.
Interrupt 0 is generated whenever the analog input voltage
on a selected multiplexer channel crosses a limit while the
LM12L458 are operating in the “watchdog” comparison
Bits 8–10 form the storage location of the user-
programmable value against which the Sequencer’s address
is compared. When the Sequencer reaches an address that
23
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3.2 LIMIT STATUS REGISTER
2.0 Internal User-Programmable
Registers (Continued)
is equal to the value stored in Bits 8–10, an internal interrupt
is generated and appears in Bit 1 of the Interrupt Status
register. If Bit 1 of the Interrupt Enable register is set to “1”,
an external interrupt will appear at pin 31 (INT).
The read-only register is located at address 1101 (A4–A1,
BW = 0) or 1101x (A4–A0, BW = 1). This register is used in
tandem with the Limit #1 and Limit #2 registers in the Instruc-
tion RAM. Whenever a given instruction’s input voltage ex-
ceeds the limit set in its corresponding Limit register (#1 or
#2), a bit, corresponding to the instruction number, is set in
the Limit Status register. Any of the active (“1”) Limit Status
flags are reset to “0” whenever this register is read or a
device reset is issued (see Bit 1 in the Configuration regis-
ter). This register holds the status of limits #1 and #2 for each
of the eight instructions.
The value stored in bits 8–10 ranges from 000 to 111,
representing 0 to 7 instructions stored in the Instruction
RAM. After the Instruction RAM has been programmed and
the RESET bit is set to “1”, the Sequencer is started by
placing a “1” in the Configuration register’s START bit. Set-
ting the INT 1 trigger value to 000 does not generate an
INT 1 the first time the Sequencer retrieves and decodes
Instruction 000. The Sequencer generates INT 1 (by placing
a “1” in the Interrupt Status register’s Bit 1) the second time
and after the Sequencer encounters Instruction 000. It is
important to remember that the Sequencer continues to
operate even if an Instruction interrupt (INT 1) is internally or
externally generated. The only mechanisms that stop the
Sequencer are an instruction with the PAUSE bit set to “1”
(halts before instruction execution), placing a “0” in the Con-
figuration register’s START bit, or placing a “1” in the Con-
figuration register’s RESET bit.
Bits 0–7 show the Limit #1 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #1 reg-
ister. When, for example, instruction 3 is a “watchdog” op-
eration (Bit 11 is set high) and the input for instruction 3
meets the magnitude and/or polarity data stored in instruc-
tion 3’s Limit #1 register, Bit 3 in the Limit Status register will
be set to a “1”.
Bits 8–15 show the Limit #2 status. Each bit will be set high
(“1”) when the corresponding instruction’s input voltage ex-
ceeds the threshold stored in the instruction’s Limit #2 reg-
ister. When, for example, the input to instruction 6 meets the
value stored in instruction 6’s Limit #2 register, Bit 14 in the
Limit Status register will be set to a “1”.
Bits 11–15 hold the number of conversions that must be
stored in the Conversion FIFO in order to generate an inter-
nal interrupt. This internal interrupt appears in Bit 2 of the
Interrupt Status register. If Bit 2 of the Interrupt Enable
register is set to “1”, an external interrupt will appear at pin
31 (INT).
3.3 TIMER
The LM12L458 have an on-board 16-bit timer that includes a
5-bit pre-scaler. It uses the clock signal applied to pin 23 as
its input. It can generate time intervals of 0 through 221 clock
cycles in steps of 25. This time interval can be used to delay
the execution of instructions. It can also be used to slow the
conversion rate when converting slowly changing signals.
This can reduce the amount of redundant data stored in the
FIFO and retrieved by the controller.
3.0 Other Registers and Functions
3.1 INTERRUPT STATUS REGISTER
This read-only register is located at address 1010 (A4–A1,
BW = 0) or 1010x (A4–A0, BW = 1). The corresponding flag
in the Interrupt Status register goes high (“1”) any time that
an interrupt condition takes place, whether an interrupt is
enabled or disabled in the Interrupt Enable register. Any of
the active (“1”) Interrupt Status register flags are reset to “0”
whenever this register is read or a device reset is issued
(see Bit 1 in the Configuration Register).
The user-defined timing value used by the Timer is stored in
the 16-bit READ/WRITE Timer register at location 1011
(A4–A1, BW = 0) or 1011x (A4–A0, BW = 1) and is pre-
loaded automatically. Bits 0–7 hold the preset value’s low
byte and Bits 8–15 hold the high byte. The Timer is activated
by the Sequencer only if the current instruction’s Bit 9 is set
(“1”). If the equivalent decimal value “N” (0 ≤ N ≤ 216 − 1) is
written inside the 16-bit Timer register and the Timer is
enabled by setting an instruction’s bit 9 to a “1”, the Se-
quencer will delay the same instruction’s execution by halt-
ing at state 3 (S3), as shown in Figure 15, for 32 x N + 2
clock cycles.
Bit 0 is set to “1” when a “watchdog” comparison limit
interrupt has taken place.
Bit 1 is set to “1” when the Sequencer has reached the
address stored in Bits 8–10 of the Interrupt Enable register.
Bit 2 is set to “1” when the Conversion FIFO’s limit, stored in
Bits 11–15 of the Interrupt Enable register, has been
reached.
3.4 DMA
The DMA works in tandem with Interrupt 2. An active DMA
Request on pin 32 (DMARQ) requires that the FIFO interrupt
be enabled. The voltage on the DMARQ pin goes high when
the number of conversions in the FIFO equals the 5-bit value
stored in the Interrupt Enable register (bits 11–15). The
voltage on the INT pin goes low at the same time as the
voltage on the DMARQ pin goes high. The voltage on the
DMARQ pin goes low when the FIFO is emptied. The Inter-
rupt Status register must be read to clear the FIFO interrupt
flag in order to enable the next DMA request.
Bit 3 is set to “1” when the single-sampled auto-zero has
been completed.
Bit 4 is set to “1” when an auto-zero and full linearity self-
calibration has been completed.
Bit 5 is set to “1” when a Pause interrupt has been gener-
ated.
Bit 6 is a “Don’t Care”.
Bit 7 is set to “1” when the LM12L458 return from power-
down to active mode.
DMA operation is optimized through the use of the 16-bit
data bus connection (a logic “0” applied to the BW pin).
Using this bus width allows DMA controllers that have single
address Read/Write capability to easily unload the FIFO.
Using DMA on an 8-bit data bus is more difficult. Two read
operations (low byte, high byte) are needed to retrieve each
Bits 8–10 hold the Sequencer’s actual instruction address
while it is running.
Bits 11–15 hold the actual number of conversions stored in
the Conversion FIFO while the Sequencer is running.
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24
3.0 Other Registers and Functions
5.0 Sequencer
(Continued)
The Sequencer uses a 3-bit counter (Instruction Pointer, or
IP, in Figure 1) to retrieve the programmable conversion
instructions stored in the Instruction RAM. The 3-bit counter
is reset to 000 during chip reset or if the current executed
instruction has its Loop bit (Bit 1 in any Instruction RAM “00”)
set high (“1”). It increments at the end of the currently
executed instruction and points to the next instruction. It will
continue to increment up to 111 unless an instruction’s Loop
bit is set. If this bit is set, the counter resets to “000” and
execution begins again with the first instruction. If all instruc-
tions have their Loop bit reset to “0”, the Sequencer will
execute all eight instructions continuously. Therefore, it is
important to realize that if less than eight instructions are
programmed, the Loop bit on the last instruction must be set.
Leaving this bit reset to “0” allows the Sequencer to execute
“unprogrammed” instructions, the results of which may be
unpredictable.
conversion result from the FIFO. Therefore, the DMA con-
troller must be able to repeatedly access two constant ad-
dresses when transferring data from the LM12L458 to the
host system.
4.0 FIFO
The result of each conversion stored in an internal read-only
FIFO (First-In, First-Out) register. It is located at 1100
(A4–A1, BW = 0) or 1100x (A4–A0, BW = 1). This register
has 32 16-bit wide locations. Each location holds 13-bit data.
Bits 0–3 hold the four LSB’s in the 12 bits + sign mode or
“1110” in the 8 bits + sign mode. Bits 4–11 hold the eight
MSB’s and Bit 12 holds the sign bit. Bits 13–15 can hold
either the sign bit, extending the register’s two’s complement
data format to a full sixteen bits or the instruction address
that generated the conversion and the resulting data. These
modes are selected according to the logic state of the Con-
figuration register’s Bit 5.
The Sequencer’s Instruction Pointer value is readable at any
time and is found in the Status register at Bits 8–10. The
Sequencer can go through eight states during instruction
execution:
The FIFO status should be read in the Interrupt Status
register (Bits 11–15) to determine the number of conversion
results that are held in the FIFO before retrieving them. This
will help prevent conversion data corruption that may take
place if the number of reads are greater than the number of
conversion results contained in the FIFO. Trying to read the
FIFO when it is empty may corrupt new data being written
into the FIFO. Writing more than 32 conversion data into the
FIFO by the ADC results in loss of the first conversion data.
Therefore, to prevent data loss, it is recommended that the
LM12L458’s interrupt capability be used to inform the system
controller that the FIFO is full.
State 0: The current instruction’s first 16 bits are read from
the Instruction RAM “00”. This state is one clock cycle long.
State 1: Checks the state of the Calibration and Start bits.
This is the “rest” state whenever the Sequencer is stopped
using the reset, a Pause command, or the Start bit is reset
low (“0”). When the Start bit is set to a “1”, this state is one
clock cycle long.
State 2: Perform calibration. If bit 2 or bit 6 of the Con-
figuration register is set to a “1”, state 2 is 76 clock cycles
long. If the Configuration register’s bit 3 is set to a “1”, state
2 is 4944 clock cycles long.
The lower portion (A0 = 0) of the data word (Bits 0–7) should
be read first followed by a read of the upper portion (A0 = 1)
when using the 8-bit bus width (BW = 1). Reading the upper
portion first causes the data to shift down, which results in
loss of the lower byte.
State 3: Run the internal 16-bit Timer. The number of
clock cycles for this state varies according to the value
stored in the Timer register. The number of clock cycles is
found by using the expression below
32T + 2
Bits 0–12 hold 12-bit + sign conversion data. Bits 0–3 will
be 1110 (LSB) when using 8-bit plus sign resolution.
where 0 ≤ T ≤ 216 −1.
State 7: Run the acquisition delay and read Limit #1’s
value if needed. The number of clock cycles for 12-bit + sign
mode varies according to
Bits 13–15 hold either the instruction responsible for the
associated conversion data or the sign bit. Either mode is
selected with Bit 5 in the Configuration register.
9 + 2D
Using the FIFO’s full depth is achieved as follows. Set the
value of the Interrupt Enable registers’s Bits 11–15 to 1111
and the Interrupt Enable register’s Bit 2 to a “1”. This gener-
ates an external interrupt when the 31st conversion is stored
in the FIFO. This gives the host processor a chance to send
a “0” to the LM12L458’s Start bit (Configuration register) and
halt the ADC before it completes the 32nd conversion. The
Sequencer halts after the current (32) conversion is com-
pleted. The conversion data is then transferred to the FIFO
and occupies the 32nd location. FIFO overflow is avoided if
the Sequencer is halted before the start of the 32nd conver-
sion by placing a “0” in the Start bit (Configuration register).
It is important to remember that the Sequencer continues to
operate even if a FIFO interrupt (INT 2) is internally or
externally generated. The only mechanisms that stop the
Sequencer are an instruction with the PAUSE bit set to “1”
(halts before instruction execution), placing a “0” in the Con-
figuration register’s START bit, or placing a “1” in the Con-
figuration register’s RESET bit.
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
The number of clock cycles for 8-bit + sign or “watchdog”
mode varies according to
2 + 2D
where D is the user-programmable 4-bit value stored in bits
12–15 of Instruction RAM “00” and is limited to 0 ≤ D ≤ 15.
State 6: Perform first comparison. This state is 5 clock
cycles long.
State 4: Read Limit #2. This state is 1 clock cycle long.
State 5: Perform a conversion or second comparison. This
state takes 44 clock cycles when using the 12-bit + sign
mode or 21 clock cycles when using the 8-bit + sign mode.
The “watchdog” mode takes 5 clock cycles.
25
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5.0 Sequencer (Continued)
01171122
FIGURE 15. Sequencer Logic Flow Chart (IP = Instruction Pointer)
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26
quisition time, the LM12L458’s analog inputs can handle
source impedance as high as 5.56 kΩ. Refer to Section 2.1,
Instruction RAM “00”, Bits 12–15 for further information.
6.0 Analog Considerations
6.1 REFERENCE VOLTAGE
The difference in the voltages applied to the VREF+ and
VREF− defines the analog input voltage span (the difference
between the voltages applied between two multiplexer inputs
or the voltage applied to one of the multiplexer inputs and
analog ground), over which 4095 positive and 4096 negative
codes exist. The voltage sources driving VREF+ or VREF−
must have very low output impedance and noise.
6.5 INPUT BYPASS CAPACITANCE
External capacitors (0.01 µF to 0.1 µF) can be connected
between the analog input pins, IN0–IN7, and analog ground
to filter any noise caused by inductive pickup associated with
long input leads. It will not degrade the conversion accuracy.
6.6 NOISE
The ADC can be used in either ratiometric or absolute refer-
ence applications. In ratiometric systems, the analog input
voltage is proportional to the voltage used for the ADC’s
reference voltage. When this voltage is the system power
supply, the VREF+ pin is connected to VA+ and VREF− is
connected to GND. This technique relaxes the system refer-
ence stability requirements because the analog input voltage
and the ADC reference voltage move together. This main-
tains the same output code for given input conditions.
The leads to each of the analog multiplexer input pins should
be kept as short as possible. This will minimize input noise
and clock frequency coupling that can cause conversion
errors. Input filtering can be used to reduce the effects of the
noise sources.
6.7 POWER SUPPLIES
Noise spikes on the VA+ and VD+ supply lines can cause
conversion errors; the comparator will respond to the noise.
The ADC is especially sensitive to any power supply spikes
that occur during the auto-zero or linearity correction. Low
inductance tantalum capacitors of 10 µF or greater paral-
leled with 0.1 µF monolithic ceramic capacitors are recom-
mended for supply bypassing. Separate bypass capacitors
should be used for the VA+ and VD+ supplies and placed as
close as possible to these pins.
For absolute accuracy, where the analog input voltage varies
between very specific voltage limits, a time and temperature
stable voltage source can be connected to the reference
inputs. Typically, the reference voltage’s magnitude will re-
quire an initial adjustment to null reference voltage induced
full-scale errors.
6.2 INPUT RANGE
The LM12L458’s fully differential ADC and reference voltage
inputs generate a two’s-complement output that is found by
using the equation below.
6.8 GROUNDING
The LM12L458’s nominal performance can be maximized
through proper grounding techniques. These include the use
of a single ground plane and meticulously separating analog
and digital areas of the board. The use of separate analog
and digital digital planes within the same board area gener-
ally provides best performance. All components that handle
digital signals should be placed within the digital area of the
board, as defined by the digital power plane, while all analog
components should be placed in the analog area of the
board. Such placement and the routing of analog and digital
signal lines within their own respective board areas greatly
reduces the occurrence of ground loops and noise. This will
also minimize EMI/RFI radiation and susceptibility.
Round up to the next integer value between −4096 to 4095
for 12-bit resolution and between −256 to 255 for 8-bit reso-
lution if the result of the above equation is not a whole
It is recommended that stray capacitance between the ana-
log inputs (IN0–IN7, VREF+, and VREF−) be reduced by in-
creasing the clearance (+1/16th inch) between the analog
signal and reference pins and the ground plane.
number. As an example, VREF+ = 2.5V, VREF− = 1V, VIN+
=
1.5V and VIN− = GND. The 12-bit + sign output code is
positive full-scale, or 0,1111,1111,1111. If VREF+ = 3.3V,
VREF− = 1V, VIN+ = 3V, and VIN− = GND, the 12-bit + sign
output code is 0,1100,0000,0000.
6.9 CLOCK SIGNAL CONSIDERATIONS
The LM12L458’s performance is optimized by routing the
analog input/output and reference signal conductors (pins
34–44) as far as possible from the conductor that carries the
clock signal to pin 23.
6.3 INPUT CURRENT
A charging current flows into or out of (depending on the
input voltage polarity) the analog input pins, IN0–IN7 at the
start of the analog input acquisition time (tACQ). This cur-
rent’s peak value will depend on the actual input voltage
applied. This charging current causes voltage spikes at the
inputs. This voltage spikes will not corrupt the conversion
results.
Avoid overshoot and undershoot on the clock line by treating
this line as a transmission line (use proper termination tech-
niques). Failure to do so can result in erratic operation.
Generally, a series 30Ω to 50Ω resistor in the clock line,
located as close to the clock source as possible, will prevent
most problems. The clock source should drive ONLY the
LM12L458 clock pin.
6.4 INPUT SOURCE RESISTANCE
<
For low impedance voltage sources ( 80Ω for 6 MHz opera-
tion) the input charging current will decay, before the end of
the S/H’s acquisition time, to a value that will not introduce
any conversion errors. For higher source impedances, the
S/H’s acquisition time can be increased. As an example,
operating with a 6 MHz clock frequency and maximum ac-
7.0 Common Application Problems
Driving the analog inputs with op-amp(s) powered from
supplies other than the supply used for the LM12L458.
This practice allows for the possibility of the amplifier output
(LM12L458 input) to reach potentials outside of the 0V to
27
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beyond the supply rails, unless the device is specifically
designed to handle this situation, but the LM12L458 is more
sensitive to this condition that most devices. Again, if any pin
experiences a potential more than 100 mV below ground or
above the supply voltage, even on a fast transient basis, the
result could be erratic operation, missing codes, or a com-
plete malfunction, depending upon how far the input is driven
beyond the supply rails. The clock input is the most sensitive
digital one. Generally, a 50Ω series resistor, located very
close to the signal source, will keep digital lines "clean".
7.0 Common Application Problems
(Continued)
VA+ range. This could happen in normal operation if the
amplifier use supply voltages outside of the range of the
LM12L458 supply rails. This could also happen upon power
up if the amplifier supply or supplies ramp up faster than the
supply of the LM12L458. If any pin experiences a potential
more than 100 mV below ground or above the supply volt-
age, even on a fast transient basis, the result could be erratic
operation, missing codes, one channel interacting with one
or more of the others, skipping channels or a complete
malfunction, depending upon how far the input is driven
beyond the supply rails.
Excessive output capacitance on the digital lines. The
current required to charge the capacitance on the digital
outputs can cause noise on the supply bus within the
LM12L458, causing internal supply "bounce" even when the
external supply pin is pretty stable. The current required to
discharge the output capacitance can cause die ground
"bounce". Either of these can cause noise to be induced at
the analog inputs, resulting in conversion errors.
Not performing a full calibration at power up. This can
result in missing codes. The device needs to have a full
calibration run and completed after power up and BEFORE
attempting to perform even a single conversion or watchdog
operation. The only way to recover if this is violated is to
interrupt the power to the device.
Output capacitance should be limited as much as possible. A
series 100Ω resistor in each digital output line, located very
close to the output pin, will limit the charge and discharge
current, minimizing the extent of the conversion errors.
Not waiting for the calibration process to complete be-
fore trying to write to the device. Once a calibration is
requested, the ONLY read of the LM12L458 should be if the
Interrupt Status Register to check for a completed calibra-
tion. Attempting a write or any other read during calibration
would cause a corruption of the calibration process, resulting
in missing codes. The only way to recover would be to
interrupt the power.
Improper CS decoding. If address decoder is used, care
must be exercised to ensure that no "runt" (very narrow)
pulse is produced on the CS line when trying to address
another device or memory. Even sub-nanosecond spikes on
the CS line can cause the chip to be reprogrammed in
accordance with what happens to be on the data lines at the
time. The result is unexpected operation. The worst case
result is that the device is put into the "Test" mode and the
on-board EEPROM that corrects linearity is corrupted. If this
happens, the only recourse is to replace the device.
Improper termination of digital lines. Improper termination
can result in energy reflections that build up to cause over-
shoot that goes above the supply potential and undershoot
that goes below ground. It is never good to drive a device
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28
Physical Dimensions inches (millimeters) unless otherwise noted
Order Number LM12L458CIV
NS Package Number V44A
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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