LM111WGRLQMLV_技术文档

June 30, 2008

LM111QML

Voltage Comparator

General Description

The LM111 is a voltage comparator that has input currents

nearly a thousand times lower than devices such as the

LM106 or LM710. It is also designed to operate over a wider

range of supply voltages: from standard ±15V op amp sup-

plies down to the single 5V supply used for IC logic. The

output is compatible with RTL, DTL and TTL as well as MOS

circuits. Further, it can drive lamps or relays, switching volt-

ages up to 50V at currents as high as 50 mA.

Features

Available with radiation guaranteed

■

High Dose Rate

Low Dose and ELDRS Free

50 krad(Si)

100 krad(Si)

—

Operates from single 5V supply

■

Input current: 200 nA max. over temperature

Offset current: 20 nA max. over temperature

Differential input voltage range: ±30V

Power consumption: 135 mW at ±15V

Power supply voltage, single 5V to ±15V

Offset voltage null capability

Both the inputs and the output of the LM111 can be isolated

from system ground, and the output can drive loads referred

to ground, the positive supply or the negative supply. Offset

balancing and strobe capability are provided and outputs can

be wire OR'ed. Although slower than the LM106 and LM710

(200 ns response time vs 40 ns) the device is also much less

prone to spurious oscillations. The LM111 has the same pin

configuration as the LM106 and LM710.

Strobe capability

Ordering Information

NS PART NUMBER

LM111E-SMD

LM111H-SMD

LM111J-8-SMD

LM111WG-SMD

LM111E/883

SMD PART NUMBER

5962-8687701Q2A

5962-8687701QGA

5962-8687701QPA

5962-8687701QZA

NS PACKAGE NUMBER

PACKAGE DESCRIPTION

20LD Leadless Chip Carrier

8LD TO-99 Metal Can

8LD CERDIP

E20A

H08C

J08A

WG10A

E20A

10LD Ceramic SOIC

20LD Leadless Chip Carrier

8LD TO-99 Metal Can

8LD CERDIP

LM111H/883

H08C

J08A

LM111J-8/883

LM111J/883

J14A

14LD CERDIP

LM111W/883

W10A

WG10A

H08C

10LD CERPACK

LM111WG/883

10LD Ceramic SOIC

8LD TO-99 Metal Can

LM111HLQMLV (Note 12)

High Dose Rate ONLY

5962L0052401VGA

50k rd(Si)

LM111J-8LQMLV (Note 12)

High Dose Rate ONLY

5962L0052401VPA

50k rd(Si)

J08A

WG10A

W10A

H08C

8LD CERDIP

LM111WGLQMLV (Note 12)

High Dose Rate ONLY

5962L0052401VZA

50k rd(Si)

10LD Ceramic SOIC

10LD CERPACK

8LD TO-99 Metal Can

8LD CERDIP

LM111WLQMLV (Note 12)

High Dose Rate ONLY

5962L0052401VHA

50k rd(Si)

LM111HRLQMLV (Note 14)

ELDRS Free ONLY

5962R0052402VGA

100k rd(Si)

LM111J-8RLQMLV (Note 14)

ELDRS Free ONLY

5962R0052402VPA

100k rd(Si)

J08A

LM111WGRLQMLV (Note 14)

ELDRS Free ONLY

5962R0052402VZA

100k rd(Si)

WG10A

W10A

10LD Ceramic SOIC

10LD CERPACK

LM111WRLQMLV (Note 14)

ELDRS Free ONLY

5962R0052402VHA

100k rd(Si)

201285

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Connection Diagrams

Metal Can Package

20128506

Note: Pin 4 connected to case

Top View

See NS Package Number H08C

Dual-In-Line Package

20128534

Top View

See NS Package Number J08A

20128535

Top View

See NS Package Number J14A

20128533

See NS Package Number W10A, WG10A

20128573

See NS Package NumberE20A

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2

Schematic Diagram

(Note Pin connections shown on schematic diagram are for H08 package. )

20128505

Note 1: Pin connections shown on schematic diagram are for H08 package.

3

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Absolute Maximum Ratings (Note 2)

Positive Supply Voltage

Negative Supply Voltage

Total Supply Voltage

+30.0V

-30.0V

36V

Output to Negative Supply Voltage

GND to Negative Supply Voltage

Differential Input Voltage

Sink Current

50V

30V

±30V

50mA

±15V

Input Voltage

(Note 3)

(Note 4)

Power Dissipation

8 LD CERDIP

400mW @ 25°C

330mW @ 25°C

500mW @ 25°C

10 seconds

8 LD Metal Can

10 LD CERPACK

10 LD Ceramic SOIC

20 LD LCC

Output Short Circuit Duration

Maximum Strobe Current

Operating Temperature Range

Thermal Resistance

10mA

-55°C ≤ T_A≤ 125°C

ꢀꢀθ_JA

8 LD CERDIP (Still Air @ 0.5W)

8 LD CERDIP (500LF/Min Air flow @ 0.5W)

8 LD Metal Can (Still Air @ 0.5W)

8 LD Metal Can (500LF/Min Air flow @ 0.5W)

10 Ceramic SOIC (Still Air @ 0.5W)

10 Ceramic SOIC (500LF/Min Air flow @ 0.5W)

10 CERPACK (Still Air @ 0.5W)

10 CERPACK (500LF/Min Air flow @ 0.5W)

14 LD CERDIP (Still Air @ 0.5W)

14 LD CERDIP (500LF/Min Air flow @ 0.5W)

20 LD LCC (Still Air @ 0.5W)

20 LD LCC (500LF/Min Air flow @ 0.5W)

ꢀꢀθ_JC

134°C/W

76°C/W

162°C/W

92°C/W

231°C/W

153°C/W

231°C/W

153°C/W

97°C/W

65°C/W

90°C/W

65°C/W

8 LD CERDIP

21°C/W

50°C/W

24°C/W

20°C/W

21°C/W

8 LD Metal Can Pkg

10 LD Ceramic SOIC

10 LD CERPACK

14 LD CERDIP

20 LD LCC

Storage Temperature Range

Maximum Junction Temperature

Lead Temperature (Soldering, 60 seconds)

Voltage at Strobe Pin

-65°C ≤ T_A≤ 150°C

175°C

300°C

V⁺= -5V

Package Weight (Typical)

8 LD Metal Can

965mg

1100mg

250mg

225mg

TBD

8 LD CERDIP

10 LD CERPACK

10 LD Ceramic SOIC

14 LD CERDIP

20 LD LCC

TBD

ESD Rating

(Note 5)

300V

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4

Recommended Operating Conditions

Supply Voltage

V_CC= ±15V_DC

Operating Temperature Range

-55°C ≤ T_A≤ 125°C

Quality Conformance Inspection

Mil-Std-883, Method 5005 - Group A

Subgroup

Description

Static tests at

Temperature (°C)

1

2

3

+25

+125

-55

4

5

Dynamic tests at

Functional tests at

Switching tests at

+25

+125

-55

6

7

+25

+125

-55

8A

8B

9

+25

+125

-55

10

11

5

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LM111/883 Electrical Characteristics

DC Parameters

The following conditions apply, unless otherwise specified. V₅₆= 0, R_S= 0 Ω, V_CC= ±15V, V_CM= 0, V_O= 1.4V WRT −V_CC

The pin assignments are based on the 8 pin package configuration. (Note 7)

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max Unit

I_IO

Input Offset Current

-10

-20

10

20

nA

1

V_CM= 13.5V, R_S= 50KΩ

2, 3

V_CM= 13.5V, V₈₅= V₈₆= 0V, R_S=

50KΩ

(Note 7)

-30

30

nA

1

-10

-20

10

20

nA

1

V_CM= -14.5V, R_S= 50KΩ

2, 3

V_CM= -14.5V, V₈₅= V₈₆= 0V,

(Note 7)

-30

30

nA

1

R_S= 50KΩ

-10

-20

-30

10

20

nA

V

1

2, 3

1

R_S= 50KΩ

V₈₅= V₈₆= 0V, R_S= 50KΩ

V_CM= 13.5V, R_S= 50KΩ

30

I_IB

Input Bias Current

100

150

100

150

100

150

10

1

2, 3

1

V_CM= -14.5V, R_S= 50KΩ

R_S= 50KΩ

2, 3

1

2, 3

1

I_OL

Output Leakage Current

Ground Leakage Current

Saturation Voltage

V_CC= ± 18V, I₅+ I₆= 5mA,

V_O= 35V WRT -V_CC

(Note 7)

500

25

2, 3

1

I_GL

V_CC= ± 18V, I₅+ I₆= 5mA,

V_O= 50V WRT -V_CC

500

1.5

0.4

5.0

15

2

V_Sat

V_I= -5mV, I₇= 50mA

V_I= -6mV, I₇= 8mA

1, 2, 3

1, 2

3

V

-I_CC

+I_CC

I_L1

Negative Supply Current

Positive Supply Current

Input Leakage Current

mA

nA

6.0

15

1, 2

3

V_CC= ± 18V, V₂₈= 1V,

V₃₈= 30V, I₅+ I₆= 5mA

V_O= 50V WRT -V_CC

(Note 7)

10

1

30

10

30

nA

2

1

2

I_L2

Input Leakage Current

V_CC= ± 18V, V₃₈= 1V,

V₂₈= 30V, I₅+ I₆= 5mA

V_O= 50V WRT -V_CC

V_OSt

Collector Output Voltage (Strobe)

14

V

1

I_St= 3mA

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6

Sub-

groups

Symbol

Parameter

Conditions

Notes

Min Max Unit

V_IO

Input Offset Voltage

V_CM= 13.5V

-3.0

-4.0

-3.0

-4.0

-3.0

-4.0

-3.0

-5.0

-6.0

-3.0

-4.0

-5.0

-6.0

-3.0

-4.0

40

3.0

4.0

3.0

4.0

3.0

4.0

3.0

5.0

6.0

3.0

4.0

5.0

6.0

3.0

4.0

mV

V/mV

1

2, 3

1

V_CM= 13.5V, V₈₅= V₈₆= 0V

V_CM= -14.5V

(Note 7)

1

2, 3

1

V_CM= -14.5V, V₈₅= V₈₆= 0V

1

2, 3

1

V₈₅= V₈₆= 0V

V_O= 0.4V, +V_CC= 4.5V,

-V_CC= 0V, V_CM= 3V

1

2, 3

1

V_O= 4.5V, +V_CC= 4.5V,

-V_CC= 0V, V_CM= 3V

2, 3

1

V_O= 0.4V, +V_CC= 4.5V,

-V_CC= 0V, V_CM= 0.5V

2, 3

1

V_O= 4.5V, +V_CC= 4.5V,

-V_CC= 0V, V_CM= 0.5V

2, 3

4

A_VS

Large Signal Gain

(Note 6)

-12V ≤ V_O≤ 35V, R_L= 1KΩ

30

5, 6

AC Parameters

The following conditions apply, unless otherwise specified. V₅₆= 0, R_S= 0 Ω, V_CC= ±15V, V_CM= 0, V_O= 1.4V WRT −V_CC

The pin assignments are based on the 8 pin package configuration. (Note 7)

Notes

Min Max Unit

400 nS

Sub-

groups

Symbol

tR

Parameter

Response Time

Conditions

7

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LM111-SMD Electrical Characteristics

DC Parameters

SMD 5962-8687701

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

V_IO

Parameter

Conditions

V_I= 0V, R_S= 50Ω

Notes

Min Max Unit

Input Offset Voltage

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

1

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.0 +4.0 mV

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

2, 3

1

+V_CC= +2.5V, -V_CC= -2.5V,

V_I= 0V,

2, 3

R_S= 50Ω

V_IO

R

Raised Input Offset Voltage

-3.0 +3.0 mV

-4.5 +4.5 mV

1

V_I= 0V, R_S= 50Ω

(Note 15)

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-3

+3

mV

-4.5 +4.5 mV

2, 3

+V_CC= 2V, -V_CC= -28V,

-3.0 +3.0 mV

-4.5 +4.5 mV

1

V_I= 0V, V_CM= +13V, R_S= 50Ω

2, 3

1, 2

3

I_IO

Input Offset Current

-10

-20

-10

+10 nA

+20 nA

+10 nA

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-20

-10

-20

+20 nA

+10 nA

+20 nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

I_IOR

±I_IB

Raised Input Offset Current

Input Bias Current

-25

-50

+25 nA

+50 nA

1, 2

3

V_I= 0V, R_S= 50KΩ

(Note 15)

-100 0.1

-150 0.1

nA

1, 2

3

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-200 0.1

-150 0.1

-200 0.1

nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

V_OSt

Collector Output Voltage (Strobe) +V_I= Gnd, -V_I= 15V,

I_St= -3mA, R_S= 50Ω

(Notes 8,

13)

14

80

V

1, 2, 3

CMRR

Common Mode Rejection Ratio

-28V ≤ -V_CC≤ -0.5V, R_S= 50Ω,

dB

2V ≤ +V_CC≤ 29.5V, R_S= 50Ω,

-14.5V ≤ V_CM≤ 13V, R_S= 50Ω

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8

Sub-

groups

Symbol

V_OL

Parameter

Conditions

Notes

Min Max Unit

Low Level Output Voltage

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 0.71V,

V_ID= -6mV

0.4

V

1, 2, 3

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= −1.75V,

V_ID= -6mV

I_O= 50mA, ±V_I= 13V,

V_ID= -5mV

1.5

V

1, 2, 3

I_O= 50mA, ±V_l= -14V,

V_ID= -5mV

I_CEX

I_L

Output Leakage Current

Input Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-1.0 10

nA

1

2

-1.0 500

+V_CC= 18V, -V_CC= -18V,

+V_I= +12V, -V_I= -17V

(Note 11) -5.0 500

nA

1, 2, 3

+V_CC= 18V, -V_CC= -18V,

+V_I= -17V, -V_I= +12V

+I_CC

Power Supply Current

6.0

mA

1, 2

3

7.0

-I_CC

-5.0

-6.0

1, 2

3

Temperature Coefficient Input

Offset Voltage

(Notes 11,

13)

Δ V_IO/ ΔT

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

-25

25

µV/°C

pA/°C

2

3

2

3

(Notes 11,

13)

Temperature Coefficient Input

Offset Current

(Notes 11,

13)

Δ I_IO/ ΔT

-100 100

-200 200

(Notes 11,

13)

I_OS

Short Circuit Current

(Note 10)

200

150

mA

mV

1

2

3

1

V_O= 5V, t ≤ 10mS, -V_I= 0.1V,

+V_I= 0V

250

+V_IOadj.

-V_IOadj.

±A_VE

Input Offset Voltage (Adjustment)

Voltage Gain (Emitter)

V_O= 0V, V_I= 0V, R_S= 50Ω

R_L= 600Ω

5.0

-5.0 mV

1

(Note 6)

10

V/mV

4

8.0

5, 6

AC Parameters SMD 5962-8687701

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

tR_LHC

Parameter

Conditions

Notes

Min Max

Unit

Response Time (Collector

Output)

V_OD(Overdrive) = -5mV,

C_L= 50pF, V_I= -100mV

(Note 13)

300

640

300

500

nS

7, 8B

8A

tR_HLC

Response Time (Collector

Output)

V_OD(Overdrive) = 5mV,

C_L= 50pF, V_I= 100mV

7, 8B

8A

9

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LM111 RADIATION Electrical Characteristics SMD 5962L0052401

DC Parameters

(Note 12)

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

V_IO

Parameter

Conditions

V_I= 0V, R_S= 50Ω

Notes

Min Max Unit

Input Offset Voltage

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

1

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.0 +4.0 mV

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

2, 3

+V_CC= +2.5V, -V_CC= -2.5V,

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.5 +4.5 mV

-3.0 +3.0 mV

1

V_I= 0V, R_S= 50Ω

2, 3

1

V_IO

R

Raised Input Offset Voltage

V_I= 0V, R_S= 50Ω

(Note 15)

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.5 +4.5 mV

-3.0 +3.0 mV

-4.5 +4.5 mV

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

(Note 15)

2, 3

I_IO

Input Offset Current

-10

-20

-10

+10 nA

+20 nA

+10 nA

1, 2

3

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-20

-10

-20

+20 nA

+10 nA

+20 nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

I_IOR

±I_IB

Raised Input Offset Current

Input Bias Current

-25

-50

+25 nA

+50 nA

1, 2

3

V_I= 0V, R_S= 50KΩ

(Note 15)

-100 0.1

-150 0.1

nA

1, 2

3

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-200 0.1

-150 0.1

-200 0.1

nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

V_OSt

Collector Output Voltage (Strobe) +V_I= Gnd, -V_I= 15V,

I_St= -3mA, R_S= 50Ω

(Notes 8,

13)

14

80

V

1, 2, 3

CMRR

Common Mode Rejection Ratio

-28V ≤ -V_CC≤ -0.5V, R_S= 50Ω,

dB

2V ≤ +V_CC≤ 29.5V, R_S= 50Ω,

-14.5V ≤ V_CM≤ 13V, R_S= 50Ω

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10

Sub-

groups

Symbol

V_OL

Parameter

Conditions

Notes

Min Max Unit

Low Level Output Voltage

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 0.5V,

V_ID= -6mV

0.4

V

1, 2, 3

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 3V,

V_ID= -6mV

I_O= 50mA, ±V_I= 13V,

V_ID= -5mV

1.5

V

1, 2, 3

I_O= 50mA, ±V_I= -14V,

V_ID= -5mV

I_CEX

I_L

Output Leakage Current

Input Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-1.0 10

nA

1

2

-1.0 500

+V_CC= 18V, -V_CC= -18V,

+V_I= +12V, -V_I= -17V

(Note 11) -5.0 500

nA

1, 2, 3

+V_CC= 18V, -V_CC= -18V,

+V_I= -17V, -V_I= +12V

+I_CC

Power Supply Current

6.0

7.0

mA

1, 2

3

mA

-I_CC

-5.0

mA

1, 2

3

-6.0

mA

Temperature Coefficient Input

Offset Voltage

-25

25

µV/°C

2

ΔV_IO/ ΔT

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

µV/°C

pA/°C

3

2

Temperature Coefficient Input

Offset Current

-100 100

Δ I_IO/ ΔT

-200 200

200

pA/°C

mA

3

1

2

3

1

I_OS

Short Circuit Current

(Note 10)

V_O= 5V, t ≤ 10mS, -V_I= 0.1V,

+V_I= 0V

150

mA

250

mA

+V_IOadj.

-V_IOadj.

±A_VE

Input Offset Voltage (Adjustment)

Voltage Gain (Emitter)

V_O= 0V, V_I= 0V, R_S= 50Ω

R_L= 600Ω

5.0

mV

-5.0 mV

1

(Note 6)

10

V/mV

4

8.0

5, 6

AC Parameters SMD 5962L0052401

(Note 12)

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

tR_LHC

Parameter

Conditions

Notes

Min Max

Unit

Response Time (Collector

Output)

V_OD(Overdrive) = -5mV,

C_L= 50pF, V_I= -100mV

300

640

300

500

nS

7, 8B

8A

(Note 13)

tR_HLC

Response Time (Collector

Output)

V_OD(Overdrive) = 5mV,

C_L= 50pF, V_I= 100mV

7, 8B

8A

11

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DC DELTA Parameters SMD 5962L0052401

(Note 12)

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Delta calculations performed on QMLV devices at group B , subgroup 5.

Sub-

groups

Symbol

V_IO

Parameter

Conditions

Notes

Min Max

Unit

Input Offset Voltage

V_I= 0V, R_S= 50Ω

-0.5

0.5

mV

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

mV

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

-0.5

0.5

mV

nA

1

±I_IB

Input Bias Current

V_I= 0V, R_S= 50KΩ

-12.5 12.5

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

-12.5 12.5

nA

1

I_CEX

Output Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-5.0

5.0

Post Radiation Parameters SMD 5962L0052401

(Note 12)

The following conditions apply, unless otherwise specified

Sub-

groups

Symbol

I_IO

Parameter

Conditions

Notes

Min Max

Unit

Input Offset Current

+V_CC= 29.5V, −V_CC= −0.5V, V_I=

0V, V_CM= −14.5V,

−50 +50

nA

1

R_S= 50KΩ

+V_CC= 2V, −V_CC= −28V,

−50 +50

nA

1

V_I= 0V, V_CM= +13V, R_S= 50KΩ

±I_IB

Input Bias Current

−150 0.1

−175 0.1

nA

1

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, −V_CC= −0.5V, V_I=

0V, V_CM= −14.5V,

R_S= 50KΩ

I_CEX

Output Leakage Current

+V_CC= 18V, −V_CC= −18V,

V_O= 32V

−25 +25

nA

1

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12

LM111 RADIATION Electrical Characteristics SMD 5962R0052402

DC Parameters

(Note 14)

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

V_IO

Parameter

Conditions

V_I= 0V, R_S= 50Ω

Notes

Min Max Unit

Input Offset Voltage

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

1

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.0 +4.0 mV

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

2, 3

+V_CC= +2.5V, -V_CC= -2.5V,

-3.0 +3.0 mV

-4.0 +4.0 mV

-3.0 +3.0 mV

-4.5 +4.5 mV

-3.0 +3.0 mV

1

V_I= 0V, R_S= 50Ω

2, 3

1

V_IO

R

Raised Input Offset Voltage

V_I= 0V, R_S= 50Ω

(Note 15)

2, 3

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

-4.5 +4.5 mV

-3.0 +3.0 mV

-4.5 +4.5 mV

2, 3

1

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

(Note 15)

2, 3

I_IO

Input Offset Current

-10

-20

-10

+10 nA

+20 nA

+10 nA

1, 2

3

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-20

-10

-20

+20 nA

+10 nA

+20 nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

I_IOR

±I_IB

Raised Input Offset Current

Input Bias Current

-25

-50

+25 nA

+50 nA

1, 2

3

V_I= 0V, R_S= 50KΩ

(Note 15)

-100 0.1

-150 0.1

nA

1, 2

3

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

1, 2

-200 0.1

-150 0.1

-200 0.1

nA

3

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

1, 2

3

V_OSt

Collector Output Voltage (Strobe) +V_I= Gnd, -V_I= 15V,

I_St= -3mA, R_S= 50Ω

(Notes 8,

13)

14

80

V

1, 2, 3

CMRR

Common Mode Rejection Ratio

-28V ≤ -V_CC≤ -0.5V, R_S= 50Ω,

dB

2V ≤ +V_CC≤ 29.5V, R_S= 50Ω,

-14.5V ≤ V_CM≤ 13V, R_S= 50Ω

13

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Sub-

groups

Symbol

V_OL

Parameter

Conditions

Notes

Min Max Unit

Low Level Output Voltage

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 0.5V,

V_ID= -6mV

0.4

V

1, 2, 3

+V_CC= 4.5V, -V_CC= Gnd,

I_O= 8mA, ±V_I= 3V,

V_ID= -6mV

I_O= 50mA, ±V_I= 13V,

V_ID= -5mV

1.5

V

1, 2, 3

I_O= 50mA, ±V_I= -14V,

V_ID= -5mV

I_CEX

I_L

Output Leakage Current

Input Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-1.0 10

nA

1

2

-1.0 500

+V_CC= 18V, -V_CC= -18V,

+V_I= +12V, -V_I= -17V

(Note 11) -5.0 500

nA

1, 2, 3

+V_CC= 18V, -V_CC= -18V,

+V_I= -17V, -V_I= +12V

+I_CC

Power Supply Current

6.0

7.0

mA

1, 2

3

mA

-I_CC

-5.0

mA

1, 2

3

-6.0

mA

Temperature Coefficient Input

Offset Voltage

-25

25

µV/°C

2

ΔV_IO/ ΔT

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

25°C ≤ T ≤ 125°C

-55°C ≤ T ≤ 25°C

µV/°C

pA/°C

3

2

Temperature Coefficient Input

Offset Current

-100 100

Δ I_IO/ ΔT

-200 200

200

pA/°C

mA

3

1

2

3

1

I_OS

Short Circuit Current

(Note 10)

(Note 11)

V_O= 5V, t ≤ 10mS, -V_I= 0.1V,

+V_I= 0V

150

mA

250

mA

+V_IOadj.

-V_IOadj.

±A_VE

Input Offset Voltage (Adjustment)

Voltage Gain (Emitter)

V_O= 0V, V_I= 0V, R_S= 50Ω

R_L= 600Ω

5.0

mV

-5.0 mV

1

(Note 7)

10

V/mV

4

8.0

5, 6

AC Parameters SMD 5962R0052402

(Note 14)

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Sub-

groups

Symbol

tR_LHC

Parameter

Conditions

Notes

Min Max

Unit

Response Time (Collector

Output)

V_OD(Overdrive) = -5mV,

C_L= 50pF, V_I= -100mV

300

640

300

500

nS

7, 8B

8A

(Note 13)

tR_HLC

Response Time (Collector

Output)

V_OD(Overdrive) = 5mV,

C_L= 50pF, V_I= 100mV

7, 8B

8A

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14

DC DELTA Parameters SMD 5962R0052402

The following conditions apply, unless otherwise specified. V_CC= ±15V, V_CM= 0

Delta calculations performed on QMLV devices at group B , subgroup 5.

(Note 14)

Sub-

groups

Symbol

V_IO

Parameter

Conditions

Notes

Min Max

Unit

Input Offset Voltage

V_I= 0V, R_S= 50Ω

-0.5

0.5

mV

1

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50Ω

mV

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50Ω

-0.5

0.5

mV

nA

1

±I_IB

Input Bias Current

V_I= 0V, R_S= 50KΩ

-12.5 12.5

+V_CC= 29.5V, -V_CC= -0.5V,

V_I= 0V, V_CM= -14.5V,

R_S= 50KΩ

+V_CC= 2V, -V_CC= -28V,

V_I= 0V, V_CM= +13V,

R_S= 50KΩ

-12.5 12.5

nA

1

I_CEX

Output Leakage Current

+V_CC= 18V, -V_CC= -18V,

V_O= 32V

-5.0

5.0

Post Radiation Parameters SMD 5962R0052402

(Note 14)

The following conditions apply, unless otherwise specified

Sub-

groups

Symbol

I_IOR

Parameter

Conditions

Notes

Min Max

Unit

Raised Input Offset Current

Input Bias Current

(Note 15)

−100 +100

−180 0.1

−225 0.1

nA

1

V_I= 0V, R_S= 50KΩ

±I_IB

V_I= 0V, R_S= 50KΩ

+V_CC= 29.5V, −V_CC= −0.5V, V_I=

0V, V_CM= −14.5V, R_S= 50KΩ

I_CEX

Output Leakage Current

+V_CC= 18V, −V_CC= −18V,

V_O= 32V

−1.0 +25

nA

1

Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics. The guaranteed

specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under the listed test

conditions.

Note 3: This rating applies for ±15V supplies. The positive input voltage limits is 30 V above the negative supply. The negative input voltage limits is equal to the

negative supply voltage or 30V below the positive supply, whichever is less.

Note 4: The maximum power dissipation must be derated at elevated temperatures and is dictated by T_Jmax(maximum junction temperature), θ_JA(package

junction to ambient thermal resistance), and T_A(ambient temperature). The maximum allowable power dissipation at any temperature is P_Dmax= (T_Jmax- T_A)/

θ

_JAor the number given in the Absolute Maximum Ratings, whichever is lower.

Note 5: Human body model, 1.5 kΩ in series with 100 pF.

Note 6: Datalog reading in K=V/mV.

Note 7: Pin names based on an 8 pin package configuration. When using higher pin count packages then:

Pin 2 & 3 are Inputs, Pin 5 is Balance, Pin 6 is

Balance / Strobe, Pin 7 is Output, and Pin 8 is V⁺. For example:

V₅₆is the Voltage between the Balance and Balance / Strobe pins

Note 8: I_ST= −2mA at −55°C

Note 9: Calculated parameter.

Note 10: Actual min. limit used is 5mA due to test setup.

Note 11: V_IDis voltage difference between inputs.

Note 12: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.

These parts may be dose rate sensitive in a space environment and demonstrate enhanced low dose rate effect. Radiation end point limits for the noted parameters

are guaranteed only for the conditions as specified in Mil-Std-883, Method 1019, Condition A.

Note 13: Group A sample ONLY

Note 14: Pre and post irradiation limits are identical to those listed under AC and DC electrical characteristics except as listed in the Post Radiation Limits Table.

These parts may be sensitive in a high dose environment. Low dose rate testing has been performed on a wafer-by-wafer basis, per test method 1019 condition

D of MIL-STD-883, with no enhanced low dose rate sensitivity (ELDRS) effect.

Note 15: Subscript (R) indicates tests which are performed with input stage current raised by connecting BAL and BAL/STB terminals to +V_CC

.

15

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LM111 Typical Performance Characteristics

Input Bias Current

20128543

20128544

Input Bias Current

20128546

20128545

Input Bias Current

20128547

20128548

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16

Input Bias Current

Input Overdrives

Input Bias Current

Input Overdrives

20128550

20128549

Input Bias Current

Response Time for Various

Input Overdrives

20128551

20128552

Response Time for Various

Input Overdrives

Output Limiting Characteristics

20128554

20128553

17

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Supply Current

20128555

20128556

Leakage Currents

20128557

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18

engineered thoughtfully. Preferably there should be a

ground plane under the LM111 circuitry, for example, one

side of a double-layer circuit card. Ground foil (or,

positive supply or negative supply foil) should extend

between the output and the inputs, to act as a guard. The

foil connections for the inputs should be as small and

compact as possible, and should be essentially

surrounded by ground foil on all sides, to guard against

capacitive coupling from any high-level signals (such as

the output). If pins 5 and 6 are not used, they should be

shorted together. If they are connected to a trim-pot, the

trim-pot should be located, at most, a few inches away

from the LM111, and the 0.01 μF capacitor should be

installed. If this capacitor cannot be used, a shielding

printed-circuit foil may be advisable between pins 6 and

7. The power supply bypass capacitors should be located

within a couple inches of the LM111. (Some other

comparators require the power-supply bypass to be

located immediately adjacent to the comparator.)

Application Hints

CIRCUIT TECHNIQUES FOR AVOIDING

OSCILLATIONS IN COMPARATOR APPLICATIONS

When a high-speed comparator such as the LM111 is used

with fast input signals and low source impedances, the output

response will normally be fast and stable, assuming that the

power supplies have been bypassed (with 0.1 μF disc capac-

itors), and that the output signal is routed well away from the

inputs (pins 2 and 3) and also away from pins 5 and 6.

However, when the input signal is a voltage ramp or a slow

sine wave, or if the signal source impedance is high (1 kΩ to

100 kΩ), the comparator may burst into oscillation near the

crossing-point. This is due to the high gain and wide band-

width of comparators like the LM111. To avoid oscillation or

instability in such a usage, several precautions are recom-

mended, as shown in Figure 1 below.

1. The trim pins (pins 5 and 6) act as unwanted auxiliary

inputs. If these pins are not connected to a trim-pot, they

should be shorted together. If they are connected to a

trim-pot, a 0.01 μF capacitor C1 between pins 5 and 6

will minimize the susceptibility to AC coupling. A smaller

capacitor is used if pin 5 is used for positive feedback as

in Figure 1.

6. It is a standard procedure to use hysteresis (positive

feedback) around a comparator, to prevent oscillation,

and to avoid excessive noise on the output because the

comparator is a good amplifier for its own noise. In the

circuit of Figure 2, the feedback from the output to the

positive input will cause about 3 mV of hysteresis.

However, if R_Sis larger than 100Ω, such as 50 kΩ, it

would not be reasonable to simply increase the value of

the positive feedback resistor above 510 kΩ. The circuit

of Figure 3 could be used, but it is rather awkward. See

the notes in paragraph 7 below.

2. Certain sources will produce a cleaner comparator

output waveform if a 100 pF to 1000 pF capacitor C2 is

connected directly across the input pins.

3. When the signal source is applied through a resistive

network, R_S, it is usually advantageous to choose an R_S

′ of substantially the same value, both for DC and for

dynamic (AC) considerations. Carbon, tin-oxide, and

metal-film resistors have all been used successfully in

comparator input circuitry. Inductive wire wound resistors

are not suitable.

7. When both inputs of the LM111 are connected to active

signals, or if a high-impedance signal is driving the

positive input of the LM111 so that positive feedback

would be disruptive, the circuit of Figure 1 is ideal. The

positive feedback is to pin 5 (one of the offset adjustment

pins). It is sufficient to cause 1 to 2 mV hysteresis and

sharp transitions with input triangle waves from a few Hz

to hundreds of kHz. The positive-feedback signal across

the 82Ω resistor swings 240 mV below the positive

supply. This signal is centered around the nominal

voltage at pin 5, so this feedback does not add to the

V_OSof the comparator. As much as 8 mV of V_OScan be

trimmed out, using the 5 kΩ pot and 3 kΩ resistor as

shown.

4. When comparator circuits use input resistors (e.g.

summing resistors), their value and placement are

particularly important. In all cases the body of the resistor

should be close to the device or socket. In other words

there should be very little lead length or printed-circuit foil

run between comparator and resistor to radiate or pick

up signals. The same applies to capacitors, pots, etc. For

example, if R_S=10 kΩ, as little as 5 inches of lead

between the resistors and the input pins can result in

oscillations that are very hard to damp. Twisting these

input leads tightly is the only (second best) alternative to

placing resistors close to the comparator.

8. These application notes apply specifically to the LM111

and are applicable to all high-speed comparators in

general, (with the exception that not all comparators have

trim pins).

5. Since feedback to almost any pin of a comparator can

result in oscillation, the printed-circuit layout should be

19

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20128529

Pin connections shown are for LM111H in the H08 hermetic package

FIGURE 1. Improved Positive Feedback

20128530

Pin connections shown are for LM111H in the H08 hermetic package

FIGURE 2. Conventional Positive Feedback

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20

20128531

FIGURE 3. Positive Feedback with High Source Resistance

21

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Typical Applications (Note 18)

Offset Balancing

Strobing

20128536

20128537

Note: Do Not Ground Strobe Pin. Output is turned off when current is pulled from

Strobe Pin.

Detector for Magnetic Transducer

Increasing Input Stage Current (Note Increases typical

common mode slew from 7.0V/μs to 18V/μs. )

20128538

Note 16: Increases typical common mode slew from 7.0V/μs to 18V/μs.

20128539

Digital Transmission Isolator

Relay Driver with Strobe

20128540

20128541

*Absorbs inductive kickback of relay and protects IC from severe voltage tran-

sients on V⁺⁺line.

Note: Do Not Ground Strobe Pin.

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22

Strobing off Both Input and Output Stages (Note Typical input current is 50 pA with inputs strobed off. )

20128542

Note: Do Not Ground Strobe Pin.

Note 17: Typical input current is 50 pA with inputs strobed off.

Note 18: Pin connections shown on schematic diagram and typical applications are for H08 metal can package.

Positive Peak Detector

Zero Crossing Detector Driving MOS Logic

20128524

20128523

*Solid tantalum

Typical Applications for H08 Package

(Pin numbers refer to H08 package)

Zero Crossing Detector Driving MOS Switch

100 kHz Free Running Multivibrator

20128513

20128514

*TTL or DTL fanout of two

23

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10 Hz to 10 kHz Voltage Controlled Oscillator

20128515

*Adjust for symmetrical square wave time when V_IN= 5 mV

†Minimum capacitance 20 pF Maximum frequency 50 kHz

Driving Ground-Referred Load

Using Clamp Diodes to Improve Response

20128517

20128516

*Input polarity is reversed when using pin 1 as output.

TTL Interface with High Level Logic

20128518

*Values shown are for a 0 to 30V logic swing and a 15V threshold.

†May be added to control speed and reduce susceptibility to noise spikes.

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24

Crystal Oscillator

Comparator and Solenoid Driver

20128520

20128519

Precision Squarer

20128521

*Solid tantalum

†Adjust to set clamp level

Low Voltage Adjustable Reference Supply

20128522

*Solid tantalum

25

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Positive Peak Detector

Zero Crossing Detector Driving MOS Logic

20128524

20128523

*Solid tantalum

Negative Peak Detector

20128525

*Solid tantalum

Precision Photodiode Comparator

20128526

*R2 sets the comparison level. At comparison, the photodiode has less than 5 mV across it, decreasing leakages by an order of magnitude.

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26

Switching Power Amplifier

20128527

27

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Switching Power Amplifier

20128528

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28

Revision History

Released

10/11/05

Revision

Section

Originator

Changes

A

New Release, Corporate format

L. Lytle

3 MDS data sheets converted into one Corp.

data sheet format. MNLM111-X Rev 0A0,

MDLM111-X Rev. 0B0, and MRLM111-X-RH

Rev 0E1. The drift table was eliminated from

the 883 section since it did not apply; Note #3

was removed from RH & QML datasheets with

SG verification that it no longer applied. Added

NSID's for 50k Rad and Post Radiation Table.

MDS data sheets will be archived.

12/14/05

B

Ordering Information Table

R. Malone

Removed NSID reference LM111J-8PQMLV,

5962P0052401VPA

30k rd(Si). Reason: NSID on LTB, Inventory

exhausted. Added following NSID's:

LM111HPQMLV, LM111WPQMLV and

LM111WGPQMLV. Reason: Still have

Inventory. LM111QML, Revision A will be

archived.

06/26/08

C

Features, Ordering Information Table, Larry McGee Added Radiation reference, ELDRS NSID's

Electrical section Notes.

and Note 14 and 15, Low Dose Electrical

Table. Deleted 30k rd(Si) NSID's:

LM111HPQMLV, LM111WPQMLV and

LM111WGPQMLV. Reason: EOL 9/06/05.

Revision B will be archived.

29

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Physical Dimensions inches (millimeters) unless otherwise noted

Metal Can Package (H)

NS Package Number H08C

Cavity Dual-In-Line Package (J)

NS Package Number J08A

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30

Dual-In-Line Package (J)

NS Package Number J14A

Leadless Chip Carrier (E)

NS Package Number E20A

31

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Cerpack Package (W)

NS Package Number W10A

Cerpack Gull Wing Package (WG)

NS Package Number WG10A

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32

Notes

33

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型号：	LM111WGRLQMLV
厂家：	National Semiconductor
描述：	Voltage Comparator 电压比较器比较器
文件：	总34页 (文件大小：1006K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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