HPC467064EL20 [NSC]
High-Performance microController with a 16k UV Erasable CMOS EPROM; 高性能微控制器，带有16K的紫外线可擦除CMOS EPROM
| 型号： | HPC467064EL20 |
| 厂家： | 
National Semiconductor |
| 描述： | High-Performance microController with a 16k UV Erasable CMOS EPROM |
| 文件： | 总34页 (文件大小：408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
August 1992
HPC167064/HPC467064 High-Performance
microController with a 16k UV Erasable CMOS EPROM
General Description
The HPC167064 is a member of the HPC family of High
Performance microControllers. Each member of the family
has the same core CPU with a unique memory and I/O
configuration to suit specific applications. The HPC167064
has a 16 kbyte, high-speed, UV-erasable, electrically pro-
grammable CMOS EPROM. This is ideally suited for appli-
cations where fast turnaround, pattern experimentation, and
code confidentiality are important requirements. The
HPC167064 can serve as a stand-alone emulator for either
the HPC16064 or the HPC16083. Two configuration regis-
ters have been added for emulation of the different chips.
The on-chip EPROM replaces the presently available user
ROM space. The on-chip EPROM can be programmed via a
DATA I/O UNISITE. There are security features added to
the chip to implement READ, ENCRYPTED READ, and
WRITE privileges for the on-chip EPROM. These defined
privileges are intended to deter theft, alteration, or uninten-
tional destruction of user code. Each part is fabricated in
National’s advanced microCMOS technology. This process
combined with an advanced architecture provides fast, flex-
ible I/O control, efficient data manipulation, and high speed
computation.
further current savings. The HPC167064 is available only in
68-pin LDCC package.
Features
Y
HPC familyÐcore features:
Ð 16-bit architecture, both byte and word operations
Ð 16-bit data bus, ALU, and registers
Ð 64 kbytes of direct memory addressing
Ð FASTÐ200 ns for fastest instruction when using
20.0 MHz clock, 134 ns at 30.0 MHz
Ð High code efficiencyÐmost instructions are single
byte
Ð 16 x 16 multiply and 32 x 16 divide
Ð Eight vectored interrupt sources
Ð Four 16-bit timer/counters with 4 synchronous out-
puts and WATCHDOG logic
Ð MICROWIRE/PLUS serial I/O interface
Ð CMOSÐvery low power with two power save modes:
IDLE and HALT
Y
16 kbytes high speed UV erasable: electrically program-
mable CMOS EPROM
Y
Stand-alone emulation of HPC16083 and HPC16064
family
The HPC devices are complete microcomputers on a single
chip. All system timing, internal logic, EPROM, RAM, and
I/O are provided on the chip to produce a cost effective
solution for high performance applications. On-chip func-
tions such as UART, up to eight 16-bit timers with 4 input
capture registers, vectored interrupts, WATCHDOGTM logic
and MICROWIRE/PLUSTM provide a high level of system
integration. The ability to address up to 64k bytes of exter-
nal memory enables the HPC to be used in powerful appli-
cations typically performed by microprocessors and expen-
sive peripheral chips.
Y
EPROM and configuration bytes programmable by
DATA I/O UNISITE with Pinsite Module
Y
Four selectable levels of security to protect on-chip
EPROM contents
Y
UARTÐfull duplex, programmable baud rate
Y
Four additional 16-bit timer/counters with pulse width
modulated outputs
Y
Four input capture registers
Y
52 general purpose I/O lines (memory mapped)
Y
a
125 C) temperature ranges for 20.0 MHz, commercial
b
55 C to
Commercial (0 C to
a
70 C), and military
(
§
§
§
The microCMOS process results in very low current drain
and enables the user to select the optimum speed/power
product for his system. The IDLE and HALT modes provide
§
(0 C to 70 C) for 30.0 MHz
a
§
§
Block Diagram (HPC167064 with 16k EPROM shown)
TL/DD/11046–1
Series 32000É and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
MICROWIRE/PLUSTM and WATCHDOGTM are trademarks of National Semiconductor Corporation.
UNIXÉ is a registered trademark of AT & T Bell Laboratories.
IBMÉ and PC-ATÉ are registered trademarks of International Business Machines Corp.
SunOSTM is a trademark of Sun Microsystems.
C
1995 National Semiconductor Corporation
TL/DD11046
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
0.5V to 7.0V
V
with Respect to GND
CC
a
b
0.5V) to (GND 0.5V)
All Other Pins
(V
CC
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. DC and AC electri-
cal specifications are not ensured when operating the de-
vice at absolute maximum ratings.
Total Allowable Source or Sink Current
Storage Temperature Range
100 mA
b
a
65 C to 150 C
§
§
Lead Temperature (Soldering, 10 sec.)
300 C
§
DC Electrical Characteristics
e
otherwise specified, T
e b
a
55 C to 125 C for HPC167064 and V
e
5.0V
CC
g
5.0V 5% unless otherwise specified, T
g
10% unless
V
§
§
CC
A
0 C to 70 C for HPC467064
e
§
§
A
Symbol
Parameter
Test Conditions
Min
Max
85
Units
mA
e
e
e
e
e
e
I
I
I
Supply Current
V
V
V
max, f
max, f
max, f
30.0 MHz (Note 1)
20.0 MHz (Note 1)
2.0 MHz (Note 1)
CC
CC
CC
CC
CC
CC
IN
IN
IN
1
2
3
70
40
mA
mA
e
e
e
e
e
e
IDLE Mode Current
HALT Mode Current
V
CC
V
CC
V
CC
max, f
max, f
max, f
30.0 MHz (Note 1)
20.0 MHz, (Note 1)
2.0 MHz, (Note 1)
6.0
4.5
1
mA
mA
mA
IN
IN
IN
e
e
e
e
V
V
max, f
0 kHz, (Note 1)
0 kHz, (Note 1)
400
100
mA
mA
CC
IN
2.5V, f
IN
CC
INPUT VOLTAGE LEVELS FOR SCHMITT TRIGGERED INPUTS RESET, NMI, AND WO; AND ALSO CKI
V
IH1
IL1
Logic High
Logic Low
0.9 V
V
V
CC
V
0.1 V
CC
ALL OTHER INPUTS
V
V
Logic High
0.7 V
*
V
IH2
CC
Logic Low
*
0.2 V
V
IL2
CC
e
e
e
g
I
I
I
I
Input Leakage Current
Input Leakage Current RDY/HLD, EXUI
Input Leakage Current B12
Input Leakage Current EXM
Input Capacitance
V
V
0 and V
0
V
CC
(Note 4)
(Note 4)
2
mA
mA
mA
mA
pF
pF
LI1
IN
IN
b
b
50
3
LI2
LI3
LI4
IN
e
e
e
RESET
0, V
V
CC
0.5
7
IN
IN
e
g
10
V
IN
0 and V
V
CC
C
C
(Note 2)
(Note 2)
10
20
I
I/O Capacitance
IO
OUTPUT VOLTAGE LEVELS
e b
b
0.1
V
V
Logic High (CMOS)
Logic Low (CMOS)
I
I
10 mA (Note 2)
V
CC
OH1
OH
0.1
0.4
0.4
0.4
V
V
V
V
e
10 mA (Note 2)
OL1
OH
e b
V
V
Port A/B Drive, CK2
I
I
7 mA
3 mA
e b
2.4
2.4
2.4
OH2
OH
e
(A0–A15, B10, B11, B12, B15)
OL2
OL
V
V
Other Port Pin Drive, WO (open drain)
(B0–B9, B13, B14, P0–P3)
I
I
1.6 mA (except WO)
OH3
OH
e
0.5 mA
OL3
OL
e b
V
V
ST1 and ST2 Drive
I
I
6 mA
OH4
OH
e
1.6 mA
OL4
OL
e b
V
V
Port A/B Drive (A0–15, B10, B11, B12, B15)
when used as External Address/Data Bus
I
I
1 mA
2.4
2.5
OH5
OH
0.4
V
e
3 mA
OL5
OL
V
I
RAM Keep-Alive Voltage
(Note 3)
V
CC
V
RAM
e
e
g
TRI-STATE Leakage Current
É
V
0 and V
V
CC
5
mA
OZ
IN
IN
e
e
e
e
is measured with RESET GND. I
Note 1: I
, I measured with no external drive (I
CC CC CC OH
3
, I
and I
OL
0, I , I
IH IL
0 and EXM
V
). I
CC CC1
is measured
CC3
1
e
2
with NMI
V
. CKI driven to V
and V
with rise and fall times less than 10 ns.
IL1
CC
IH1
Note 2: This is guaranteed by design and not tested.
Note 3: Test duration is 100 ms.
Note 4: The EPROM mode of operation for this device requires high voltage input on pins EXM/V , I3, I4, I5, I6 and I7. This will increase the input leakage current
PP
a
above the normal specification when driven to voltages greater than V
0.3V.
CC
*See NORMAL RUNNING MODE.
2
20 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figures 1 thru 5 ). V
CC
e
e b
a
e
55 C to 125 C for HPC167064 and V
CC
g
g
5V 10%,
5V 5%*, T
§
§
A
e
a
0 C to 70 C for HPC467064
T
§
§
A
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
t
t
t
t
t
t
t
CKI Operating Frequency
CKI Clock Period
CKI High Time
2
50
20
MHz
ns
C
e
1/f
500
C1
C
22.5
22.5
100
100
0
ns
CKIH
CKI Low Time
ns
CKIL
e
2/f
e
CPU Timing Cycle
CPU Wait State Period
ns
C
C
t
ns
WAIT
C
Delay of CK2 Rising Edge after CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
55
55
ns
(Note 2)
(Note 2)
DC1C2R
DC1C2F
0
ns
e
f
f
f /8
C
External UART Clock Input Frequency
2.5**
1.25
MHz
MHz
U
External MICROWIRE/PLUS Clock Input Frequency
MW
e
e
f
t
f /22
C
External Timer Input Frequency
Pulse Width for Timer Inputs
0.91
MHz
ns
XIN
t
C
100
XIN
t
t
t
MICROWIRE Setup TimeÐMaster
MICROWIRE Setup TimeÐSlave
100
20
UWS
UWH
UWV
ns
ns
ns
MICROWIRE Hold TimeÐMaster
MICROWIRE Hold TimeÐSlave
20
50
MICROWIRE Output Valid TimeÐMaster
MICROWIRE Output Valid TimeÐSlave
50
150
e
e
a
10
a
100
t
t
t
t
t
t
*/4 t
40
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
115
110
ns
ns
ns
ns
ns
ns
SALE
C
a
t
C
HWP
e
e
t
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
200
160
116
(Note 3)
HAE
HAD
C
*/4 t
a
85
66
C
e
a
(/2 t
(Note 5)
(Note 5)
BF
BE
C
e
a
66
(/2 t
116
C
t
t
t
t
t
t
t
t
t
t
t
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
10
10
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UAS
UAH
RPW
OE
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
60
45
70
5
(Note 6)
OD
DRDY
WDW
UDS
40
10
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
(HPC467064)
(HPC167064)
20
UDH
UDH
A
25*
WRRDY Delay from Rising Edge of UWR
70
*See NORMAL RUNNING MODE.
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
e
Note: C
40 pF.
Note 1: These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t and t ) on CKI input less than 2.5 ns.
L
CKIR
CKIL
Note 2: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
HAE
occurs later, t
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
a
a
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
C
may be as long as (3t
4 WS
e
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t 20.00 MHz,
c
72t
HAE
C
e
c
Note 4: WS
t
WAIT
with one wait state programmed.
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: Due to tester limitationsÐactual limits will be better.
3
20 MHz
AC Electrical Characteristics (Continued)
g
e
e b
a
55 C to 125 C for HPC167064 and V
e
g
5V 10%,
(See Notes 1 and 4 and Figures 1 thru 5 .) V
a
5V 5%*, T
§
§
CC
0 C to 70 C for HPC467064 (Continued)
A
CC
e
T
§
§
A
Symbol and Formula
Parameter
Min
Max
Units
Notes
t
t
t
t
t
t
t
Delay from CKI Rising Edge to ALE Rising Edge
Delay from CKI Rising Edge to ALE Falling Edge
Delay from CK2 Rising Edge to ALE Rising Edge
Delay from CK2 Falling Edge to ALE Falling Edge
ALE Pulse Width
0
0
35
35
45
45
ns
ns
ns
ns
ns
ns
ns
(Notes 1, 2)
(Notes 1, 2)
DC1ALER
DC1ALEF
e
e
a
a
(/4 t
20
20
DC2ALER
DC2ALEF
C
(/4 t
C
e
e
e
b
(/2 t
9
7
5
41
18
20
LL
ST
VP
C
b
b
(/4 t
(/4 t
Setup of Address Valid before ALE Falling Edge
Hold of Address Valid after ALE Falling Edge
C
C
e
e
b
C
t
t
t
t
t
t
t
t
t
t
t
t
(/4 t
5
ALE Falling Edge to RD Falling Edge
Data Input Valid after Address Output Valid
Data Input Valid after RD Falling Edge
RD Pulse Width
20
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ARR
ACC
a
b
WS 55
t
C
145
85
e
a
C
b
WS 65
(/2 t
RD
RW
DR
e
e
a
b
b
WS 10
(/2 t
140
0
C
*/4 t
15
Hold of Data Input Valid after RD Rising Edge
Bus Enable after RD Rising Edge
ALE Falling Edge to WR Falling Edge
WR Pulse Width
60
C
e
b
15
t
C
85
RDA
e
b
5
(/2 t
45
ARW
C
e
a
b
WS 15
*/4 t
160
145
20
WW
C
e
a
C
b
WS 5
(/2 t
Data Output Valid before WR Rising Edge
Hold of Data Valid after WR Rising Edge
Falling Edge of ALE to Falling Edge of RDY
RDY Pulse Width
V
e
b
5
(/4 t
HW
C
e
a
C
b
WS 50
(/4 t
75
DAR
RWR
e
t
C
100
4
30 MHz
AC Electrical Characteristics
(See Notes 1 and 4 and Figures 1 thru 5 ). V
CC
e
e a
0 C to 70 C for HPC467064.
g
5V 10%, T
§
§
A
Symbol and Formula
Parameter
Min
Max
Units
Notes
f
t
t
t
t
t
t
t
CKI Operating Frequency
CKI Clock Period
CKI High Time
2
33
22.5
22.5
66
66
0
30
MHz
ns
C
e
1/f
500
C1
C
ns
CKIH
CKI Low Time
ns
CKIL
e
2/f
e
CPU Timing Cycle
CPU Wait State Period
ns
C
C
t
C
ns
WAIT
Delay of CK2 Rising Edge after CKI Falling Edge
Delay of CK2 Falling Edge after CKI Falling Edge
55
55
ns
(Note 2)
(Note 2)
DC1C2R
DC1C2F
0
ns
e
f
f
f /8
C
External UART Clock Input Frequency
3.75**
1.875
MHz
MHz
U
External MICROWIRE/PLUS Clock Input Frequency
MW
e
e
f
t
f /22
C
External Timer Input Frequency
Pulse Width for Timer Inputs
1.364
MHz
ns
XIN
XIN
t
C
66
t
t
t
MICROWIRE Setup TimeÐMaster
MICROWIRE Setup TimeÐSlave
100
20
UWS
UWH
UWV
ns
ns
ns
MICROWIRE Hold TimeÐMaster
MICROWIRE Hold TimeÐSlave
20
50
MICROWIRE Output Valid TimeÐMaster
MICROWIRE Output Valid TimeÐSlave
50
150
e
e
a
10
a
85
t
t
t
t
t
t
*/4 t
40
HLD Falling Edge before ALE Rising Edge
HLD Pulse Width
90
76
ns
ns
ns
ns
ns
ns
SALE
HWP
C
a
t
C
e
e
t
HLDA Falling Edge after HLD Falling Edge
HLDA Rising Edge after HLD Rising Edge
Bus Float after HLDA Falling Edge
Bus Enable after HLDA Rising Edge
151
135
99
(Note 3)
HAE
HAD
C
*/4 t
a
85
C
e
a
66
a
66
(/2 t
(Note 5)
(Note 5)
BF
BE
C
e
(/2 t
99
C
t
t
t
t
t
t
t
t
t
t
Address Setup Time to Falling Edge of URD
Address Hold Time from Rising Edge of URD
URD Pulse Width
10
10
100
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
UAS
UAH
RPW
OE
URD Falling Edge to Output Data Valid
Rising Edge of URD to Output Data Invalid
RDRDY Delay from Rising Edge of URD
UWR Pulse Width
60
45
70
5
(Note 6)
OD
DRDY
WDW
UDS
UDH
A
40
10
20
Input Data Valid before Rising Edge of UWR
Input Data Hold after Rising Edge of UWR
WRRDY Delay from Rising Edge of UWR
70
t
t
t
t
t
t
t
Delay from CKI Rising Edge to ALE Rising Edge
Delay from CKI Rising Edge to ALE Falling Edge
20 Delay from CK2 Rising Edge to ALE Rising Edge
0
0
35
35
37
37
ns
ns
ns
ns
ns
ns
ns
(Notes 1, 2)
(Notes 1, 2)
DC1ALER
DC1ALEF
DC2ALER
DC2ALEF
e
e
a
a
(/4 t
C
(/4 t
20
Delay from CK2 Falling Edge to ALE Falling Edge
ALE Pulse Width
C
e
e
e
b
b
b
(/2 t
9
7
5
24
9
LL
ST
VP
C
(/4 t
(/4 t
Setup of Address Valid before ALE Falling Edge
Hold of Address Valid after ALE Falling Edge
C
C
11
5
30 MHz
AC Electrical Characteristics (Continued)
(See Notes 1 and 4 and Figures 1 thru 5 ). V
e
e a
0 C to 70 C for HPC467064. (Continued)
g
5V 10%, T
§
§
CC
A
Symbol and Formula
Parameter
ALE Falling Edge to RD Falling Edge
Min
Max
Units
ns
Notes
e
e
b
5
t
t
t
t
t
t
t
t
t
t
t
t
(/4 t
12
ARR
C
a
b
WS 32
t
C
Data Input Valid after Address Output Valid
Data Input Valid after RD Falling Edge
RD Pulse Width
100
60
ns
ACC
e
a
C
b
WS 39
(/2 t
ns
RD
RW
DR
e
e
a
b
b
WS 14
(/2 t
85
0
ns
C
*/4 t
15
Hold of Data Input Valid after RD Rising Edge
Bus Enable after RD Rising Edge
ALE Falling Edge to WR Falling Edge
WR Pulse Width
35
ns
C
e
b
15
t
C
51
28
101
94
7
ns
RDA
e
b
5
(/2 t
ns
ARW
C
e
a
b
WS 15
*/4 t
ns
WW
C
e
a
(/2 t
C
b
WS 5
Data Output Valid before WR Rising Edge
Hold of Data Valid after WR Rising Edge
Falling Edge of ALE to Falling Edge of RDY
RDY Pulse Width
ns
V
e
b
10
(/4 t
ns
HW
C
e
a
C
b
WS 50
(/4 t
33
ns
DAR
RWR
e
t
C
66
ns
**This maximum frequency is attainable provided that this external baud clock has a duty cycle such that the high period includes two (2) falling edges of the CK2
clock.
e
Note: C
40 pF.
Note 1: These AC Characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO with rise and fall
times (t and t ) on CKI input less than 2.5 ns.
L
CKIR
CKIL
Note 2: Do not design with this parameter unless CKI is driven with an active signal. When using a passive crystal circuit, its stability is not guaranteed if either CKI
or CKO is connected to any external logic other than the passive components of the crystal circuit.
Note 3: t
HAE
occurs later, t
is spec’d for case with HLD falling edge occurring at the latest time can be accepted during the present CPU cycle being executed. If HLD falling edge
a
a
a
100) depending on the following CPU instruction cycles, its wait states and ready input.
C
may be as long as (3t
4 WS
e
(number of pre-programmed wait states). Minimum and maximum values are calculated at maximum operating frequency, t 30.00 MHz,
c
72t
HAE
C
e
c
Note 4: WS
t
WAIT
with one wait state programmed.
Note 5: Due to emulation restrictionsÐactual limits will be better.
Note 6: Due to tester limitationsÐactual limits will be better.
CKI Input Signal Characteristics
Rise/Fall Time
TL/DD/11046–2
Duty Cycle
TL/DD/11046–3
FIGURE 1. CKI Input Signal
6
CKI Input Signal Characteristics
TL/DD/11046–4
Note: AC testing inputs are driven at V for logic ‘‘1’’ and V for a logic ‘‘0’’. Output timing measurements are made at V /2 for both logic ‘‘1’’ and logic ‘‘0’’.
CC
IH
IL
FIGURE 2. Input and Output for AC Tests
Timing Waveforms
TL/DD/11046–5
FIGURE 3. CK1, CK2, ALE Timing Diagram
TL/DD/11046–6
FIGURE 4. Write Cycle
7
Timing Waveforms (Continued)
TL/DD/11046–7
FIGURE 5. Read Cycle
TL/DD/11046–8
FIGURE 6. Ready Mode Timing
TL/DD/11046–9
FIGURE 7. Hold Mode Timing
8
Timing Waveforms (Continued)
TL/DD/11046–10
FIGURE 8. MICROWIRE Setup/Hold Timing
TL/DD/11046–11
FIGURE 9. UPI Read Timing
TL/DD/11046–12
FIGURE 10. UPI Write Timing
9
Functional Modes of Operation
There are two primary functional modes of operation for the
HPC167064.
The HPC167064 emulates the HPC16064 and HPC16083,
except as described here.
EPROM Mode
The value of EXM is latched on the rising edge of
#
#
#
RESET. Thus, the user may not switch from ROMed to
ROMless operation or vice-versa, without another
RESET pulse.
Normal Running Mode
EPROM MODE
In the EPROM mode, the HPC167064 is configured to ‘‘ap-
proximately emulate’’ a standard NMC27C256 EPROM.
The security logic can be used to control access to the
#
on-chip EPROM. This feature is unique to the
HPC167064. There is no corresponding mode of opera-
tion on the HPC16064 or the HPC16083.
Some dissimilarities do exist. The most significant one is
that HPC167064 contains only 16 kbytes of programmable
memory, rather than the 32 kbytes in 27C256. An
HPC167064 in the EPROM mode can be programmed with
a Data I/O machine.
Specific inputs are allowed to be driven at high voltage
#
(13V) to configure the device for programming. These
high voltage inputs are unique to the HPC167064. The
same inputs cannot be driven to high voltage on the
HPC16064 and HPC16083 without damage to the part.
Given below is the list of functions that can be performed by
the user in the EPROM mode.
Programming
#
The Port D input structure on this device is slightly differ-
ent from the masked ROM HPC16083 and HPC16064.
#
CAUTION: Exceeding 14V on pin 1 (V ) will damage the
PP
HPC167064.
V
min and V
IL2
max are the same as for the masked
max
IH2
ROM HPC16083 and HPC16064. There is a V
IH2
Initially, and after each erasure, all bits of the HPC
EPROM are in the ‘‘1’’ state. Data is introduced by selec-
tively programming ‘‘0s’’ into the desired bit locations.
Although only ‘‘0s’’ will be programmed, both ‘‘1s’’ and
‘‘0s’’ can be presented in the data word. The only way to
change a ‘‘0’’ to a ‘‘1’’ is by ultraviolet light erasure.
a
requirement for this device equal to V
is also a V
0.05V. There
min requirement for this device equal to
CC
IL2
GND-0.05V. The V
max and V
min requirement for
IH2 IL2
the masked ROM devices is the Absolute Maximum Rat-
a
ings of V
0.5V and GND-0.5V respectively.
CC
The D.C. Electrical Characteristics and A.C. Electrical
e b
125 C, are guaranteed over a reduced operating
#
#
Program/verify EPROM registers
#
#
Characteristics for the HPC167064, where T
a
voltage range of V
55 C
§
A
To read data (verify) during the programming process,
must be at 13V. When reading data after the pro-
to
§
V
PP
g
masked ROM devices that it simulates which is V
5%. This is different from the
CC
gramming process, V can be either 13V or at V
PP
.
CC
CC
10%. These characteristics for the HPC467064, where
Program/verify ECON registers
g
e b
a
0 C to 70 C, are guaranteed over the masked
There are two configuration registers ECON6 and
ECON7 to emulate different family members and also to
enable/disable different features in the chip. These reg-
isters are not mapped in the EPROM user space. These
bytes must be programmed through a pointer register
ECONA.
T
A
§
§
g
ROM operating voltage range which is V
10%.
In addition to the reduced operating voltage range for the
HPC167064, the A.C. timing parameter t is required
CC
UDH
to be a mimimum value of 25 ns. The masked ROM de-
vices require a mimimum t 0f 20 ns. This A.C. timing
UDH
To prevent unintentional programming, the ECON6, 7
registers must be programmed with the assistance of this
pointer register. ECONA, and externally presented ad-
dress, both identify the same ECON register may be pro-
grammed.
parameter for the HPC467064 is required to be the same
as the masked ROM devices.
HPC167064 EPROM SECURITY
The HPC167064 includes security logic to provide READ
and WRITE protection of the on-chip EPROM. These de-
fined privileges are intended to deter theft, alteration, or un-
intentional destruction of user code. Two bits are used to
define four levels of security on the HPC167064 to control
access to on-chip EPROM.
NORMAL RUNNING MODE
In this mode, the HPC167064 executes user software in the
normal manner. By default, its arcitecture imitates that of
the HPC16064. It may be configured to emulate the
HPC16083. The addressable memory map will be exactly as
for the HPC16083. The WATCHDOG function monitors ad-
dresses accordingly. Thus, the HPC167064 can be used as
a stand-alone emulator for both HPC16064 and HPC16083.
Security Level 3
This is the default configuration of an erased HPC167064.
READ and WRITE accesses to the on-chip EPROM or
ECON registers may be accomplished without constraint in
EPROM mode. READ accesses to the on-chip EPROM may
be accomplished without constraint in NORMAL RUNNING
mode.
Within this mode, the on-chip EPROM cell acts as read only
memory. Each memory fetch is 16-bits wide. The
HPC167064 operates to 20 MHz with 1 wait state for the on-
chip memory.
10
Functional Modes of Operation (Continued)
Security Level 2
An erasure system should be calibrated periodically. The
distance from lamp to unit should be maintained at one inch.
The erasure time increases as the square of the distance. (If
distance is doubled the erasure time increases by a factor of
4.) Lamps lose intensity as they age. When a lamp is
changed, the distance has changed or the lamp has aged,
the system should be checked to make certain full erasure
is occurring.
This security level prevents programming of the on-chip
EPROM or the ECON registers thereby providing WRITE
protection. Read accesses to the on-chip EPROM or ECON
registers may be accomplished without constraint in
EPROM. Read accesses to the on-chip EPROM may be
accomplished without constraint in NORMAL RUNNING
mode.
Incomplete erasure will cause symptoms that can be mis-
leading. Programmers, components, and even system de-
signs have been erroneously suspected when incomplete
erasure was the problem.
Security Level 1
This security level prevents programming of the on-chip
EPROM or ECON registersÐthereby providing registers
write protection. Read accesses to the on-chip ECON-regis-
ters may be accomplished without constraint in EPROM
mode. Read accesses to the on-chip EPROM will produce
ENCRYPTED data in EPROM. READ accesses to the on-
chip EPROM, during NORMAL RUNNING mode, are sub-
ject to Runtime Memory Protection. Under Runtime Mem-
ory Protection, only instruction opcodes stored within the
on-chip EPROM are allowed to access the EPROM as oper-
and. If any other instruction opcode attempts to use the
contents of EPROM as an operand, it will receive the hex
value ‘‘FF’’. The Runtime Memory Protection feature is de-
signed to prevent hostile software, running from external
memory or on-chip RAM, from reading secured EPROM
data. Transfers of control into, or out of the on-chip EPROM
(such as jump or branch) are not affected by Runtime Mem-
ory Protection. Interrupt vector fetches from EPROM pro-
ceed normally, and are not affected by Runtime Memory
Protection.
Minimum HPC167064 Erasure Time
Light Intensity
(Micro-Watts/cm )
Erasure Time
(Minutes)
2
15,000
36
50
10,000
Memory Map of the HPC167064
The HPC167064 has 256 bytes of on-chip user RAM and
chip registers located at address 0000–01FF that is always
enabled, and 256 bytes of on-chip RAM located at 0200–
02FF that can be enabled or disabled. It has 8 kbytes of on-
chip EPROM located at address 0E000–0FFFF that is al-
ways enabled and 8 kbytes of EPROM located at address
0C000–0DFFF that can be enabled or disabled.
The ECON6 contains two bits ROM0 and RAM0. When
these bits are ‘‘1’’ (erased default), full 16 kbytes of ROM
and 512 bytes of RAM are enabled. Programming a ‘‘0’’ to
these bits disables the lower 8k for the EPROM and upper
256 bytes for the RAM. The ECON registers are only acces-
sible to the user during EPROM mode.
Security Level 0
This security level prevents programming of the on-chip
EPROM or ECON registers, thereby providing write protec-
tion. Read accesses to the on-chip ECON registers may be
accomplished without constraint in EPROM mode. READ
accesses to the on-chip EPROM are NOT ALLOWED in
EPROM mode. Such accesses will return data value ‘‘FF’’
hex. Runtime Memory Protection is enforced as in security
level 1.
Address In
Address In Other
HPC Modes
EPROM Mode
7FFF
Operation
These four levels of security help ensure that the user
EPROM code is not tampered with in a test fixture and that
code executing from RAM or external memory does not
dump the user algorithm.
Erasure Characteristics
4000
3FFF
FFFF
The erasure characteristics of the HPC167064 are such that
erasure begins to occur when exposed to light with wave-
lengths shorter than approximately 4000 Angstroms (Ð). It
should be noted that sunlight and certain types of fluores-
cent lamps have wavelengths in the 3000Ж4000Рrange.
After programming, opaque labels should be placed over
the HPC167064’s window to prevent unintentional erasure.
Covering the window will also prevent temporary functional
failure due to the generation of photo currents.
2000
1FFF
E000
DFFF
The recommended erasure procedure for the HPC167064 is
exposure to short wave ultraviolet light which has a wave-
length of 2537 Angstroms (Ð). The integrated dose (i.e., UV
Enabled or
Disabled by
config logic
c
intensity exposure time) for erasure should be a minimum
2
of 30W-sec/cm .
The HPC167064 should be placed within 1 inch of the lamp
tubes during erasure. Some lamps have a filter on their
tubes which should be removed before erasure. The era-
sure time table shows the minimum HPC167064 erasure
time for various light intensities.
0000
C000
–
11
Pin Descriptions
The HPC167064 is available only in 68-pin LDCC package.
POWER SUPPLY PINS
V
V
and
CC1
CC2
I/O PORTS
Positive Power Supply
Port A is a 16-bit bidirectional I/O port with a data direction
register to enable each separate pin to be individually de-
fined as an input or output. When accessing external memo-
ry, port A is used as the multiplexed address/data bus.
GND
DGND
Ground for On-Chip Logic
Ground for Output Buffers
Note: There are two electrically connected V
DGND are electrically isolated. Both V
must be used.
pins on the chip, GND and
pins and both ground pins
CC
CC
Port B is a 16-bit port with 12 bits of bidirectional I/O similar
in structure to Port A. Pins B10, B11, B12 and B15 are gen-
eral purpose outputs only in this mode. Port B may also be
configured via a 16-bit function register BFUN to individually
allow each pin to have an alternate function.
CLOCK PINS
CKI
The Chip System Clock Input
The Chip System Clock Output (inversion of CKI)
CKO
B0: TDX
B1:
UART Data Output
Pins CKI and CKO are usually connected across an external
crystal.
B2: CKX
B3: T2IO
B4: T3IO
B5: SO
B6: SK
B7: HLDA
B8: TS0
B9: TS1
B10: UA0
UART Clock (Input or Output)
Timer2 I/O Pin
CK2
Clock Output (CKI divided by 2)
OTHER PINS
Timer3 I/O Pin
WO
This is an active low open drain output that sig-
nals an illegal situation has been detected by the
WATCHDOG logic.
MICROWIRE/PLUS Output
MICROWIRE/PLUS Clock (Input or Output)
Hold Acknowledge Output
Timer Synchronous Output
Timer Synchronous Output
Address 0 Input for UPI Mode
ST1
Bus Cycle Status Output: indicates first opcode
fetch.
ST2
Bus Cycle Status Output: indicates machine
states (skip, interrupt and first instruction cycle).
B11: WRRDY Write Ready Output for UPI Mode
B12:
RESET
is an active low input that forces the chip to re-
start and sets the ports in a TRI-STATE mode.
B13: TS2
B14: TS3
Timer Synchronous Output
Timer Synchronous Output
RDY/HLD has two uses, selected by a software bit. It’s ei-
ther an input to extend the bus cycle for slower
memories, or a HOLD request input to put the
bus in a high impedance state for DMA purpos-
es.
B15: RDRDY Read Ready Output for UPI Mode
When accessing external memory, four bits of port B are
used as follows:
NC
(no connection) do not connect anything to this
pin.
B10: ALE
B11: WR
B12: HBE
Address Latch Enable Output
Write Output
EXM
Has two uses. External memory enable (active
high) which disables internal EPROM and maps
High Byte Enable Output/Input
(sampled at reset)
it to external memory, and is V during EPROM
PP
mode.
B15: RD
Read Output
Port I is an 8-bit input port that can be read as general
purpose inputs and is also used for the following functions:
EI
External
interrupt
with
vector
address
FFF1:FFF0. (Rising/falling edge or high/low lev-
el sensitive). Alternately can be configured as
4th input capture.
I0:
I1:
I2:
I3:
I4:
I5:
I6:
I7:
NMI
INT2
INT3
INT4
SI
Nonmaskable Interrupt Input
EXUI
External interrupt which is internally OR’ed with
the UART interrupt with vector address
FFF3:FFF2 (Active Low).
Maskable Interrupt/Input Capture/URD
Maskable Interrupt/Input Capture/UWR
Maskable Interrupt/Input Capture
MICROWIRE/PLUS Data Input
UART Data Input
RDX
Port D is an 8-bit input port that can be used as general
purpose digital inputs.
Port P is a 4-bit output port that can be used as general
purpose data, or selected to be controlled by timers 4
through 7 in order to generate frequency, duty cycle and
pulse width modulated outputs.
12
Connection Diagram
TL/DD/11046–17
Top View
Order Number HPC167064, EL
See NS Package Number EL68C
Ports A & B
The highly flexible A and B ports are similarly structured.
The Port A (see Figure 11), consists of a data register and a
direction register. Port B (see Figures 12 thru Figure 14) has
an alternate function register in addition to the data and
direction registers. All the control registers are read/write
registers.
A write operation to a port pin configured as an input causes
the value to be written into the data register, a read opera-
tion returns the value of the pin. Writing to port pins config-
ured as outputs causes the pins to have the same value,
reading the pins returns the value of the data register.
Primary and secondary functions are multiplexed onto Port
B through the alternate function register (BFUN). The sec-
ondary functions are enabled by setting the corresponding
bits in the BFUN register.
The associated direction registers allow the port pins to be
individually programmed as inputs or outputs. Port pins se-
lected as inputs are placed in a TRI-STATE mode by reset-
ting corresponding bits in the direction register.
TL/DD/11046–19
FIGURE 11. Port A: I/O Structure
13
Ports A & B (Continued)
TL/DD/11046–20
FIGURE 12. Structure of Port B Pins B0, B1, B2, B5, B6 and B7 (Typical Pins)
TL/DD/11046–21
FIGURE 13. Structure of Port B Pins B3, B4, B8, B9, B13 and B14 (Timer Synchronous Pins)
14
Ports A & B (Continued)
TL/DD/11046–22
FIGURE 14. Structure of Port B Pins B10, B11, B12 and B15 (Pins with Bus Control Roles)
Operating Modes
To offer the user a variety of I/O and expanded memory
options, the HPC167064 has four operating modes. The
various modes of operation are determined by the state of
both the EXM pin and the EA bit in the PSW register. The
state of the EXM pin determines whether on-chip EPROM
will be accessed or external memory will be accessed within
the address range of the on-chip EPROM. The on-chip
EPROM range of the HPC167064 is C000 to FFFF
(16 kbytes).
DOG logic is engaged. A logic ‘‘1’’ in the EA bit enables
accesses to be made anywhere within the 64 kbytes ad-
dress range and the ‘‘illegal address detection’’ feature of
the WATCHDOG logic is disabled.
All HPC devices can be used with external memory. Exter-
nal memory may be any combination of RAM and EPROM.
Both 8-bit and 16-bit external data bus modes are available.
Upon entering an operating mode in which external memory
is used, Port A becomes the Address/Data bus. Four pins of
Port B become the control lines ALE, RD, WR and HBE.
The High Byte Enable pin (HBE) is used in 16-bit mode to
select high order memory bytes. The RD and WR signals
are only generated if the selected address is off-chip. The 8-
bit mode is selected by pulling HBE high at reset. If HBE is
left floating or connected to a memory device chip select at
reset, the 16-bit mode is entered. The following sections
describe the operating modes of the HPC167064.
A logic ‘‘0’’ state on the EXM pin will cause the HPC device
to address on-chip EPROM when the Program Counter (PC)
contains addresses within the on-chip EPROM address
range. A logic ‘‘1’’ state on the EXM pin will cause the HPC
device to address memory that is external to the HPC when
the PC contains on-chip EPROM addresses. The function of
the EA bit is to determine the legal addressing range of the
HPC device. A logic ‘‘0’’ state in the EA bit of the PSW
register does two thingsÐaddresses are limited to the on-
chip EPROM range and on-chip RAM and Register range,
and the ‘‘illegal address detection’’ feature of the WATCH-
Note: The HPC devices use 16-bit words for stack memory. Therefore,
when using the 8-bit mode, User’s Stack must be in internal RAM.
15
HPC167064 Operating Modes
SINGLE CHIP NORMAL MODE
In this mode, the HPC167064 functions as a self-contained
microcomputer (see Figure 15 ) with all memory (RAM and
EPROM) on-chip. It can address internal memory only, con-
sisting of 16 kbytes of EPROM (C000 to FFFF) and
512 bytes of on-chip RAM and Registers (0000 to 02FF).
The ‘‘illegal address detection’’ feature of the WATCHDOG
is enabled in the Single-Chip Normal mode and a WATCH-
DOG Output (WO) will occur if an attempt is made to access
addresses that are outside of the on-chip EPROM and RAM
range of the device. Ports A and B are used for I/O func-
tions and not for addressing external memory. The EXM pin
and the EA bit of the PSW register must both be logic ‘‘0’’ to
enter the Single-Chip Normal mode.
EXPANDED NORMAL MODE
TL/DD/11046–23
FIGURE 15. Single-Chip Mode
The Expanded Normal mode of operation enables the
HPC167064 to address external memory in addition to the
on-chip ROM and RAM (see Table I). WATCHDOG illegal
address detection is disabled and memory accesses may
be made anywhere in the 64 kbyte address range without
triggering an illegal address condition. The Expanded Nor-
mal mode is entered with the EXM pin pulled low (logic ‘‘0’’)
and setting the EA bit in the PSW register to ‘‘1’’.
Power Save Modes
Two power saving modes are available on the HPC167064:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer T0 are active but all other processor activities are
stopped. In either mode, all on-board RAM, registers and
I/O are unaffected.
TABLE I. HPC167064 Operating Modes
HALT MODE
EXM EA
Pin Bit
Memory
Operating Mode
The HPC167064 is placed in the HALT mode under soft-
ware control by setting bits in the PSW. All processor activi-
ties, including the clock and timers, are stopped. In the
HALT mode, power requirements for the HPC167064 are
Configuration
Single-Chip Normal
Expanded Normal
0
0
0
1
C000–FFFF On-Chip
C000–FFFF On-Chip
0300–BFFF Off-Chip
minimal and the applied voltage (V ) may be decreased
CC
without altering the state of the machine. There are two
ways of exiting the HALT mode: via the RESET or the NMI.
The RESET input reinitializes the processor. Use of the NMI
input will generate a vectored interrupt and resume opera-
tion from that point with no initialization. The HALT mode
can be enabled or disabled by means of a control register
HALT enable. To prevent accidental use of the HALT mode
the HALT enable register can be modified only once.
Single-Chip ROMless
Expanded ROMless
1
1
0
1
C000–FFFF Off-Chip
0300–FFFF Off-Chip
SINGLE-CHIP ROMless MODE
In this mode, the on-chip EPROM of the HPC167064 is not
used. The address space corresponding to the on-chip
EPROM is mapped into external memory so 16k of external
memory may be used with the HPC167064 (see Table I).
The WATCHDOG circuitry detects illegal addresses (ad-
dresses not within the on-chip EPROM and RAM range).
The Single-Chip ROMless mode is entered when the EXM
pin is pulled high (logic ‘‘1’’) and the EA bit is logic ‘‘0’’.
IDLE MODE
The HPC167064 is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the on-
board oscillator and Timer T0, is stopped. As with the HALT
mode, the processor is returned to full operation by the
RESET or NMI inputs, but without waiting for oscillator stabi-
lization. A timer T0 overflow will also cause the HPC167064
to resume normal operation.
EXPANDED ROM MODE
This mode of operation is similar to Single-Chip ROMless
mode in that no on-chip ROM is used, however, a full
64 kbytes of external memory may be used. The ‘‘illegal
address detection’’ feature of WATCHDOG is disabled. The
EXM pin must be pulled high (logic ‘‘1’’) and the EA bit in the
PSW register set to ‘‘1’’ to enter this mode.
Note: If an NMI interrupt is received during the instruction which puts the
device in Halt or Idle Mode, the device will enter that power saving
mode. The interrupt will be held pending until the device exits that
power saving mode. When exiting Idle mode via the T0 overflow, the
NMI interrupt will be serviced when the device exits Idle. If another
NMI interrupt is received during either Halt of Idle the processor will
exit the power saving mode and vector to the interrupt address.
Wait States
The internal EPROM can be accessed at the maximum op-
HPC167064 Interrupts
Complex interrupt handling is easily accomplished by the
HPC167064’s vectored interrupt scheme. There are eight
possible interrupt sources as shown in Table II.
erating frequency with one wait state. With 0 wait states,
max. The
internal ROM accesses are limited to )/3
f
C
HPC167064 provides four software selectable Wait States
that allow access to slower memories. The Wait States are
selected by the state of two bits in the PSW register. Addi-
tionally, the RDY input may be used to extend the instruc-
tion cycle, allowing the user to interface with slow memories
and peripherals.
16
HPC167064 Interrupts (Continued)
TL/DD/11046–24
FIGURE 16. 8-Bit External Memory
TL/DD/11046–25
FIGURE 17. 16-Bit External Memory
17
HPC167064 Interrupts (Continued)
TABLE II. Interrupts
Interrupt Source
Vector
Arbitration
Ranking
Address
FFFF:FFFE
FFFD:FFFC
FFFB:FFFA
FFF9:FFF8
FFF7:FFF6
FFF5:FFF4
FFF3:FFF2
FFF1:FFF0
RESET
0
1
2
3
4
5
6
7
Nonmaskable external on rising edge of I1 pin
External interrupt on I2 pin
External interrupt on I3 pin
External interrupt on I4 pin
Overflow on internal timers
Internal on the UART transmit/receive complete or external on EXUI
External interrupt on EI pin
For the interrupts from the on-board peripherals, the user
has the responsibility of resetting the interrupt pending flags
through software.
Interrupt Arbitration
The HPC167064 contains arbitration logic to determine
which interrupt will be serviced first if two or more interrupts
occur simultaneously. The arbitration ranking is given in Ta-
ble II. The interrupt on RESET has the highest rank and is
serviced first.
The NMI bit is read only and I2, I3, and I4 are designed as to
only allow a zero to be written to the pending bit (writing a
one has no affect). A LOAD IMMEDIATE instruction is to be
the only instruction used to clear a bit or bits in the IRPD
register. This allows a mask to be used, thus ensuring that
the other pending bits are not affected.
Interrupt Processing
Interrupts are serviced after the current instruction is com-
pleted except for the RESET, which is serviced immediately.
RESET and EXUI are level-LOW-sensitive interrupts and EI
is programmable for edge-(RISING or FALLING) or level-
(HIGH or LOW) sensitivity. All other interrupts are edge-sen-
sitive. NMI is positive-edge sensitive. The external interrupts
on I2, I3 and I4 can be software selected to be rising or
falling edge. External interrupt (EXUI) is shared with UART
interrupt. This interrupt is level-low sensitive. To select this
interrupt disable the ERI and ETI UART interrupt bits in the
ENUI register. To select the UART interrupt leave this pin
floating or tie it high.
INTERRUPT CONDITION REGISTER (IRCD)
Three bits of the register select the input polarity of the
external interrupt on I2, I3, and I4.
Servicing the Interrupts
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice. The Global Interrupt Enable bit (GIE) is
copied into the CGIE bit of the PSW register; it is then reset,
thus disabling further interrupts. The program counter is
loaded with the contents of the memory at the vector ad-
dress and the processor resumes operation at this point. At
the end of the interrupt service routine, the user does a
RETI instruction to pop the stack and re-enable interrupts if
the CGIE bit is set, or RET to just pop the stack if the CGIE
bit is clear, and then returns to the main program. The GIE
bit can be set in the interrupt service routine to nest inter-
rupts if desired. Figure 18 shows the Interrupt Enable Logic.
Interrupt Control Registers
The HPC167064 allows the various interrupt sources and
conditions to be programmed. This is done through the vari-
ous control registers. A brief description of the different con-
trol registers is given below.
INTERRUPT ENABLE REGISTER (ENIR)
RESET and the External Interrupt on I1 are non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENIR Register allows the Maskable interrupts to be collec-
tively enabled or disabled. Thus, in order for a particular
interrupt to request service, both the individual enable bit
and the Global Interrupt bit (GIE) have to be set.
RESET
The RESET input initializes the processor and sets Ports A
and B in the TRI-STATE condition and Port P in the LOW
state. RESET is an active-low Schmitt trigger input. The
processor vectors to FFFF:FFFE and resumes operation at
the address contained at that memory location (which must
correspond to an on board location). The Reset vector ad-
dress must be between C000 and FFFF when emulating the
HPC16064 and between E000 and FFFF when emulating
the HPC16003.
INTERRUPT PENDING REGISTER (IRPD)
The IRPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger condi-
tions causes the appropriate bit to be set. There is no indi-
cation of the order in which the interrupts have been re-
ceived. The bits are set independently of the fact that the
interrupts may be disabled. IRPD is a Read/Write register.
The bits corresponding to the maskable, external interrupts
are normally cleared by the HPC167064 after servicing the
interrupts.
Timer Overview
The HPC167064 contains a powerful set of flexible timers
enabling the HPC167064 to perform extensive timer func-
tions not usually associated with microcontrollers. The
HPC167064 contains nine 16-bit timers. Timer T0 is a
free-running timer, counting up at a fixed CKI/16
18
19
Timer Overview (Continued)
(Clock Input/16) rate. It is used for WATCHDOG logic, high
speed event capture, and to exit from the IDLE mode. Con-
sequently, it cannot be stopped or written to under software
control. Timer T0 permits precise measurements by means
of the capture registers I2CR, I3CR, and I4CR. A control bit
in the register TMMODE configures timer T1 and its associ-
ated register R1 as capture registers I3CR and I2CR. The
capture registers I2CR, I3CR, and I4CR respectively, record
the value of timer T0 when specific events occur on the
interrupt pins I2, I3, and I4. The control register IRCD pro-
grams the capture registers to trigger on either a rising edge
or a falling edge of its respective input. The specified edge
can also be programmed to generate an interrupt (see Fig-
ure 19 ).
dividing the clock input. Timer T2 has additional capability of
being clocked by the timer T3 underflow. This allows the
user to cascade timers T3 and T2 into a 32-bit timer/coun-
ter. The control register DIVBY programs the clock input to
timers T2 and T3 (see Figure 20 ).
The timers T1 through T7 in conjunction with their registers
form Timer-Register pairs. The registers hold the pulse du-
ration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC167064 simplifies
pulse generation and measurement. There are four syn-
chronous timer outputs (TS0 through TS3) that work in con-
junction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (see Figure 20 ).
The HPC167064 provides an additional 16-bit free running
timer, T8, with associated input capture register EICR (Ex-
ternal Interrupt Capture Register) and Configuration Regis-
ter, EICON. EICON is used to select the mode and edge of
the EI pin. EICR is a 16-bit capture register which records
the value of T8 (which is identical to T0) when a specific
event occurs on the EI pin.
Timer/register pairs 4–7 form four identical units which can
generate synchronous outputs on Port P (see Figure 21 ).
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally by
TL/DD/11046–28
TL/DD/11046–27
FIGURE 20. Timers T2–T3 Block
FIGURE 19. Timers T0, T1 and T8
with Four Input Capture Registers
20
Timer Overview (Continued)
Maximum output frequency for any timer output can be ob-
tained by setting timer/register pair to zero. This then will
produce an output frequency equal to (/2 the frequency of
the source used for clocking the timer.
Timer Registers
There are four control registers that program the timers. The
divide by (DIVBY) register programs the clock input to tim-
ers T2 and T3. The timer mode register (TMMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch, acknowledge and enable interrupts
from timers T0 through T3. The control register PWMODE
similarly programs the pulse width timers T4 through T7 by
allowing them to be started, stopped, and to latch and en-
able interrupts on underflows. The PORTP register contains
bits to preset the outputs and enable the synchronous timer
output functions.
TL/DD/11046–30
FIGURE 23. Synchronous Pulse Generation
The illegal conditions that trigger the WATCHDOG logic are
potentially infinite loops and illegal addresses. Should the
WATCHDOG register not be written to before Timer T0
overflows twice, or more often than once every 4096
counts, an infinite loop condition is assumed to have oc-
curred. An illegal condition also occurs when the processor
generates an illegal address when in the Single-Chip
modes.* Any illegal condition forces the WATCHDOG Out-
put (WO) pin low. The WO pin is an open drain output and
can be connected to the RESET or NMI inputs or to the
users external logic.
*Note: See Operating Modes for details.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure 24 ). MICROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and SO as the output. SK is the clock for the serial
shift register (SIO). The SK clock signal can be provided by
an internal or external source. The internal clock rate is pro-
grammable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
TL/DD/11046–29
FIGURE 21. Timers T4–T7 Block
Timer Applications
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC167064.
The MICROWIRE/PLUS capability enables it to interface
with any of National Semiconductor’s MICROWIRE periph-
erals (i.e., A/D converters, display drivers, EEPROMs).
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
MICROWIRE/PLUS Operation
The HPC167064 can enter the MICROWIRE/PLUS mode
as the master or a slave. A control bit in the IRCD register
determines whether the HPC167064 is the master or slave.
The shift clock is generated when the HPC167064 is config-
ured as a master. An externally generated shift clock on the
SK pin is used when the HPC167064 is configured as a
slave. When the HPC167064 is a master, the DIVBY regis-
ter programs the frequency of the SK clock. The DIVBY
register allows the SK clock frequency to be programmed in
15 selectable steps from 64 Hz to 1 MHz with CKI at
16.0 MHz.
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TS0–TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 con-
tains the time delay between events. Figure 23 is an exam-
ple of synchronous pulse train generation.
TL/DD/11046–31
FIGURE 22. Square Wave Frequency Generation
The contents of the SIO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the SIO register is clocked out on the falling
edge of the SK clock. Serial data on the SI pin is clocked in
on the rising edge of the SK clock.
WATCHDOG Logic
The WATCHDOG Logic monitors the operations taking
place and signals upon the occurrence of any illegal activity.
21
MICROWIRE/PLUS Application
Figure 25 illustrates a MICROWIRE/PLUS arrangement for
an automotive application. The microcontroller-based sys-
tem could be used to interface to an instrument cluster and
various parts of the automobile. The diagram shows two
HPC167064 microcontrollers interconnected to other
MICROWIRE peripherals. HPC167064 1 is set up as the
master and initiates all data transfers. HPC167064 2 is set
up as a slave answering to the master.
The master microcontroller interfaces the operator with the
system and could also manage the instrument cluster in an
automotive application. Information is visually presented to
the operator by means of a LCD display controlled by the
COP472 display driver. The data to be displayed is sent
serially to the COP472 over the MICROWIRE/PLUS link.
Data such as accumulated mileage could be stored and re-
trieved from the EEPROM COP494. The slave HPC167064
could be used as a fuel injection processor and generate
timing signals required to operate the fuel valves. The mas-
ter processor could be used to periodically send updated
values to the slave via the MICROWIRE/PLUS link. To
speed up the response, chip select logic is implemented by
connecting an output from the master to the external inter-
rupt input on the slave.
TL/DD/11046–32
FIGURE 24. MICROWIRE/PLUS
TL/DD/11046–33
FIGURE 25. MICROWIRE/PLUS Application
22
HPC167064 UART
The HPC167064 contains a software programmable UART.
The UART (see Figure 26 ) consists of a transmit shift regis-
ter, a receiver shift register and five addressable registers,
as follows: a transmit buffer register (TBUF), a receiver buff-
er register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive func-
tions; this register also determines the length of the data
frame (8 or 9 bits) and the value of the ninth bit in transmis-
sion. The ENUR register flags framing and data overrun er-
rors while the UART is receiving. Other functions of the
ENUR register include saving the ninth bit received in the
data frame and enabling or disabling the UART’s Attention
Mode of operation. The determination of an internal or ex-
ternal clock source is done by the ENUI register, as well as
selecting the number of stop bits and enabling or disabling
transmit and receive interrupts.
The baud rate clock for the Receiver and Transmitter can
be selected for either an internal or external source using
two bits in the ENUI register. The internal baud rate is pro-
grammed by the DIVBY register. The baud rate may be se-
lected from a range of 8 Hz to 128 kHz in binary steps or T3
underflow. By selecting a 9.83 MHz crystal, all standard
baud rates from 75 baud to 38.4 kBaud can be generated.
The external baud clock source comes from the CKX pin.
The Transmitter and Receiver can be run at different rates
by selecting one to operate from the internal clock and the
other from an external source.
The HPC167064 UART supports two data formats. The first
format for data transmission consists of one start bit, eight
data bits and one or two stop bits. The second data format
for transmission consists of one start bit, nine data bits, and
one or two stop bits. Receiving formats differ from transmis-
sion only in that the Receiver always requires only one stop
bit in a data frame.
UART Wake-Up Mode
The HPC167064 UART features a Wake-Up Mode of opera-
tion. This mode of operation enables the HPC167064 to be
networked with other processors. Typically in such environ-
ments, the messages consist of addresses and actual data.
Addresses are specified by having the ninth bit in the data
frame set to 1. Data in the message is specified by having
the ninth bit in the data frame reset to 0.
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC167064 with an inter-
rupt. The processor then examines the content of the re-
ceiver buffer to decide whether it has been addressed and
whether to accept subsequent data.
TL/DD/11046–34
FIGURE 26. UART Block Diagram
23
The host uses DMA to interface with the HPC167064. The
host initiates a data transfer by activating the HLD input of
the HPC167064. In response, the HPC167064 places its
system bus in a TRI-STATE Mode, freeing it for use by the
host. The host waits for the acknowledge signal (HLDA)
from the HPC167064 indicating that the sytem bus is free.
On receiving the acknowledge, the host can rapidly transfer
data into, or out of, the shared memory by using a conven-
tional DMA controller. Upon completion of the message
transfer, the host removes the HOLD request and the
HPC167064 resumes normal operations.
Universal Peripheral Interface
The Universal Peripheral Interface (UPI) allows the
HPC167064 to be used as an intelligent peripheral to anoth-
er processor. The UPI could thus be used to tightly link two
HPC167064’s and set up systems with very high data ex-
change rates. Another area of application could be where a
HPC167064 is programmed as an intelligent peripheral to a
host system such as the Series 32000 microprocessor.
É
Figure 27 illustrates how a HPC167064 could be used as an
intelligent peripheral for a Series 32000-based application.
The interface consists of a Data Bus (port A), a Read Strobe
(URD), a Write Strobe (UWR), a Read Ready Line (RDRDY),
a Write Ready Line (WRRDY) and one Address Input (UA0).
The data bus can be either eight or sixteen bits wide.
To insure proper operation, the interface logic shown is rec-
ommended as the means for enabling and disabling the us-
er’s bus. Figure 28 illustrates an application of the shared
memory interface between the HPC167064 and a Series
32000 system.
The URD and UWR inputs may be used to interrupt the
HPC167064. The RDRDY and WRRDY outputs may be
used to interrupt the host processor.
Memory
The UPI contains an Input Buffer (IBUF), an Output Buffer
(OBUF) and a Control Register (UPIC). In the UPI mode,
Port A on the HPC167064 is the data bus. UPI can only be
used if the HPC167064 is in the Single-Chip mode.
The HPC167064 has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 8 kbytes of EPROM and 512 bytes of RAM
available on the chip itself. The EPROM may contain pro-
gram instructions, constants or data. The EPROM and RAM
share the same address space allowing instructions to be
executed out of RAM.
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. It is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPC167064
supports shared memory access with two pins. The pins are
the RDY/HLD input pin and the HLDA output pin. The user
can software select either the Hold or Ready function by the
state of a control bit. The HLDA output is multiplexed onto
Port B.
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always addressed on even-byte boundaries. The
HPC167064 uses memory-mapped organization to support
registers, I/O and on-chip peripheral functions.
The HPC167064 memory address space extends to
64 kbytes and registers and I/O are mapped as shown in
Table III and Table IV.
TL/DD/11046–35
FIGURE 27. HPC167064 as a Peripheral (UPI Interface to Series 32000 Application)
24
Shared Memory Support (Continued)
TL/DD/11046–36
FIGURE 28. Shared Memory Application (HPC167064 Interface to Series 32000 System)
Design Considerations
TABLE III. Memory Map of HPC167064 Emulating an HPC16064
FFFF:FFF0 Interrupt Vectors
FFEF:FFD0 JSRP Vectors
FFCF:FFCE
0128
0126
0124
0122
0120
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
UART
:
:
On-Chip ROM
User Memory
C001:C000
BFFF:BFFE
: :
0301:0300
(
(
(
0104
Port D Input Register
External Expansion
Memory
00F5:00F4
00F3:00F2
00F1:00F0
BFUN Register
DIR B Register
DIR A Register/IBUF
Ports A & B
Control
02FF:02FE
:
01C1:01C0
:
On-Chip RAM
User RAM
00E6
UPIC Register
UPI Control
Ports A & B
00E3:00E2
00E1:00E0
Port B
Port A/OBUF
0195:0194 WATCHDOG Register WATCHDOG Logic
0192
T0CON Register
00DE
Reserved
0191:0190 TMMODE Register
018F:018
018D:018C T3 Timer
018B:018A R3 Register
0189:0188 T2 Timer
0187:0186 R2 Register
0185:0184 I2CR Register/ R1
0183:0182 I3CR Register/ T1
0181:0180 I4CR Register
00DD:00DC
00D8
00D6
00D4
00D2
00D0
HALT Enable Register
Port I Input Register
SIO Register
IRCD Register
IRPD Register
ENIR Register
DIVBY Register
Port Control
& Interrupt
Control
Timer Block T0:T3
Registers
00CF:00CE
00CD:00CC
00CB:00CA
00C9:00C8
00C7:00C6
00C5:00C4
00C3:00C2
00C0
X Register
B Register
K Register
A Register
PC Register
SP Register
Reserved
015E:015F EICR
015C
HPC Core
Registers
EICON
0153:0152 Port P Register
0151:0150 PWMODE Register
014F:014E R7 Register
014D:014C T7 Timer
PSW Register
014B:014A R6 Register
0149:0148 T6 Timer
0147:0146 R5 Register
0145:0144 T5 Timer
Timer Block T4:T7
00BF:00BE
: :
0001:0000
On-Chip
RAM
User RAM
0143:0142 R4 Register
0141:0140 T4 Timer
25
Design Considerations (Continued)
TABLE IV. Memory Map of HPC167064 Emulating an HPC16083
FFFF:FFF0 Interrupt Vectors
FFEF:FFD0 JSRP Vectors
FFCF:FFCE
0128
0126
0124
0122
0120
ENUR Register
TBUF Register
RBUF Register
ENUI Register
ENU Register
UART
:
:
E001:E000
On-Chip EPROM
(
User Memory
0104
Port D Input Register
DFFF:DFFE
: :
0201:0200
External Expansion
Memory
00F5:00F4
00F3:00F2
00F1:00F0
BFUN Register
DIR B Register
DIR A Register /IBUF
Ports A & B
Control
(
(
01FF:01FE
:
01C1:01C0
00E6
UPIC Register
UPI Control
Ports A & B
:
On-Chip RAM
User RAM
00E3:00E2
00E1:00E0
Port B
Port A/OBUF
0195:0194
WATCHDOG Register WATCHDOG Logic
00DE
Reserved
0192
0191:0190
018F:018E DIVBY Register
018D:018C T3 Timer
T0CON Register
TMMODE Register
00DD:00DC
00D8
00D6
00D4
00D2
00D0
HALT Enable Register
Port I Input Register
SIO Register
IRCD Register
IRPD Register
ENIR Register
Port Control
& Interrupt
Control
018B:018A R3 Register
Registers
Timer Block T0:T3
0189:0188
0187:0186
0185:0184
0183:0182
0181:0180
T2 Timer
R2 Register
I2CR Register/R1
I3CR Register/T1
I4CR Register
00CF:00CE
00CD:00CC
00CB:00CA
00C9:00C8
00C7:00C6
00C5:00C4
00C3:00C2
00C0
X Register
B Register
K Register
A Register
PC Register
SP Register
Reserved
HPC Core
Registers
015E:015F EICR
015C
EICON
Port P Register
PWMODE Register
0153:0152
0151:0150
PSW Register
014F:014E R7 Register
014D:014C T7 Timer
014B:014A R6 Register
00BF:00BE
: :
0001:0000
Timer Block T4:T7
On-Chip
RAM
User RAM
0149:0148
0147:0146
0145:0144
0143:0142
0141:0140
T6 Timer
R5 Register
T5 Timer
R4 Register
T4 Timer
26
Design Considerations (Continued)
Designs using the HPC family of 16-bit high speed CMOS
microcontrollers need to follow some general guidelines on
usage and board layout.
It is very critical to have an extremely clean power supply for
the HPC crystal oscillator. Ideally one would like a V and
CC
ground plane that provide low inductance power lines to the
chip. The power planes in the PC board should be decou-
pled with three decoupling capacitors as close to the chip
as possible. A 1.0 mF, a 0.1F, and a 0.001F dipped mica or
ceramic cap should be mounted as close to the HPC as is
physically possible on the board, using the shortest leads,
or surface mount components. This should provide a stable
power supply, and noiseless ground plane which will vastly
improve the performance of the crystal oscillator network.
Floating inputs are a frequently overlooked problem. CMOS
inputs have extremely high impedance and, if left open, can
float to any voltage. You should thus tie unused inputs to
V
or ground, either through a resistor or directly. Unlike
CC
the inputs, unused output should be left floating to allow the
output to switch without drawing any DC current.
To reduce voltage transients, keep the supply line’s parasit-
ic inductances as low as possible by reducing trace lengths,
using wide traces, ground planes, and by decoupling the
supply with bypass capacitors. In order to prevent additional
voltage spiking, this local bypass capacitor must exhibit low
inductive reactance. You should therefore use high frequen-
cy ceramic capacitors and place them very near the IC to
minimize wiring inductance.
TABLE V. HPC Oscillator
XTAL
Frequency
(MHz)
R (X)
1
2
1500
1200
910
750
600
470
390
300
220
180
150
120
100
75
4
X
Keep V bus routing short. When using double sided or
CC
multilayer circuit boards, use ground plane techniques.
6
X
8
Keep ground lines short, and on PC boards make them as
wide as possible, even if trace width varies. Use separate
ground traces to supply high current devices such as re-
lay and transmission line drivers.
10
12
14
16
18
20
22
24
26
28
30
X
X
X
X
In systems mixing linear and logic functions and where
supply noise is critical to the analog components’ per-
formance, provide separate supply buses or even sepa-
rate supplies.
If you use local regulators, bypass their inputs with a tan-
talum capacitor of at least 1 mF and bypass their outputs
with a 10 mF to 50 mF tantalum or aluminum electrolytic
capacitor.
If the system uses a centralized regulated power supply,
use a 10 mF to 20F tantalum electrolytic capacitor or a
50 mF to 100 mF aluminum electrolytic capacitor to de-
62
e
e
e
couple the V
bus connected to the circuit board.
R
3.3 MX
CC
F
1
2
C
C
27 pF
33 pF
Provide localized decoupling. For random logic, a rule of
thumb dictates approximately 10 nF (spaced within
12 cm) per every two to five packages, and 100 nF for
every 10 packages. You can group these capacitances,
but it’s more effective to distribute them among the ICs. If
the design has a fair amount of synchronous logic with
outputs that tend to switch simultaneously, additional de-
coupling might be advisable. Octal flip-flop and buffers in
bus-oriented circuits might also require more decoupling.
Note that wire-wrapped circuits can require more decou-
pling than ground plane or multilayer PC boards.
XTAL Specifications: The crystal used was an M-TRON Industries MP-1 Se-
ries XTAL. ‘‘AT’’ cut, parallel resonant.
e
C
L
20 pF
Series Resistance is
@
25X 25 MHz
@
40X 10 MHz
@
600X 2 MHz
A recommended crystal oscillator circuit to be used with the
HPC is shown in Figure 29. See table for recommended
component values. The recommended values given in
Table V have yielded consistent results and are made to
match a crystal with a 20 pF load capacitance, with some
small allowance for layout capacitance.
A recommended layout for the oscillator network should be
as close to the processor as physically possible, entirely
within 1 distance. This is to reduce lead inductance from
×
long PC traces, as well as interference from other compo-
nents, and reduce trace capacitance. The layout contains a
large ground plane either on the top or bottom surface of
the board to provide signal shielding, and a convenient loca-
tion to ground both the HPC, and the case of the crystal.
TL/DD/11046–37
FIGURE 29. Recommended Crystal Circuit
27
Indirect
HPC167064 CPU
The HPC167064 CPU has a 16-bit ALU and six 16-bit regis-
ters.
The instruction contains an 8-bit address field. The contents
of the WORD addressed points to the memory for the oper-
and.
Arithmetic Logic Unit (ALU)
Indexed
The ALU is 16 bits wide and can do 16-bit add, subtract and
shift or logic AND, OR and exclusive OR in one timing cycle.
The ALU can also output the carry bit to a 1-bit C register.
The instruction contains an 8-bit address field and an 8- or
16-bit displacement field. The contents of the WORD ad-
dressed is added to the displacement to get the address of
the operand.
Accumulator (A) Register
Immediate
The 16-bit A register is the source and destination register
for most I/O, arithmetic, logic and data memory access op-
erations.
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand.
Register Indirect (Auto Increment and Decrement)
The operand is the memory addressed by the X register.
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words).
Address (B and X) Registers
The 16-bit B and X registers can be used for indirect ad-
dressing. They can automatically count up or down to se-
quence through data memory.
Register Indirect (Auto Increment and Decrement) with
Conditional Skip
Boundary (K) Register
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory.
The operand is the memory addressed by the B register.
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words). The B register is
then compared with the K register. A skip condition is gener-
ated if B goes past K.
Stack Pointer (SP) Register
The 16-bit SP register is the pointer that addresses the
stack. The SP register is incremented by two for each push
or call and decremented by two for each pop or return. The
stack can be placed anywhere in user memory and be as
deep as the available memory permits.
ADDRESSING MODESÐDIRECT MEMORY AS
DESTINATION
Direct Memory to Direct Memory
Program (PC) Register
The instruction contains two 8- or 16-bit address fields. One
field directly points to the source operand and the other field
directly points to the destination operand.
Immediate to Direct Memory
The 16-bit PC register addresses program memory.
Addressing Modes
ADDRESSING MODESÐACCUMULATOR AS
DESTINATION
The instruction contains an 8- or 16-bit address field and an
8- or 16-bit immediate field. The immediate field is the oper-
and and the direct field is the destination.
Register Indirect
This is the ‘‘normal’’ mode of addressing for the
HPC167064 (instructions are single-byte). The operand is
the memory addressed by the B register (or X register for
some instructions).
Double Register Indirect Using the B and X Registers
Used only with Reset, Set and IF bit instructions; a specific
bit within the 64 kbyte address range is addressed using the
B and X registers. The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register. The specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X.
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand.
HPC Instruction Set Description
Description
Mnemonic
Action
ARITHMETIC INSTRUCTIONS
a
ADD
ADC
Add
Add with carry
Add short imm8
Decimal add with carry
Subtract with carry
Decimal subtract w/carry
Multiply (unsigned)
Divide (unsigned)
MA MemI
x
MA carry
x
C
C
MA MemI
xC
a
a
a
MA MemI Axcarry
x
x
C
C
ADDS
DADC
SUBC
DSUBC
MULT
DIV
A
imm8xCMA carry
x
a
a
MA MemI CxMA (Decimal) carry
x
C
b
b
a
MA
CxMA carry
x
a
C
MemxI
x
MA (Decimal)xcarry
MMAA*/MemIxMMAA,&reXm, 0
X,K0, x0 K,C0x
C
K, carry
DIVD
Divide Double Word (unsigned)
X & MA/MemIxMA, remxX, 0x
Compare MA & MemI, Do next if equal
x
C
IFEQ
IFGT
If equal
If greater than
l
Compare MA & MemI, Do next if MA MemI
AND
OR
XOR
Logical AND
Logical OR
Logical Exclusive-OR
MA and MemIxMA
MA
x
MA xoor rMMeemmI IxMA
MEMORY MODIFY INSTRUCTIONS
a
1
INC
DECSZ
Increment
Decrement, skip if 0
Mem
Mem
1
x
xMMeemm, Skip next if Mem
b
e
0
28
HPC Instruction Set Description (Continued)
Mnemonic
Description
Action
BIT INSTRUCTIONS
SBIT
RBIT
IFBIT
Set bit
Reset bit
If bit
0
1xMMeemm..bbiitt
x
If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
LD
Load
MemI
Mxem(XM)em
xMA
x
g
A, X 1 (or 2)
Load, incr/decr X
Store to Memory
Exchange
x
X
ST
X
AÝ
Exchange, incr/decr X
Push Memory to Stack
Pop Stack to Memory
Load A, incr/decr B,
Skip on condition
Exchange, incr/decr B,
Skip on condition
AÝMem
1 (or 2)
x
x
X
g
a
PUSH
POP
LDS
W
b
Mem(B)
A xWM(SemP)(,XS),PX
SP
SP
2
x
SP, W(SP2)x
W
g
A, B 1 (or 2)
x
x
B,
MeSmki(pBn)Ýext if B greater/less than K
A, B 1 (or 2)
x
B,
g
XS
Skip next if B greater/less than K
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LD B
LD K
LD X
LD BK
Load B immediate
Load K immediate
Load X immediate
Load B and K immediate
immxB
x
immxK
immxBX, imm
x
K
ACCUMULATOR AND C INSTRUCTIONS
CLR A
INC A
DEC A
COMP A
SWAP A
RRC A
RLC A
SHR A
SHL A
SC
Clear A
0
x
A
a
Increment A
Decrement A
Complement A
Swap nibbles of A
Rotate A right thru C
Rotate A left thru C
Shift A right
Shift A left
A
A
x
1xA
b
1
A
1’s complement of A
]
x
A
[
[
]
[
]
[
A 3:0
]
w
A 11:8
w
A 7:4
Ý
Ax15:12 x x x
CwA15 w . . . wA0wC
CxA15
x
. . .x A0x C
0 wA15 w...... wAA00wC
0
CxA15
RC
Reset C
0
1xC
C
Set C
e
e
IFC
IF C
Do next if C
Do next if C
1
0
IFNC
IF not C
TRANSFER OF CONTROL INSTRUCTIONS
a
a
b
a
JSRP
Jump subroutine from table
PC
x
W(SP),SP
Ý
2
x
SP
JSR
Jump subroutine relative
PC
W(SP),SP
a
2
PC xSP,PC
x
x
PC
PC
W(table
x
)
x
a
a
Ý
Ý
Ý
is 1025 to
JSRL
JP
Jump subroutine long
Jump relative short
Jump relative
PC(xW(SP),SP
2
1x023)SP,PC
a
a
a
a
a b
Ý
PC( is 32 to 31)
b
PC( is 257 to 255)
Ý
Ý
Ý
PC
PC
PC
PC
x
x
x
a
Ý
JMP
JMPL
JID
Jump relative long
a
PC
x
a
Jump indirect at PC
A
A
1
PC
a
then Mem(PC) PC
JIDW
NOP
RET
RETSK
RETI
x
PC
a
No Operation
PC
SP
1
x
PC
b
b
Return
x
x
2xSSPP,,WW((SSPP))xPPCC,, &intsekrirpupt re-enabled
Return then skip next
Return from interrupt
SP 2xSP,W(SP)xPC
b
SP
2
Note: W is 16-bit word of memory
MA is Accumulator A or direct memory (8-bit or 16-bit)
Mem is 8-bit byte or 16-bit word of memory
MemI is 8-bit or 16-bit memory or 8-bit or 16-bit immediate data
imm is 8-bit or 16-bit immediate data
imm8 is 8-bit immediate data only
For details of memory usage by each instruction, see The HPC User’s Manual.
29
Code Efficiency
One of the most important criteria of a single chip microcon-
troller is code efficiency. The more efficient the code, the
more features that can be put on a chip. The memory size
on a chip is fixed so if code is not efficient, features may
have to be sacrificed or the programmer may have to buy a
larger, more expensive version of the chip.
DECIMAL ADD AND SUBTRACT
This instruction is needed to interface with the decimal user
world.
It can handle both 16-bit words and 8-bit bytes.
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes. Many applications
store most data in 4-digit variables. The HPC167064 sup-
plies 8-bit byte capability for 2-digit variables and literal vari-
ables.
The HPC family has been designed to be extremely code-
efficient. The HPC looks very good in all the standard cod-
ing benchmarks; however, it is not realistic to rely only on
benchmarks. Many large jobs have been programmed onto
the HPC, and the code savings over other popular micro-
controllers has been considerable.
MULTIPLY AND DIVIDE INSTRUCTIONS
Reasons for this saving of code include the following:
The HPC167064 has 16-bit multiply, 16-bit by 16-bit divide,
and 32-bit by 16-bit divide instructions. This saves both
code and time. Multiply and divide can use immediate data
or data from memory. The ability to multiply and divide by
immediate data saves code since this function is often
needed for scaling, base conversion, computing indexes of
arrays, etc.
SINGLE BYTE INSTRUCTIONS
The majority of instructions on the HPC167064 are single-
byte. There are two especially code-saving instructions: JP
is a 1-byte jump. True, it can only jump within a range of plus
or minus 32, but many loops and decisions are often within
a small range of program memory. Most other micros need
2-byte instructions for any short jumps.
Development Support
JSRP is a 1-byte subroutine call. The user makes a table of
the 16 most frequently called subroutines and these calls
will only take one byte. Most other micros require two and
even three bytes to call a subroutine. The user does not
have to decide which subroutine addresses to put into the
table; the assembler can give this information.
The HPC167064 acts as a stand alone emulator for either
the HPC16083 or the HPC16064. No separate development
tool is thus provided to support this emulator device. The
user will use either the HPC16083 or the HPC16064 (de-
pending on which device is in use) development tools to
develop and debug the application hardware and software
in their target as normally done for the non-emulator HPC
devices. The application software can then be programmed
in the on-chip EPROM and the HPC167064 can then be
plugged in the target system to run the application like a
regular masked ROM device. The HPC167064 can be pro-
grammed using a DATA I/O UNISITE with pinsite module.
EFFICIENT SUBROUTINE CALLS
The 2-byte JSR instructions can call any subroutine within
plus or minus 1k of program memory.
MULTIFUNCTION INSTRUCTIONS FOR DATA MOVE-
MENT AND PROGRAM LOOPING
The HPC167064 has single-byte instructions that perform
multiple tasks. For example, the XS instruction will do the
following:
To support the security feature of the HPC167064, a soft-
ware switch is provided with the linker (under PROMHPC)
which will generate an encrypted hex file for the user. The
purpose is to be able to compare this software generated
encrypted data with the encrypted data produced by the
actual chip to provide a way to verify on-chip EPROM code
after security has been enabled. For details of how to gener-
ate encrypted data and all other HPC167064 features, refer
to the Appendix K of the HPC Family User’s Manual.
1. Exchange A and memory pointed to by the B register
2. Increment or decrement the B register
3. Compare the B register to the K register
4. Generate a conditional skip if B has passed K
The value of this multipurpose instruction becomes evident
when looping through sequential areas of memory and exit-
ing when the loop is finished.
BIT MANIPULATION INSTRUCTIONS
Any bit of memory, I/O or registers can be set, reset or
tested by the single byte bit instructions. The bits can be
addressed directly or indirectly. Since all registers and I/O
are mapped into the memory, it is very easy to manipulate
specific bits to do efficient control.
30
Development Support (Continued)
PROGRAMMING SUPPORT
HOW TO ORDER
The HPC167064 EPROM array can be programmed using a
DATA I/O Unisite model with a pinsite module. No adaptor
board is required with the DATA I/O programmer. Program-
ming of the configuration bytes and security bits is de-
scribed in the HPC Family User’s Manual.
To order a complete development package, select the sec-
tion for the microcontroller to be developed and order the
parts listed.
Development Tools Selection Table
Order
Manual
Description
Includes
Number
Number
HPC-DEV-IBMA
Assembler/Linker/Librarian
Package for IBM PC/AT
HPC Assembler/Linker/Librarian
User’s Manual
424410836-001
HPC-DEV-IBMC
C Compiler
HPC C Compiler User’s Manual
HPC Assembler/Linker/Librarian
User’s Manual
424410883-001
424410836-001
Assembler/Linker/Librarian
Package for IBM PC/AT
DIAL-A-HELPER
If the user has a PC with a communications package then
files from the FILE SECTION can be downloaded to disk for
later use.
Dial-A-Helper is a service provided by the Microcontroller
Applications group. Dial-A-Helper is an Electronic Bulletin
Board Information system and, additionally, provides the ca-
pability of remotely accessing the development system at a
customer site.
Order P/N: MDS-DIAL-A-HLP
Information System Package Contains:
Dial-A-Helper Users Manual
Public Domain Communications Software
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be ac-
cessed over standard dial-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Micro-
controller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities can be found. The minimum require-
ment for accessing Dial-A-Helper is a Hayes compatible mo-
dem.
FACTORY APPLICATIONS SUPPORT
Dial-A-Helper also provides immediate factory applications
support. If a user is having difficulty in operating a MDS,
messages can be left on our electronic bulletin board, which
we will respond to.
Voice: (408) 721-5582
Modem: (408) 739-1162
Baud: 300 or 1200 baud
Set-Up: Length: 8-bit
Parity: None
Stop Bit: 1
Operation: 24 hrs, 7 Days
TL/DD/11046–38
31
Part Selection
The HPC family includes devices with many different options and configurations to meet various application needs. The
number HPC167064 has been generically used throughout this datasheet to represent the whole family of parts. The
following chart explains how to order various options available when ordering HPC family members.
Note: All options may not currently be available.
TL/DD/11046–39
Examples:
a
HPC467064/EL20Ð16k EPROM, Commercial temperature (0 C to 70 C), LDCC
§
§
HPC167064/EL20Ð16k EPROM Military temperature ( 55 C to 125 C), LDCC (to be used for automotive
b
a
§
§
temperature range also)
Socket Selection
Suggested sockets and extractor tool:
Ý
Ý
Socket
Amp
PLCC
821574-1
6141749
*YAMAICHI
1C51-0684-390
1C120-0684-204
ENPLAS
Amp
PLCC-68-1.27-02
821566-1
Ý
Extractors Tool
*A shim must be used in conjunction with this socket to ensure proper contacts. For details of the shim and how to obtain it, contact factory applications group
at (408) 721-5582.
32
33
Physical Dimensions inches (millimeters)
Leaded EPROM Chip Carrier (EL)
Order Number HPC167064EL or HPC467064EL
NS Package Number EL68C
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
National Semiconductor
Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
Fax: 1(800) 737-7018
Fax:
(
49) 0-180-530 85 86
@
13th Floor, Straight Block,
Ocean Centre, 5 Canton Rd.
Tsimshatsui, Kowloon
Hong Kong
Tel: (852) 2737-1600
Fax: (852) 2736-9960
Tel: 81-043-299-2309
Fax: 81-043-299-2408
Email: cnjwge tevm2.nsc.com
a
a
a
a
Deutsch Tel:
English Tel:
Fran3ais Tel:
Italiano Tel:
(
(
(
(
49) 0-180-530 85 85
49) 0-180-532 78 32
49) 0-180-532 93 58
49) 0-180-534 16 80
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
©2020 ICPDF网 联系我们和版权申明