DS92LV2412SQX [NSC]
5-50MHz 24-Bit Channel Link II Serializer and Deserializer; 5-50MHz 24位通道链接II串行器和解串
| 型号： | DS92LV2412SQX |
| 厂家： | 
National Semiconductor |
| 描述： | 5-50MHz 24-Bit Channel Link II Serializer and Deserializer |
| 文件： | 总40页 (文件大小：1108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
May 25, 2010
DS92LV2411/DS92LV2412
5-50MHz 24-Bit Channel Link II Serializer and Deserializer
General Description
Features
The DS92LV2411 (Serializer) / DS92LV2412 (Deserializer)
chipset translates a parallel 24–bit LVCMOS data interface
into a single high-speed CML serial interface with embedded
clock information. This single serial stream eliminates skew
issues between clock and data, reduces connector size and
interconnect cost for transferring a 24-bit, or less, bus over
FR-4 printed circuit board backplanes, differential or coax ca-
bles.
24–bit data, 3–bit control, 5 – 50 MHz clock
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Application payloads up to 1.2 Gbps
AC coupled interconnects: STP up to 10 m or coax 20+ m
1.8V or 3.3V compatible LVCMOS I/O interface
Integrated terminations on Ser and Des
AT-SPEED BIST mode and reporting pin
Configurable by pins or I2C compatible serial control bus
In addition to the 24-bit data bus interface, the
DS92LV2411/12 also features a 3-bit control bus for slow
speed signals. This allows implementing video and display
applications with up to 24–bits per pixel (RGB888), or em-
bedding audio information with compressed video formats.
Power down mode minimizes power dissipation
>8 kV HBM ESD Rating
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SERIALIZER — DS92LV2411
Supports Spread Spectrum Clocking (SSC) on inputs
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■
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Programmable transmit de-emphasis, receive equalization,
on-chip scrambling and DC balancing enables long distance
transmission over lossy cables and backplanes. The
DS92LV2412 automatically locks to incoming data without an
external reference clock or special sync patterns, providing
easy “plug-and-go” or “hot plug” operation. EMI is minimized
by the use of low voltage differential signaling, receiver drive
strength control, and spread spectrum clocking capability.
Data scrambler for reduced EMI
DC-balance encoder for AC coupling
Selectable output VOD and adjustable de-emphasis
DESERIALIZER — DS92LV2412
Random data lock; no reference clock required
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Adjustable input receiver equalization
LOCK (real time link status) reporting pin
The DS92LV2411/12 chipset is programmable though an I2C
interface as well as through pins. A built-in AT-SPEED BIST
feature validates link integrity and may be used for system
diagnostics.
Selectable Spread Spectrum Clock Generation (SSCG)
and output slew rate control (OS) to reduce EMI
Applications
The DS92LV2411 is offered in a 48-pin LLP and the
DS92LV2412 is offered in a 60-pin LLP package. Both de-
vices operate over the full industrial temperature range of -40°
C to +85°C.
Embedded Video and Display
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Medical Imaging
Factory Automation
Office Automation — Printer, Scanner
Security and Video Surveillance
General purpose data communication
Applications Diagram
30065327
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 2010 National Semiconductor Corporation
300653
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Block Diagrams
30065328
30065329
Ordering Information
NSID
DS92LV2411SQ
Package Description
Quantity
SPEC
Package ID
SQA48A
SQA48A
SQA60B
SQA60B
48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch
60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch
60–pin LLP, 9.0 X 9.0 X 0.8 mm, 0.5 mm pitch
TBD
1000
TBD
1000
NOPB
NOPB
NOPB
NOPB
DS92LV2411SQX
DS92LV2412SQ
DS92LV2412SQX
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DS92LV2411 Pin Diagram
30065319
Serializer - DS92LV2411 — Top View
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DS92LV2411 Serializer Pin Descriptions
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
DI[7:0]
DI[15:8]
DI[23:16]
CI1
34, 33, 32, 29, I, LVCMOS Parallel Interface Data Input Pins
28, 27, 26, 25 w/ pull-down For 8–bit RED Display: DI7 = R7 – MSB, DI0 = R0 – LSB.
42, 41, 40, 39, I, LVCMOS Parallel Interface Data Input Pins
38, 37, 36, 35 w/ pull-down For 8–bit GREEN Display: DI15 = G7 – MSB, DI8 = G0 – LSB.
2, 1, 48, 47,
I, LVCMOS Parallel Interface Data Input Pins
46, 45, 44, 43 w/ pull-down For 8–bit BLUE Display: DI23 = B7 – MSB, DI16 = B0 – LSB.
5
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI1 = Data Enable Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI2
3
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI2 = Horizontal Sync Input
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum
transition pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
CI3
4
I, LVCMOS Control Signal Input
w/ pull-down For Display/Video Application:
CI3 = Vertical Sync Input
CI3 is limited to 1 transition per 130 clock cycles. Thus, the minimum pulse width allowed
is 130 clock cycle wide.
I, LVCMOS Clock Input
CLKIN
10
w/ pull-down Latch/data strobe edge set by RFB pin.
Control and Configuration
PDB
21
I, LVCMOS Power-down Mode Input
w/ pull-down PDB = 1, Ser is enabled (normal operation).
Refer to ”Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Ser is powered down
When the Ser is in the power-down state, the driver outputs (DOUT+/-) are both logic high,
the PLL is shutdown, IDD is minimized. Control Registers are RESET.
VODSEL
De-Emph
RFB
24
23
11
I, LVCMOS Differential Driver Output Voltage Select
w/ pull-down VODSEL = 1, CML VOD is ±420 mV, 840 mVp-p (typ) — long cable / De-Emph applications
VODSEL = 0, CML VOD is ±280 mV, 560 mVp-p (typ) — short cable (no De-emph), low
power mode.
This is can also be control by I2C register.
I, Analog
w/ pull-up De-Emph = open (float) - disabled
To enable De-emphasis, tie a resistor from this pin to GND or control via register.
De-Emphasis Control
See Table 3.
This can also be controlled by I2C register access.
I, LVCMOS Clock Input Latch/Data Strobe Edge Select
w/ pull-down RFB = 1, parallel interface data and control signals are latched on the rising clock edge.
RFB = 0, parallel interface data and control signals are latched on the falling clock edge.
This can also be controlled by I2C register access.
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Pin Name
Pin #
I/O, Type Description
CONFIG
[1:0]
13, 12
I, LVCMOS 00: Control Signal Filter DISABLED
w/ pull-down 01: Control Signal Filter ENABLED
10: Reverse compatibility mode to interface with the DS90UR124 or DS99R124Q
11: Reverse compatibility mode to interface with the DS90C124
I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. See Table 10.
ID[x]
6
8
I, Analog
SCL
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
SDA
9
I/O, LVCMOS I2C Serial Control Bus Data Input / Output - Optional
Open Drain SDA requires an external pull-up resistor VDDIO
.
BISTEN
31
I, LVCMOS BIST Mode — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES[2:0]
18, 16, 15
I, LVCMOS Reserved - tie LOW
w/ pull-down
Channel-Link II — CML Serial Interface
DOUT+
20
O, CML
Non–Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
DOUT-
19
O, CML
Inverting Output.
The output must be AC Coupled with a 0.1 µF capacitor.
Power and Ground
VDDL
7
14
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
VDDP
VDDHS
VDDTX
VDDIO
GND
PLL Power, 1.8 V ±5%
17
TX High Speed Logic Power, 1.8 V ±5%
Output Driver Power, 1.8 V ±5%
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10%
22
30
DAP
DAP is the large metal contact at the bottom side, located at the center of the LLP
package. Connect to the ground plane (GND) with at least 9 vias.
NOTE: 1= HIGH, 0 L= LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
5
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DS92LV2412 Pin Diagram
30065320
Deserializer - DS92LV2412 — Top View
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DS92LV2412 Deserializer Pin Descriptions
Pin Name
Pin #
I/O, Type Description
LVCMOS Parallel Interface
DO[7:0]
DO[15:8]
DO[23:16]
CO1
33, 34, 35,
I, STRAP, Parallel Interface Data Output Pins
36, 37, 39, O, LVCMOS For 8–bit RED Display: DO7 = R7 – MSB, DO0 = R0 – LSB.
40, 41
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These
pins are inputs during power-up (See STRAP Inputs).
I, STRAP, Parallel Interface Data Output Pins
20, 21, 22,
23, 25, 26, O, LVCMOS For 8–bit GREEN Display: DO15 = G7 – MSB, DO8 = G0 – LSB.
27, 28
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These
pins are inputs during power-up (See STRAP Inputs).
I, STRAP, Parallel Interface Data Input Pins
9, 10, 11,
12, 14, 17, O, LVCMOS For 8–bit BLUE Display: DO23 = B7 – MSB, DO16 = B0 – LSB.
18, 19
6
In power-down (PDB = 0), outputs are controlled by the OSS_SEL (See Table 7). These
pins are inputs during power-up (See STRAP Inputs).
O, LVCMOS Control Signal Output
For Display/Video Application:
CO1 = Data Enable Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).
CO2
8
O, LVCMOS Control Signal Output
For Display/Video Application:
CO2 = Horizontal Sync Output
Control signal pulse width must be 3 clocks or longer to be transmitted when the Control
Signal Filter is enabled (CONFIG[1:0] = 01). There is no restriction on the minimum transition
pulse when the Control Signal Filter is disabled (CONFIG[1:0] = 00).
The signal is limited to 2 transitions per 130 clocks regardless of the Control Signal Filter
setting.
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).
CO3
7
O, LVCMOS Control Signal Output
For Display/Video Application:
CO3 = Vertical Sync Output
CO3 is different than CO1 and CO2 because it is limited to 1 transition per 130 clock cycles.
Thus, the minimum pulse width allowed is 130 clock cycle wide.
The CONFIG[1:0] pins have no affect on CO3 signal
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7).
CLKOUT
LOCK
5
O, LVCMOS Pixel Clock Output
In power-down (PDB = 0), output is controlled by the OSS_SEL pin (See Table 7). Data
strobe edge set by RFB.
32
O, LVCMOS LOCK Status Output
LOCK = 1, PLL is Locked, outputs are active LOCK = 0, PLL is unlocked, DO[23:0], CO1,
CO2, CO3 and CLKOUT output states are controlled by OSS_SEL (See Table 7). May be
used as Link Status or to flag when Video Data is active (ON/OFF).
PASS
42
O, LVCMOS PASS Output (BIST Mode)
PASS = 1, error free transmission
PASS = 0, one or more errors were detected in the received payload
Route to test point for monitoring, or leave open if unused.
Control and Configuration — STRAP PINS
For a High State, use a 10 kΩ pull up to VDDIO; for a Low State, the IO includes an internal pull down. The STRAP pins are read upon
power-up and set device configuration. Pin Number listed along with shared data output name in square brackets.
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Pin Name
Pin #
I/O, Type Description
CONFIG[1:0]
10 [DO22],
9 [DO23]
STRAP
00: Control Signal Filter DISABLED
I, LVCMOS 01: Control Signal Filter ENABLED
w/ pull-down 10: Reverse compatibility mode to interface with the DS90UR241 or DS99R241
11: Reverse compatibility mode to interface with the DS90C241
LF_MODE
12 [DO20]
STRAP
SSCG Low Frequency Mode
I, LVCMOS Only required when SSCG is enabled, otherwise LF_MODE condition is a DON’T CARE
w/ pull-down (X).
LF_MODE = 1, SSCG in low frequency mode (CLK = 5-20 MHz)
LF_MODE = 0, SSCG in high frequency mode (CLK = 20-50 MHz)
This can also be controlled by I2C register access.
OS_CLKOUT
OS_DATA
OP_LOW
11 [DO21]
14 [DO19]
42 [PASS]
STRAP
Output CLKOUT Slew Select
I, LVCMOS OS_CLKOUT = 1, Increased CLKOUT slew rate
w/ pull-down OS_CLKOUT = 0, Normal CLKOUT slew rate (default)
This can also be controlled by I2C register access.
STRAP
Output DO[23:0], CO1, CO2, CO3 Slew Select
I, LVCMOS OS_DATA = 1, Increased DO slew rate
w/ pull-down OS_DATA = 0, Normal DO slew rate (default)
This can also be controlled by I2C register access.
STRAP
Outputs held LOW when LOCK = 1
I, LVCMOS NOTE: Do not use any other strap options with this strap function enabled
w/ pull-down OP_LOW = 1: all outputs are held LOW during power up until released by programming
OP_LOW release/set register HIGH.
NOTE: Before the device is powered up, the outputs are in TRI-STATE™
See Figure 24 and Figure 25
OP_LOW = 0: all outputs toggle normally as soon as LOCK goes HIGH (default)
This can also be controlled by I2C register access.
OSS_SEL
17 [DO18]
STRAP
Output Sleep State Select
I, LVCMOS OSS_SEL is used in conjunction with PDB to determine the state of the outputs in Power
w/ pull-down Down (Sleep). (See Table 7).
NOTE: OSS_SEL STRAP CANNOT BE USED IF OP_LOW = 1
This can also be controlled by I2C register access.
RFB
18 [DO17]
20 [DO15],
STRAP
Clock Output Strobe Edge Select
I, LVCMOS RFB = 1, parallel interface data and control signals are strobed on the rising clock edge.
w/ pull-down RFB = 0, parallel interface data and control signals are strobed on the falling clock edge.
This can also be controlled by I2C register access.
EQ[3:0]
STRAP
Receiver Input Equalization
21 [DO14], I, LVCMOS (See Table 4).
22 [DO13], w/ pull-down This can also be controlled by I2C register access.
23 [DO12]
OSC_SEL[2:0] 26 [DO10],
27 [DO9],
STRAP
Oscillator Selectl
I, LVCMOS (See Table 8 and Table 9).
28 [DO8] w/ pull-down This can also be controlled by I2C register access.
SSC[3:0]
34 [DO6],
35 [DO5],
STRAP
Spread Spectrum Clock Generation (SSCG) Range Select
I, LVCMOS (See Table 5 and Table 6).
36 [DO4], w/ pull-down This can also be controlled by I2C register access.
37 [DO3]
MAP_SEL[1:0]
40[D],
41 [D]
STRAP
Bit mapping reverse compatibility / DS90UR241 Options
I, LVCMOS Pin or Register Control
w/ pull-down Default setting is b'00.
Control and Configuration
PDB
59
I, LVCMOS Power Down Mode Input
w/ pull-down PDB = 1, Des is enabled (normal operation).
Refer to “Power Up Requirements and PDB Pin” in the Applications Information Section.
PDB = 0, Des is in power-down.
When the Des is in the power-down state, the LVCMOS output state is determined by Table
7. Control Registers are RESET.
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Pin Name
Pin #
I/O, Type Description
I, Analog I2C Serial Control Bus Device ID Address Select — Optional
Resistor to Ground and 10 kΩ pull-up to 1.8V rail. (See Table 10).
ID[x]
56
SCL
SDA
3
2
I, LVCMOS I2C Serial Control Bus Clock Input - Optional
SCL requires an external pull-up resistor to VDDIO
.
I/O,
I2C Serial Control Bus Data Input / Output - Optional
LVCMOS SDA requires an external pull-up resistor to VDDIO
Open Drain
.
BISTEN
44
47
I, LVCMOS BIST Enable Input — Optional
w/ pull-down BISTEN = 0, BIST is disabled (normal operation)
BISTEN = 1, BIST is enabled
RES
NC
I, LVCMOS Reserved - tie LOW
w/ pull-down
1, 15, 16,
30, 31, 45,
46, 60
Not Connected
Leave pin open (float)
Channel-Link II — CML Serial Interface
RIN+
RIN-
CMF
49
50
51
I, CML
I, CML
True Input. The input must be AC Coupled with a 0.1 μF capacitor.
Inverting Input. The input must be AC Coupled with a 0.1 μF capacitor.
I, Analog
Common-Mode Filter
VCM center-tap is a virtual ground which may be ac-coupled to ground to increase receiver
common mode noise immunity. Recommended value is 4.7 μF or higher.
ROUT+
ROUT-
52
53
O, CML
O, CML
True Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Inverting Output — Receive Signal after the Equalizer
NC if not used or connect to test point for monitor. Requires I2C control to enable.
Power and Ground
VDDL
29
48
Power
Power
Power
Power
Power
Power
Power
Ground
Logic Power, 1.8 V ±5%
VDDIR
Input Power, 1.8 V ±5%
VDDR
43, 55
4, 58
57
RX High Speed Logic Power, 1.8 V ±5%
SSCG Power, 1.8 V ±5%
VDDSC
VDDPR
VDDCMLO
VDDIO
GND
PLL Power, 1.8 V ±5%
54
RX High Speed Logic Power, 1.8 V ±5%
13, 24, 38
DAP
LVCMOS I/O Power, 1.8 V ±5% OR 3.3 V ±10% (VDDIO)
DAP is the large metal contact at the bottom side, located at the center of the LLP package.
Connected to the ground plane (GND) with at least 9 vias.
NOTE: 1 = HIGH, 0 = LOW
The VDD (VDDn and VDDIO) supply ramp should be faster than 1.5 ms with a monotonic rise. If slower then 1.5 ms then a capacitor
on the PDB pin is needed to ensure PDB arrives after all the VDD have settled to the recommended operating voltage.
9
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ꢀθJA
24.2 °C/W
4.5 °C/W
≥±8 kV
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
ꢀθJC
ESD Rating (HBM)
Recommended Operating
Conditions
Supply Voltage – VDDn (1.8V)
Supply Voltage – VDDIO
LVCMOS I/O Voltage
Receiver Input Voltage
Driver Output Voltage
Junction Temperature
Storage Temperature
48L LLP Package
−0.3V to +2.5V
−0.3V to +4.0V
−0.3V to +(VDDIO + 0.3V)
−0.3V to (VDD + 0.3V)
−0.3V to (VDD + 0.3V)
+150°C
Min
1.71
1.71
Nom
Max
1.89
1.89
Units
V
V
Supply Voltage (VDDn
LVCMOS Supply
)
1.8
1.8
Voltage (VDDIO
)
−65°C to +150°C
OR
LVCMOS Supply
Voltage (VDDIO
Operating Free Air
Temperature (TA)
Clock Frequency
Supply Noise (Note 10)
3.0
3.3
3.6
V
Maximum Power Dissipation
Capacity at 25°C
Derate above 25°C
)
215 mW
1/ θJA mW / °C
28.5 °C/W
−40
5
+25
+85
50
100
°C
MHz
mVP-P
ꢀθJA
2.8 °C/W
ꢀθJC
60L LLP Package
Maximum Power Dissipation
Capacity at 25°C
TBD W
Derate above 25°C
TBD mW / °C
Serializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified. (Note 2, Note 3, Note 4)
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
LVCMOS INPUT DC SPECIFICATIONS
VDDIO = 3.0 to 3.6V
VDDIO
VDDIO
0.8
2.2
V
V
V
V
VIH
High Level Input Voltage
Low Level Input Voltage
0.65*
VDDIO
VDDIO = 1.71 to 1.89V
VDDIO = 3.0 to 3.6V
VDDIO = 1.71 to 1.89V
DI[23:0],
CI1,CI2,CI3,
CLKIN, PDB,
VODSEL,
RFB,
GND
VIL
0.35*
VDDIO
GND
VDDIO = 3.0
to 3.6V
BISTEN,
CONFIG[1:0]
−15
−15
±1
±1
+15
+15
μA
μA
IIN
VIN = 0V or VDDIO
Input Current
VDDIO = 1.7
to 1.89V
CML DRIVER DC SPECIFICATIONS
VODSEL = 0
VODSEL = 1
VODSEL = 0
VODSEL = 1
±205
±320
±280
±420
560
±355
±520
VOD
Differential Output Voltage
mV
RL = 100Ω,
De-emph = disabled,
Figure 2
mVp-p
mVp-p
Differential Output Voltage
(DOUT+) – (DOUT-)
VODp-p
ΔVOD
VOS
840
RL = 100Ω, De-emph = disabled,
Output Voltage Unbalance
1
50
mV
VODSEL = L
DOUT+,
DOUT-
VODSEL = 0
VODSEL = 1
1.65
V
V
Offset Voltage – Single-ended RL = 100Ω,
At TP A & B, Figure 1
De-emph = disabled
1.575
Offset Voltage Unbalance
Single-ended
ΔVOS
RL = 100Ω, De-emph = disabled
1
mV
At TP A & B, Figure 1
DOUT+/- = 0V,
De-emph = disabled
IOS
Output Short Circuit Current
VODSEL = 0
−36
100
mA
Internal Output Termination
Reistor
DOUT+,
DOUT-
RTO
80
120
Ω
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10
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
SUPPLY CURRENT
IDDT1
Checker Board
Pattern,
VDD= 1.89V All VDD pins
VDDIO= 1.89V
75
3
85
5
mA
mA
Serializer
Supply Current
(includes load current)
RL = 100 Ω, CLKIN = 50 MHz
De-emph = 3kΩ,
VODSEL = H, Figure 9
IDDIOT1
IDDT2
VDDIO
VDDIO = 3.6V
11
15
mA
Checker Board
Pattern,
VDD= 1.89V All VDD pins
VDDIO= 1.89V
65
3
75
5
mA
mA
De-emph = 6kΩ,
VODSEL = L, Figure 9
IDDIOT2
VDDIO
VDDIO = 3.6V
11
15
mA
IDDZ
VDD= 1.89V All VDD pins
40
5
1000
10
µA
µA
µA
Serializer
Supply Current Power-down
PDB = 0V , (All other
LVCMOS Inputs = 0V)
VDDIO= 1.89V
VDDIO
IDDIOZ
VDDIO = 3.6V
10
20
Deserializer DC Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
3.3 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 3.0 to 3.6V
VIH
VIL
IIN
VDDIO
0.8
High Level Input Voltage
Low Level Input Voltage
Input Current
2.0
GND
−15
V
V
PDB,
BISTEN
VIN = 0V or VDDIO
±1
+15
μA
DO[23:0],
CO1, CO2,
CO3,
CLKOUT,
LOCK, PASS
VDDIO
0.2
-
VOH
IOH = −0.5 mA, RDS = L
VDDIO
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
V
VOL
IOL = +0.5 mA, RDS = L
GND
0.2
V
VOUT = 0V, RDS = L
VOUT = 0V, RDS = H
VOUT = 0V, RDS = L
VOUT = 0V, RDS = H
TBD
TBD
TBD
TBD
mA
mA
mA
mA
CLKOUT
Outputs
Outputs
IOS
Output Short Circuit Current
TRI-STATE® Output Current
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
IOZ
−10
+10
µA
1.8 V I/O LVCMOS DC SPECIFICATIONS – VDDIO = 1.71 to 1.89V
0.65*
VDDIO
VIH
VDDIO
High Level Input Voltage
V
PDB,
BISTEN
0.35*
VDDIO
VIL
IIN
Low Level Input Voltage
Input Current
GND
−15
V
μA
V
VIN = 0V or VDDIO
±1
+15
0.2
DO[23:0],
CO1, CO2,
CO3,
CLKOUT,
LOCK, PASS
VDDIO
- 0.2
VOH
IOH = −0.5 mA, RDS = L
VDDIO
High Level Output Voltage
VOL
IOL = +0.5 mA, RDS = L
Low Level Output Voltage
GND
V
VOUT = 0V, RDS = L
VOUT = 0V, RDS = H
VOUT = 0V, RDS = L
VOUT = 0V, RDS = H
TBD
TBD
TBD
TBD
mA
mA
mA
mA
Output Short Circuit Current
Output Short Circuit Current
TRI-STATE Output Current
CLKOUT
Outputs
Outputs
IOS
PDB = 0V, OSS_SEL = 0V,
VOUT = 0V or VDDIO
IOZ
-10
+10
µA
11
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Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
CML RECEIVER DC SPECIFICATIONS
Differential Input Threshold
High Voltage
VTH
+50
−50
mV
mV
V
VCM = +1.2V (Internal VBIAS
)
Differential Input Threshold
Low Voltage
VTL
RIN+, RIN-
Common Mode Voltage,
Internal VBIAS
VCM
1.2
TBD
TBD
-10
-10
+10
+10
µA
µA
IIN
Input Current
Internal Input Termination
Resistor
RIN+,
RIN-
RTI
80
100
120
Ω
LOOP THROUGH CML DRIVER OUTPUT DC SPECIFICATIONS – EQ TEST PORT
VOD
Differential Output Voltage
RL = 100Ω
TBD
TBD
mV
V
ROUT+/-
Offset Voltage
Single-ended
VOS
RL = 100Ω
SUPPLY CURRENT
IDD1
VDD= 1.89V All VDD pins
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
100
TBD
TBD
TBD
mA
mA
mA
mA
mA
mA
µA
Checker Board
Pattern, RDS = H,
CL = 4pF, Figure 9
VDDIO=1.89V
VDDIO
Deserializer
IDDIO1
VDDIO = 3.6V
Supply Current
(includes load current)
CLKOUT = 50 MHz
IDD2
VDD= 1.89V All VDD pins
Random Pattern, RDS
= H, CL = 4pF
VDDIO =1.89V
VDDIO
IDDIO2
IDDZ
VDDIO = 3.6V
VDD= 1.89V All VDD pins
TBD
TBD
TBD
Deserializer Supply Current
Power Down
PDB = 0V, All other
LVCMOS Inputs = 0V
VDDIO=1.89V
VDDIO
µA
IDDIOZ
VDDIO = 3.6V
µA
Recommended Serializer Timing for CLKIN
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Conditions
5 MHz to 50 MHz, Figure 4
Min
Typ
Max
Units
Transmit Input CLKIN Period
20
T
200
ns
tTCIH
Transmit Input CLKIN High
Time
0.4T
0.5T
0.5T
0.6T
ns
tTCIL
Transmit Input CLKIN Low Time
CLKIN Input Transition Time
0.4T
0.5
0.6T
2.4
35
ns
ns
tCLKT
SSCIN CLKIN Input – Spread
Spectrum at 50 MHz
fmod
fdev
kHz
%
±2
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tLHT
Ser Output Low-to-High
Transition Time, Figure 3
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
200
ps
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
200
200
200
ps
ps
ps
ns
tHLT
Ser Output High-to-Low
RL = 100Ω, De-emphasis = disabled,
VODSEL = 0
Transition Time, Figure 3
RL = 100Ω, De-emphasis = disabled,
VODSEL = 1
tDIS
Input Data - Setup Time,
DI[23:0], CI1, CI2, CI3 to CLKIN
2
Figure 4
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12
Symbol
Parameter
Conditions
Min
Typ
Max
Units
tDIH
Input Data - Hold Time,
Figure 4
CLKIN to DI[23:0], CI1, CI2, CI3
2
ns
tXZD
tPLD
tSD
Ser Ouput Active to OFF Delay,
Figure 6
8
15
10
ns
ms
ns
Serializer PLL Lock Time,
Figure 5
RL = 100Ω
RL = 100Ω
1.4
Serializer Delay - Latency,
Figure 7
144*T
TBD
TBD
TBD
145
tDJIT
Ser Output Total Jitter,
Figure 8
RL = 100Ω, De-Emph = disabled,
RANDOM pattern
UI
Serializer Jitter Transfer
Function -3 dB Bandwidth
λSTXBW
δSTX
kHz
dB
Serializer Jitter Transfer
Function Peaking
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
CLK Output Period
Conditions
tRCP = tTCP
Pin/Freq.
CLKOUT
Min
13.3
45
Typ
T
Max
100
55
Units
ns
tRDC
CLK Output Duty Cycle
50
%
tCLH
LVCMOS
Low-to-High
Transition Time, Figure 10
VDDIO = 1.71 to 1.89V,
CL = 8 pF, OS_CLKOUT/
DATA = L
CLKOUT
2.5
1.5
2.5
1.5
2.5
1.5
2.5
1.5
3.5
2.5
3.5
2.5
3.5
2.5
3.5
2.5
ns
ns
ns
ns
ns
ns
ns
ns
VDDIO = 1.71 to 1.89V
CL = 8 pF, OS_CLKOUT/
DATA = H
VDDIO = 3.0 to 3.6V
CL = 8 pF, OS_CLKOUT/
DATA = L
VDDIO = 3.0 to 3.6V
CL = 8 pF, OS_CLKOUT/
DATA = H
tCHL
LVCMOS
High-to-Low
Transition Time, Figure 10
VDDIO = 1.71 to 1.89V
CL = 8 pF, OS_CLKOUT/
DATA = L
CLKOUT
VDDIO = 1.71 to 1.89V
CL = 8 pF, OS_CLKOUT/
DATA = H
VDDIO = 3.0 to 3.6V
CL = 8 pF), OS_CLKOUT/
DATA = L
VDDIO = 3.0 to 3.6V
CL = 8 pF, OS_CLKOUT/
DATA = H
tROS
Data Valid before CLKOUT –
Set Up Time, Figure 14
VDDIO = 1.71 to 1.89V or
VDDIO = 3.0 to 3.6V
CL = 8 pF (lumped load)
RFB =
DO[23:0], CO1, CO2,
CO3
0.3
0.4
0.5
0.5
UI
UI
tROH
Data Valid after CLKOUT –
Hold Time, Figure 14
VDDIO = 1.71 to 1.89V or
VDDIO = 3.0 to 3.6V
CL = 8 pF (lumped load)
DO[23:0], CO1, CO2,
CO3
13
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Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max
Units
tXZR
Active to OFF Delay, Figure 12 OSS_SEL = 0
DO[23:0], CO1, CO2,
CO3, LOCK, PASS,
CLKOUT
TBD
ns
tDDLT
Deserializer Lock Time,
Figure 13
SSC[3:0] = OFF,
(Note 6)
CLKOUT = 5to 50MHz
10
ms
ms
SSC[3:0] = ON,
(Note 6)
10
tDD
Des Delay - Latency, Figure 11
CLKOUT = 5 to 50 MHz
CLKOUT = 5 to 50 MHz
CLKOUT = 5 to 50 MHz
CLKOUT = 5 to 50 MHz
CLKOUT = 5to 50 MHz
140*T
TBD
TBD
ns
UI
ns
UI
ps
tDPJ
Des Period Jitter
SSC[3:0] = OFF,
(Note 8)
±1
tDCCJ
tRJIT
Des Cycle-to-Cycle Jitter
SSC[3:0] = OFF,
(Note 9)
TBD
0.5
±300
TBD
Des Input Jitter Tolerance,
Figure 16
EQ = OFF
UI
BIST Mode
tPASS BIST PASS Valid Time,
BISTEN = 1, Figure 17
SSCG Mode
TBD
10
ns
fDEV
Spread Spectrum
Clocking Deviation
Frequency
CLKOUT = 5 to 50 MHz,
SSC[3:0] = ON
±0.5
8
±2
%
fMOD
Spread Spectrum
Clocking Modulation
Frequency
CLKOUT = 5 to 50 MHz,
SSC[3:0] = ON
100
kHz
Recommended Timing for the Serial Control Bus
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
fSCL
Parameter
SCL Clock Frequency
SCL Low Period
Conditions
Min
Typ
Max
Units
kHz
us
Standard Mode
Standard Mode
Fast Mode
100
tLOW
4.7
1.3
4.0
0.6
4.0
us
tHIGH
SCL High Period
Standard Mode
Fast Mode
us
us
tHD;STA Hold time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
us
0.6
4.7
0.6
us
us
us
tSU:STA Set Up time for a start or a
repeated start condition,
Figure 18
Standard Mode
Fast Mode
tHD;DAT Data Hold Time,
Standard Mode
Fast Mode
0
3.45
0.9
us
us
ns
ns
us
us
us
Figure 18
0
tSU;DAT Data Set Up Time,
Standard Mode
Fast Mode
250
100
4.0
0.6
4.7
Figure 18
tSU;STO Set Up Time for STOP
Standard Mode
Fast Mode
Condition, Figure 18
tBUF
Bus Free Time
Standard Mode
Fast Mode
Between STOP and START,
Figure 18
1.3
us
tr
tf
SCL & SDA Rise Time,
Figure 18
Standard Mode
Fast Mode
1000
300
300
300
ns
ns
ns
ns
SCL & SDA Fall Time,
Figure 18
Standard Mode
Fast mode
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14
DC and AC Serial Control Bus Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
VIH
VIL
Parameter
Input High Level
Conditions
Min
2.2
Typ
Max
VDD 3.3V
0.8
Units
V
SDA and SCL
SDA and SCL
Input Low Level Voltage
Input Hysteresis
GND
V
VHY
VOL
Iin
>50
mV
V
SDA, IOL = 3mA
0
0.4
SDA or SCL, Vin = VDDIO or GND
-15
+15
µA
ns
ns
ns
ns
ns
pF
tR
SDA RiseTime – READ
SDA Fall Time – READ
40
25
SDA, RPU = X, Cb ≤ 400pF
tF
tSU;DAT Set Up Time — READ
tHD;DAT Hold Up Time — READ
520
55
tSP
Cin
Input Filter
50
Input Capacitance
SDA or SCL
<5
Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability
and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond those indicated in
the Recommended Operating Conditions is not implied. The Recommended Operating Conditions indicate conditions at which the device is functional and the
device should not be operated beyond such conditions.
Note 2: The Electrical Characteristics tables list guaranteed specifications under the listed Recommended Operating Conditions except as otherwise modified
or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are not guaranteed.
Note 3: Typical values represent most likely parametric norms at VDD = 3.3V, Ta = +25 degC, and at the Recommended Operation Conditions at the time of
product characterization and are not guaranteed.
Note 4: Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to ground except VOD, ΔVOD,
VTH and VTL which are differential voltages.
Note 5: When the Serializer output is at TRI-STATE the Deserializer will lose PLL lock. Resynchronization / Relock must occur before data transfer require tPLD
Note 6: tPLD and tDDLT is the time required by the serializer and deserializer to obtain lock when exiting power-down state with an active clock.
Note 7: UI – Unit Interval is equivalent to one serialized data bit width (1UI = 1 / 28*CLK). The UI scales with clock frequency.
Note 8: tDPJ is the maximum amount the period is allowed to deviate over many samples.
Note 9: tDCCJ is the maximum amount of jitter between adjacent clock cycles.
Note 10: Supply noise testing was done with minimum capacitors on the PCB. A sinusoidal signal is AC coupled to the VDDn (1.8V) supply with amplitude = 100
mVp-p measured at the device VDDn pins. Bit error rate testing of input to the Ser and output of the Des with 10 meter cable shows no error when the noise
frequency on the Ser is less than 750 kHz. The Des on the other hand shows no error when the noise frequency is less than 400 kHz.
Note 11: Specification is guaranteed by characterization and is not tested in production.
Note 12: Specification is guaranteed by design and is not tested in production.
15
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AC Timing Diagrams and Test Circuits
30065346
FIGURE 1. Serializer Test Circuit
30065330
FIGURE 2. Serializer Output Waveforms
30065347
FIGURE 3. Serializer Output Transition Times
30065331
FIGURE 4. Serializer Input CLKIN Waveform and Set and Hold Times
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16
30065348
FIGURE 5. Serializer Lock Time
30065349
FIGURE 6. Serializer Disable Time
30065310
FIGURE 7. Serializer Latency Delay
17
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30065350
FIGURE 8. Serializer Output Jitter
30065332
FIGURE 9. Checkerboard Data Pattern
30065305
FIGURE 10. Deserializer LVCMOS Transition Times
30065311
FIGURE 11. Deserializer Delay – Latency
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18
30065313
FIGURE 12. Deserializer Disable Time (OSS_SEL = 0)
30065314
FIGURE 13. Deserializer PLL Lock Times and PDB TRI-STATE™ Delay
30065335
FIGURE 14. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = Off
19
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30065334
FIGURE 15. Deserializer Output Data Valid (Setup and Hold) Times with SSCG = On
30065316
FIGURE 16. Receiver Input Jitter Tolerance
30065352
FIGURE 17. BIST PASS Waveform
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20
30065336
FIGURE 18. Serial Control Bus Timing Diagram
21
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DS92LV2412 Des Modes
Functional Description
CONFIG1 CONFIG0 MODE
SER DEVICE
The DS92LV2411 / DS92LV2412 chipset transmits and re-
ceives 24-bits of data and 3 control signals over a single serial
CML pair operating at 140 Mbps to 1.4 Gbps. The serial
stream also contains an embedded clock, video control sig-
nals and the DC-balance information which enhances signal
quality and supports AC coupling.
L
L
Normal Mode,
Control Signal
Filter disabled
DS92LV2411,
DS92LV2411,
DS92LV0421,
DS92LV0411
L
H
Normal Mode,
Control Signal
Filter enabled
DS92LV2411,
DS92LV2411,
DS92LV0421,
DS92LV0411
The Des can attain lock to a data stream without the use of a
separate reference clock source, which greatly simplifies sys-
tem complexity and overall cost. The Des also synchronizes
to the Ser regardless of the data pattern, delivering true au-
tomatic “plug and lock” performance. It can lock to the incom-
ing serial stream without the need of special training patterns
or sync characters. The Des recovers the clock and data by
extracting the embedded clock information, validating and
then deserializing the incoming data stream providing a par-
allel LVCMOS video bus to the display or ASIC/FPGA.
H
H
L
Reverse
Compatibility
Mode
DS90UR241
H
Reverse
Compatibility
Mode
DS90C241
The DS92LV2411 / DS92LV2412 chipset can operate in 24-
bit color depth (with DE, HS, VS encoded within the serial data
stream). In 18–bit color applications, the three video control
signals maybe sent encoded within the serial bit stream (re-
strictions apply) along with six additional general purpose
signals.
VIDEO CONTROL SIGNAL FILTER — SER & DES
When operating the devices in Normal Mode, the Control Sig-
nals have the following restrictions:
•
•
•
Normal Mode with Control Signal Filter Enabled: Control
Signal 1 and Control Signal 2 — Only 2 transitions per 130
clock cycles are transmitted, the transition pulse must be
3 parallel clocks or longer.
Normal Mode with Control Signal Filter Disabled: Control
Signal 1 and Control Signal 2 — Only 2 transitions per 130
clock cycles are transmitted, no restriction on minimum
transition pulse.
Block Diagrams for the chipset are shown at the beginning of
this datasheet.
Data Transfer
The DS92LV2411 / DS92LV2412 chipset will transmit and
receive a pixel of data in the following format: C1 and C0 rep-
resent the embedded clock in the serial stream. C1 is always
HIGH and C0 is always LOW. The remaining 26 bit spaces
contain the scrambled, encoded and DC-Balanced serial da-
ta.
Control Signal 3 — Only 1 transition per 130 clock cycles
is transmitted , minimum pulse width is 130 clock cycles.
Control Signals are defined as low frequency signals with lim-
ited transition. Glitches of a control signal can cause a visual
error in display applications. This feature allows for the
chipset to validate and filter out any high frequency noise on
the control signals. See Figure.
SER & DES OPERATING MODES AND REVERSE
COMPATIBILITY (CONFIG[1:0])
The DS92LV2411 / DS92LV2412 chipset is compatible with
other single serial lane Channel Link II or FPD-Link II devices.
Configuraiton modes are provided for reverse compatibility
with the DS90C241 / DS90C124 and also the DS90UR241 /
DS90UR124 by setting the respective mode with the CONFIG
[1:0] pins on the Ser or Des as shown in Table and Table. This
selection also determines whether the Control Signal Filter
feature is enabled or disabled in the Normal mode. These
configuration modes are selectable the control pins only.
SERIALIZER Functional Description
The Ser converts a wide parallel input bus to a single serial
output data stream, and also acts as a signal generator for
the chipset Built In Self Test (BIST) mode. The device can be
configured via external pins or through the optional serial
control bus. The Ser features enhance signal quality on the
link by supporting: a selectable VOD level, a selectable de-
emphasis signal conditioning and also the Channel Link II
data coding that provides randomization, scrambling, and DC
Balanacing of the data. The Ser includes multiple features to
reduce EMI associated with display data transmission. This
includes the randomization and scrambling of the data and
also the system spread spectrum clock support. The Ser fea-
tures power saving features with a sleep mode, auto stop
clock feature, and optional LVCMOS (1.8 V) parallel bus com-
patibility.
TABLE 1. DS92LV2411 Ser Modes
CONFIG1 CONFIG0 MODE
DES DEVICE
L
L
Normal Mode,
Control Signal
Filter disabled
DS92LV2412,
DS92LV2412,
DS92LV0422,
DS92LV0412
L
H
Normal Mode,
Control Signal
Filter enabled
DS92LV2412,
DS92LV2412,
DS92LV0422,
DS92LV0412
See also the Functional Description of the chipset's serial
control bus and BIST modes.
EMI Reduction Features
H
H
L
Reverse
Compatibility
Mode
DS90UR124,
DS99R124
Data Randomization & Scrambling
Channel Link II Ser / Des feature a 3 step encoding process
which enables the use of AC coupled interconnects and also
helps to manage EMI. The serializer first passes the parallel
data through a scrambler which randomizes the data. The
randomized data is then DC balanced. The DC balanced and
H
Reverse
Compatibility
Mode
DS90C124
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22
randomized data then goes through a bit shuffling circuit and
is transmitted out on the serial line. This encoding process
helps to prevent static data patterns on the serial stream. The
resulting frequency content of the serial stream ranges from
the parallel clock frequency to the nyquist rate. For example,
if the Ser / Des chip set is operating at a parallel clock fre-
quency of 50 MHz, the resulting frequency content of serial
stream ranges from 50 MHz to 700 MHz ( 50 MHz *28 bits =
1.4 Gbps / 2 = 700 MHz ).
Ser — Spread Spectrum Compatibility
The Ser CLKIN is capable of tracking spread spectrum clock-
ing (SSC) from a host source. The CLKIN will accept spread
spectrum tracking up to 35 kHz modulation and ±0.5, ±1 or
±2% deviations (center spread). The maximum conditions for
the CLKIN input are: a modulation frequency of 35 kHz and
amplitude deviations of ±2% (4% total).
30065360
FIGURE 19. De-Emph vs. R value
Integrated Signal Conditioning Features — Ser
Ser — VOD Select (VODSEL)
Power Saving Features
Ser — Power Down Feature (PDB)
The Ser differential output voltage may be increased by set-
ting the VODSEL pin High. When VODSEL is Low, the VOD
is at the standard (default) level. When VODSEL is High, the
VOD is increased in level. The increased VOD is useful in
extremely high noise environments and also on extra long
cable length applications. When using de-emphasis it is rec-
ommended to set VODSEL = H to avoid excessive signal
attenuation especially with the larger de-emphasis settings.
This feature may be controlled by the external pin or by reg-
ister.
The Ser has a PDB input pin to ENABLE or POWER DOWN
the device. This pin is controlled by the host and is used to
save power, disabling the link when the it is not needed. In
the POWER DOWN mode, the high-speed driver outputs are
both pulled to VDD and present a 0V VOD state. Note – in
POWER DOWN, the optional Serial Bus Control Registers
are RESET.
Ser — Stop Clock Feature
TABLE 2. Differential Output Voltage
The Ser will enter a low power SLEEP state when the CLKIN
is stopped. A STOP condition is detected when the input clock
frequency is less than 3 MHz. The clock should be held at a
static Low or high state. When the CLKIN starts again, the Ser
will then lock to the valid input clock and then transmits the
serial data to the Des. Note – in STOP CLOCK SLEEP, the
optional Serial Bus Control Registers values are RE-
TAINED.
Input
Effect
VOD
mV
VOD
mVp-p
VODSEL
H
L
±420
±280
840
560
Ser — De-Emphasis (De-Emph)
1.8V or 3.3V VDDIO Operation
The De-Emph pin controls the amount of de-emphasis be-
ginning one full bit time after a logic transition that the Ser
drives. This is useful to counteract loading effects of long or
lossy cables. This pin should be left open for standard switch-
ing currents (no de-emphasis) or if controlled by register. De-
emphasis is selected by connecting a resistor on this pin to
ground, with R value between 0.5 kΩ to 1 MΩ, or by register
setting. When using De-Emphasis it is recommended to set
VODSEL = H.
The Ser parallel bus and Serial Bus Interface can operate with
1.8 V or 3.3 V levels (VDDIO) for host compatibility. The 1.8 V
levels will offer lower noise (EMI) and also a system power
savings.
Ser — Pixel Clock Edge Select (RFB)
The RFB pin determines the edge that the data is latched on.
If RFB is High, input data is latched on the Rising edge of the
CLKIN. If RFB is Low, input data is latched on the Falling edge
of the CLKIN. Ser and Des maybe set differently. This feature
may be controlled by the external pin or by register.
TABLE 3. De-Emphasis Resistor Value
De-Emphasis Setting
Disabled
- 12 dB
Resistor Value (kΩ)
Open
0.6
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
1.0
- 9 dB
Optional BIST Mode
2.0
- 6 dB
Please see the following section on the chipset BIST mode
for details.
5.0
- 3 dB
DESERIALIZER Functional Description
The Des converts a single input serial data stream to a wide
parallel output bus, and also provides a signal check for the
chipset Built In Self Test (BIST) mode. The device can be
configured via external pins and strap pins or through the op-
tional serial control bus. The Des features enhance signal
23
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quality on the link with an integrated equalizer on the serial
input and Channel Link II data encoding which provides ran-
domization, scrambling, and DC balanacing of the data. The
Des includes multiple features to reduce EMI associated with
data transmission. This includes the randomization and
scrambling of the data, the output spread spectrum clock
generation (SSCG) support and output clock and data slew
rate select. The Des features power saving features with a
power down mode, and optional LVCMOS (1.8 V) interface
compatibility.
EMI Reduction Features
Des — Output Slew Rate Select (OS_CLKOUT/OS_DATA)
The parallel data outputs and clock outputs of the deserializer
feature selectable output slew rates. The slew rate of the
CLKOUT pin is controlled by the strap pin or register
OS_CLKOUT, while the data outputs (DO[23:0] and CO[3:1])
are controlled by the strap pin or register OS_DATA. When
OS_CLKOUT/DATA = HIGH, the maxium slew rate is select-
ed. When the OS_CLKOUT/DATA = LOW, the minimum slew
rate is selected. Use the higher slew rate when driving longer
traces or a heavier capacitive load.
Integrated Signal Conditioning Features — Des
Des — Input Equalizer Gain (EQ)
Des — Common Mode Filter Pin (CMF) — Optional
The Des can enable receiver input equalization of the serial
stream to increase the eye opening to the Des input. Note this
function cannot be seen at the RxIN+/- input but can be ob-
served at the serial test port (ROUT+/-) enabled via the Serial
Bus control registers. The equalization feature may be con-
trolled by the external pin or by register.
The Des provides access to the center tap of the internal ter-
mination. A capacitor may be placed on this pin for additional
common-mode filtering of the differential pair. This can be
useful in high noise environments for additional noise rejec-
tion capability. A 4.7 µF capacitor may be connected to this
pin to Ground.
TABLE 4. Receiver Equalization Configuration Table
Des — SSCG Generation — Optional
INPUTS
Effect
The Des provides an internally generated spread spectrum
clock (SSCG) to modulate its outputs. Both clock and data
outputs are modulated. This will aid to lower system EMI.
Output SSCG deviations to ±2% (4% total) at up to 100 kHz
modulations is available. See Table 5. This feature may be
controlled by external STRAP pins or by register.
EQ3
L
EQ2
L
EQ1
L
EQ0
H
~1.5 dB
~3 dB
L
L
H
L
H
L
H
H
L
H
~4.5 dB
~6 dB
L
H
L
H
H
H
H
H
X
H
~7.5 dB
~9 dB
L
H
L
H
H
H
X
H
~10.5 dB
~12 dB
OFF*
H
X
H
L
* Default Setting is EQ = Off
TABLE 5. SSCG Configuration (LF_MODE = L) — Des Output
SSC[3:0] Inputs
Result
LF_MODE = L (20 - 50 MHz)
SSC3
SSC2
L
SSC1
L
SSC0
L
fdev (%)
NA
fmod (kHz)
L
L
Disable
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
CLK/2168
CLK/1300
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
CLK/868
CLK/650
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
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24
TABLE 6. SSCG Configuration (LF_MODE = H) — Des Output
SSC[3:0] Inputs
Result
LH_MODE = H (5 - 20 MHz)
SSC3
L
SSC2
L
SSC1
L
SSC0
L
fdev (%)
NA
fmod (kHz)
Disable
L
L
L
H
L
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
±2.0
±0.5
±1.0
±1.5
L
L
H
H
L
CLK/620
CLK/370
L
L
H
L
L
H
H
H
H
L
L
L
H
L
L
H
H
L
L
H
L
H
H
H
H
H
H
H
H
L
L
H
L
CLK/258
CLK/192
L
H
H
L
L
H
L
H
H
H
H
L
H
L
H
H
H
tus. Note – in POWER DOWN, the optional Serial Bus Control
Registers are RESET.
Des — Stop Stream SLEEP Feature
The Des will enter a low power SLEEP state when the input
serial stream is stopped. A STOP condition is detected when
the embedded clock bits are not present. When the serial
stream starts again, the Des will then lock to the incoming
signal and recover the data. Note – in STOP STREAM
SLEEP, the optional Serial Bus Control Registers values are
RETAINED.
30065333
Des — CLOCK-DATA RECOVERY STATUS FLAG (LOCK)
and OUTPUT STATE SELECT (OSS_SEL)
FIGURE 20. SSCG Waveform
1.8V or 3.3V VDDIO Operation
When PDB is driven HIGH, the CDR PLL begins locking to
the serial input and LOCK goes from TRI-STATE to LOW
(depending on the value of the OSS_SEL setting). After the
DS92LV2412 completes its lock sequence to the input serial
data, the LOCK output is driven HIGH, indicating valid data
and clock recovered from the serial input is available on the
parallel bus and clock outputs. The CLKOUT output is held at
its current state at the change from OSC_CLK (if this is en-
abled via OSC_SEL) to the recovered clock (or vice versa).
The Des parallel bus and Serial Bus Interface can operate
with 1.8 V or 3.3 V levels (VDDIO) for target host compatibility.
The 1.8 V levels will offer a lower noise (EMI) and also a sys-
tem power savings.
Power Saving Features
Des — PowerDown Feature (PDB)
If there is a loss of clock from the input serial stream, LOCK
is driven Low and the state of the outputs are based on the
OSS_SEL setting (STRAP PIN configuration or register).
The Des has a PDB input pin to ENABLE or POWER DOWN
the device. This pin can be controlled by the system to save
power, disabling the Des when the display is not needed. An
auto detect mode is also available. In this mode, the PDB pin
is tied High and the Des will enter POWER DOWN when the
serial stream stops. When the serial stream starts up again,
the Des will lock to the input stream and assert the LOCK pin
and output valid data. In POWER DOWN mode, the Data and
CLKOUT output states are determined by the OSS_SEL sta-
Des — Oscillator Output — Optional
The Des provides an optional clock output when the input
clock (serial stream) has been lost. This is based on an inter-
nal oscillator. The frequency of the oscillator may be selected.
This feature may be controlled by the external pin or by reg-
ister. See Table 8 and Table 9.
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TABLE 7. OSS_SEL and PDB Configuration — Des Outputs
OUTPUTS
INPUTS
PDB
Serial
Input
OSS_SEL
CLKOUT
DO[23:0], CO1,
CO2, CO3
LOCK
PASS
X
L
L
L
H
L
Z
Z
Z
L
L
L
H
Z
H
H
H
H
X
L
Z
L
Z
Static
Static
Active
H
H
H
H
X
L
L
Active
Active
TABLE 8. OSC (Oscillator) Mode — Des Output
OUTPUTS
INPUTS
Embedded CLK
CLKOUT
DO[23:0]/CO1/CO2/CO3
LOCK
PASS
NOTE *
OSC
L
L
H
Output
Present
Toggling
Active
H
H
* NOTE — Absent and OSC_SEL ≠ 000
30065340
FIGURE 21. Des Outputs with Output State Select Low (OSS_SEL = L)
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30065353
FIGURE 22. Des Outputs with Output State Select High (OSS_SEL = H)
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TABLE 9. OSC_SEL (Oscillator) Configuration
OSC_SEL[2:0] INPUTS
CLKOUT Oscillator Frequency
OSC_SEL2
OSC_SEL1
OSC_SEL0
L
L
L
L
L
H
L
Off – Feature Disabled – Default
50 MHz ±40%
L
H
H
L
25 MHz ±40%
L
H
L
16.7 MHz ±40%
12.5 MHz ±40%
10 MHz ±40%
H
H
H
H
L
H
L
H
H
8.3 MHz ±40%
H
6.3 MHz ±40%
30065354
FIGURE 23. Des Outputs with Output State High and CLK Output Oscillator Option Enabled
Des — OP_LOW — Optional
Other features should be selected through the I2C
register interface.
The OP_LOW feature is used to hold the LVCMOS outputs,
except for the LOCK output, at a LOW state. When the
OP_LOW feature is enabled, the LVCMOS outputs will be
held at logic LOW while LOCK = LOW. The user must toggle
the OP_LOW Set/Reset register bit to release the outputs to
the normal toggling state. Note that the release of the outputs
can only occur when LOCK is HIGH. The OP_LOW strap op-
tion is assigned to the PASS pin, at pin location 42.
2. The OSS_SEL feature is not available when OP_LOW is
enabled.
Outputs DO[23:0], CO[3:1] and CLKOUT are in TRI-STATE™
before PDB toggles HIGH because the OP-LOW strap value
has not been recognized until the DS92LV2412 powers up.
Figure 24 shows the user controlled release of the OP_LOW
and automatic reset of OP_LOW set on the falling edge of
LOCK. Figure 25 shows the user controlled release of
OP_LOW and manual reset of OP_LOW set. Note manual
reset of OP_LOW can only occur when LOCK is HIGH.
Restrictions on other straps:
1. Other strap options should not be used in order to keep
the data and clock outputs at a true logic LOW state.
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30065365
FIGURE 24. OP_LOW Auto Set
30065366
FIGURE 25. OP_LOW Manual Set/Reset
Des — Clock Edge Select (RFB)
downstream devices. The Des output does not need to use
the same edge as the Ser input. This feature may be con-
trolled by the external pin or by register.
The RFB pin determines the edge that the data is strobed on.
If RFB is High, output data is strobed on the Rising edge of
the CLKOUT. If RFB is Low, data is strobed on the Falling
edge of the CLKOUT. This allows for inter-operability with
29
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Des — Control Signal Filter — Optional
the incoming serial payloads for errors. If an error in the pay-
load (1 to 24) is detected, the PASS pin will switch low for one
half of the clock period. During the BIST test, the PASS output
can be monitored and counted to determine the payload error
rate.
The deserializer provides an optional Control Signal (C3, C2,
C1) filter that monitors the three control signals and eliminates
any pulses or glitches that are 1 or 2 parallel clock periods
wide. Control signals must be 3 parallel clock periods wide (in
its HIGH or LOW state, regardless of which state is active).
This is set by the CONFIG[1:0] strap option or by I2C register
control.
Step 3: To Stop the BIST mode, the Des BISTEN pin is set
Low. The Des stops checking the data and the final test result
is held on the PASS pin. If the test ran error free, the PASS
output will be High. If there was one or more errors detected,
the PASS output will be Low. The PASS output state is held
until a new BIST is run, the device is RESET, or Powered
Down. The BIST duration is user controlled by the duration of
the BISTEN signal.
Des — SSCG Low Frequency Optimization (LF_Mode)
Text to come. This feature may be controlled by the external
pin or by Register.
Des — Strap Input Pins
Step 4: To return the link to normal operation, the Ser BISTEN
Configuration of the device maybe done via configuration in-
put pins and the STRAP input pins, or via the Serial Control
Bus. The STRAP input pins share select parallel bus output
pins. They are used to load in configuration values during the
initial power up sequence of the device. Only a pull-up on the
pin is required when a HIGH is desired. By default the pad
has an internal pull down, and will bias Low by itself. The rec-
ommended value of the pull up is 10 kΩ to VDDIO; open (NC)
for Low, no pull-down is required (internal pull-down). If using
the Serial Control Bus, no pull ups are required.
input is set Low. The Link returns to normal operation.
Figure 27 shows the waveform diagram of a typical BIST test
for two cases. Case 1 is error free, and Case 2 shows one
with multiple errors. In most cases it is difficult to generate
errors due to the robustness of the link (differential data trans-
mission etc.), thus they may be introduced by greatly extend-
ing the cable length, faulting the interconnect, reducing signal
condition enhancements (De-Emphasis, VODSEL, or Rx
Equalization).
Optional Serial Bus Control
Please see the following section on the optional Serial Bus
Control Interface.
Optional BIST Mode
Please see the following section on the chipset BIST mode
for details.
Built In Self Test (BIST)
An optional At-Speed Built In Self Test (BIST) feature sup-
ports the testing of the high-speed serial link. This is useful in
the prototype stage, equipment production, in-system test
and also for system diagnostics. In the BIST mode only a input
clock is required along with control to the Ser and Des BIS-
TEN input pins. The Ser outputs a test pattern (PRBS7) and
drives the link at speed. The Des detects the PRBS7 pattern
and monitors it for errors. A PASS output pin toggles to flag
any payloads that are received with 1 to 24 errors. Upon com-
pletion of the test, the result of the test is held on the PASS
output until reset (new BIST test or Power Down). A high on
PASS indicates NO ERRORS were detected. A Low on PASS
indicates one or more errors were detected. The duration of
the test is controlled by the pulse width applied to the Des
BISTEN pin.
30065343
FIGURE 26. BIST Mode Flow Diagram
BER Calculations
It is possible to calculate the approximate Bit Error Rate
(BER). The following is required:
Inter-operability is supported between this Channel Link II de-
vice and all Channel Link II generations (Gen 1/2/3) — see
respective datasheets for details on entering BIST mode and
control.
•
•
•
Clock Frequency (MHz)
BIST Duration (seconds)
BIST test Result (PASS)
Sample BIST Sequence
See Figure 26 for the BIST mode flow diagram.
The BER is less than or equal to one over the product of 24
times the CLK rate times the test duration. If we assume a 50
MHz clock, a 10 minute (600 second) test, and a PASS, the
BERT is ≤ 1.39 X 10E-12
The BIST mode runs a check on the data payload bits. The
LOCK pin also provides a link status. It the recovery of the C0
and C1 bits does not reconstruct the expected clock signal,
the LOCK pin will switch Low. The combination of the LOCK
and At-Speed BIST PASS pin provides a powerful tool for
system evaluation and performance monitoring.
Step 1: Place the DS92LV2411 Ser in BIST Mode by setting
Ser BISTEN = H. For the DS92LV2411 Ser or DS99R421
Channel Link II Ser BIST Mode is enabled via the BISTEN
pin. A CLKIN is required for BIST. When the Des detects the
BIST mode pattern and command (DCA and DCB code) the
data and control signal outputs are shut off.
Step 2: Place the DS92LV2412 Des in BIST mode by setting
the BISTEN = H. The Des is now in the BIST mode and checks
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30065364
FIGURE 27. BIST Waveforms
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To communicate with a remote device, the host controller
(master) sends the slave address and listens for a response
from the slave. This response is referred to as an acknowl-
edge bit (ACK). If a slave on the bus is addressed correctly,
it Acknowledges (ACKs) the master by driving the SDA bus
low. If the address doesn't match a device's slave address, it
Not-acknowledges (NACKs) the master by letting SDA be
pulled High. ACKs also occur on the bus when data is being
transmitted. When the master is writing data, the slave ACKs
after every data byte is successfully received. When the mas-
ter is reading data, the master ACKs after every data byte is
received to let the slave know it wants to receive another data
byte. When the master wants to stop reading, it NACKs after
the last data byte and creates a stop condition on the bus. All
communication on the bus begins with either a Start condition
or a Repeated Start condition. All communication on the bus
ends with a Stop condition. A READ is shown in Figure 30
and a WRITE is shown in Figure 31.
Optional Serial Bus Control
The Ser and Des may also be configured by the use of a serial
control bus that is I2C protocol compatible. By default, the I2C
reg_0x00'h is set to 00'h and all configuration is set by control/
strap pins. A write of 01'h to reg_0x00'h will enable/allow con-
figuration by registers; this will override the control/strap pins.
Multiple devices may share the serial control bus since mul-
tiple addresses are supported. See Figure 28.
The serial bus is comprised of three pins. The SCL is a Serial
Bus Clock Input. The SDA is the Serial Bus Data Input / Out-
put signal. Both SCL and SDA signals require an external pull
up resistor to VDDIO. For most applications a 4.7 k pull up re-
sistor to VDDIO may be used. The resistor value may be
adjusted for capacitive loading and data rate requirements.
The signals are either pulled High, or driven Low.
If the Serial Bus is not required, the three pins may be left
open (NC).
TABLE 10. ID[x] Resistor Value – DS92LV2411 Ser
Resistor
Address
7'b
Address
8'b
RID kΩ
0 appended
(WRITE)
0.47
2.7
7b' 110 1001 (h'69)
7b' 110 1010 (h'6A)
7b' 110 1011 (h'6B)
7b' 110 1110 (h'6E)
8b' 1101 0010 (h'D2)
8b' 1101 0100 (h'D4)
8b' 1101 0110 (h'D6)
8b' 1101 1100 (h'DC)
8.2
30065341
Open
FIGURE 28. Serial Control Bus Connection
TABLE 11. ID[x] Resistor Value – DS92LV2412 Des
The third pin is the ID[X] pin. This pin sets one of five possible
device addresses. Three different connections are possible.
The pin may be tied to ground. The pin may be pulled to
VDD (1.8V, NOT VDDIO)) with a 10 kΩ resistor. Or a 10 kΩ pull
up resistor (to VDD 1.8V, NOT VDDIO)) and a pull down resistor
of the recommended value to set other three possible ad-
dresses may be used. See Table 10 for the Ser and Table
11 for the Des.
Resistor
Address
7'b
Address
8'b
RID kΩ
0 appended
(WRITE)
0.47
2.7
7b' 111 0001 (h'71)
7b' 111 0010 (h'72)
7b' 111 0011 (h'73)
7b' 111 0110 (h'76)
8b' 1110 0010 (h'E2)
8b' 1110 0100 (h'E4)
8b' 1110 0110 (h'E6)
8b' 1110 1100 (h'EC)
8.2
The Serial Bus protocol is controlled by START, START-Re-
peated, and STOP phases. A START occurs when SCL
transitions Low while SDA is High. A STOP occurs when SDA
transition High while SCL is also HIGH. See Figure 29
Open
30065351
FIGURE 29. START and STOP Conditions
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30065338
FIGURE 30. Serial Control Bus — READ
30065339
FIGURE 31. Serial Control Bus — WRITE
TABLE 12. SERIALIZER — Serial Bus Control Registers
ADD ADD Register Name Bit(s) R/W Defa Function
Description
(dec) (hex)
ult
(bin)
0
0
Ser Config 1
7
6
5
R/W
R/W
R/W
0
0
0
Reserved
Reserved
RFB
Reserved
Reserved
0: Data latched on Falling edge of CLKIN
1: Data latched on Rising edge of CLKIN
4
R/W
R/W
0
VODSEL
0: Low
1: High
3:2
00 CONFIG
00: Control Signal Filter Disabled
01: Control Signal Filter Enabled
10: Reserved
11: Reserved
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: normal mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG
0: Configurations set from control pins
1: Configuration set from registers (except I2C_ID)
1
1
Device ID
REG ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 1101 ID[X]
000
Serial Bus Device ID, Four IDs are:
7b '1101 001 (h'69)
7b '1101 010 (h'6A)
7b '1101 011 (h'6B)
7b '1101 110 (h'6E)
All other addresses are Reserved.
2
2
De-Emphasis
Control
7:5
R/W 000 De-E Setting
000: set by external Resistor
001: -1 dB
010: -2 dB
011: -3.3 dB
100: -5 dB
101: -6.7 dB
110: -9 dB
111: -12 dB
4
R/W
0
De-E EN
0: De-Emphasis Enabled
1: De-Emphasis Disabled
3:0
R/W 000 Reserved
Reserved
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TABLE 13. DESERIALIZER — Serial Bus Control Registers
ADD ADD Register Name Bit(s) R/W Defa Function
Description
(dec) (hex)
ult
(bin)
0
0
Des Config 1
7
6
R/W
R/W
R/W
R/W
R/W
0
0
0
0
LF_MODE
OS_CLKOUT
OS_DATA
RFB
0: 20 to 50 MHz SSCG Operation
1: 5 to 20 MHz SSCG Operation
0: Normal CLKOUT Slew Rate
1: Increased CLKOUT Slew Rate
5
0: Normal DATA Slew Rate
1: Increased DATA Slew Rate
4
0: Data strobed on Falling edge of CLKOUT
1: Data strobed on Rising edge of CLKOUT
3:2
00 CONFIG
00: Normal Mode, Control Signal Filter Disabled
01: Normal Mode, Control Signal Filter Enabled
10: Reserved
11: Reserved
1
R/W
0
SLEEP
Note – not the same function as PowerDown (PDB)
0: Normal Mode
1: Sleep Mode – Register settings retained.
0
7
R/W
R/W
0
0
REG Control
0: Configurations set from control pins / STRAP pins
1: Configurations set from registers (except I2C_ID)
1
1
Slave ID
0: Address from ID[X] Pin
1: Address from Register
6:0
R/W 1110 ID[X]
000
Serial Bus Device ID, Four IDs are:
7b '1110 001 (h'71)
7b '1110 010 (h'72)
7b '1110 011 (h'73)
7b '1110 110 (h'76)
All other addresses are Reserved.
2
2
Des Features 1
7
6
R/W
R/W
0
0
OP_LOW
OSS_SEL
0: Set outputs state LOW (except LOCK)
1: Release output LOW state, outputs toggling
normally
Note: This register only workds during LOCK = 1
Output Sleep State Select
0: CLKOUT, DO[23:0], CO1, CO2, CO3 = Tri-State,
LOCK = Normal, PASS = H
1: CLKOUT, DO[23:0], CO1, CO2, CO3 = L, LOCK =
Normal, PASS = H
5:4
3
R/W
R/W
00 Reserved
Reserved
0
OP_LOW Strap 0: Strap will determine whether OP_LOW feature is
Bypass
ON or OFF
1: Turns OFF OP_LOW feature
2:0
R/W
00 OSC_SEL
000: disable
001: 50 MHz ±40%
010: 25 MHz ±40%
011: 16.7 MHz ±40%
100: 12.5 MHz ±40%
101: 10 MHz ±40%
110: 8.3 MHz ±40%
111: 6.3 MHz ±40%
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ADD ADD Register Name Bit(s) R/W Defa Function
Description
(dec) (hex)
ult
(bin)
3 3
Des Features 2
7:5
R/W 000 EQ Gain
000: ~1.625 dB
001: ~3.25 dB
010: ~4.87 dB
011: ~6.5 dB
100: ~8.125 dB
101: ~9.75 dB
110: ~11.375 dB
111: ~13 dB
4
R/W
0
EQ Enable
0: EQ = disable
1: EQ = enable
3:0
R/W 0000 SSC
IF LF_MODE = 0, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/2168
0010: fdev = ±1.0%, fmod = CLK/2168
0011: fdev = ±1.5%, fmod = CLK/2168
0100: fdev = ±2.0%, fmod = CLK/2168
0101: fdev = ±0.5%, fmod = CLK/1300
0110: fdev = ±1.0%, fmod = CLK/1300
0111: fdev = ±1.5%, fmod = CLK/1300
1000: fdev = ±2.0%, fmod = CLK/1300
1001: fdev = ±0.5%, fmod = CLK/868
1010: fdev = ±1.0%, fmod = CLK/868
1011: fdev = ±1.5%, fmod = CLK/868
1100: fdev = ±2.0%, fmod = CLK/868
1101: fdev = ±0.5%, fmod = CLK/650
1110: fdev = ±1.0%, fmod = CLK/650
1111: fdev = ±1.5%, fmod = CLK/650
IF LF_MODE = 1, then:
000: SSCG disable
0001: fdev = ±0.5%, fmod = CLK/620
0010: fdev = ±1.0%, fmod = CLK/620
0011: fdev = ±1.5%, fmod = CLK/620
0100: fdev = ±2.0%, fmod = CLK/620
0101: fdev = ±0.5%, fmod = CLK/370
0110: fdev = ±1.0%, fmod = CLK/370
0111: fdev = ±1.5%, fmod = CLK/370
1000: fdev = ±2.0%, fmod = CLK/370
1001: fdev = ±0.5%, fmod = CLK/258
1010: fdev = ±1.0%, fmod = CLK/258
1011: fdev = ±1.5%, fmod = CLK/258
1100: fdev = ±2.0%, fmod = CLK/258
1101: fdev = ±0.5%, fmod = CLK/192
1110: fdev = ±1.0%, fmod = CLK/192
1111: fdev = ±1.5%, fmod = CLK/192
4
4
ROUT Config
7
R/W
0
Repeater Enable 0: Output ROUT+/- = disable
1: Output ROUT+/- = enable
6:0
R/W 0000 Reserved
Reserved
000
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TYPICAL APPLICATION CONNECTION
Applications Information
Figure 32 shows a typical connection diagram of the
DS92LV2411 Ser in pin control mode for a 24-bit application.
The CML outputs require 0.1 µF AC coupling capacitors to the
line. The line driver includes internal termination. Bypass ca-
pacitors are placed near the power supply pins. At a minimum,
four 0.1 µF capacitors and a 4.7 µF capacitor should be used
for local device bypassing. System GPO (General Purpose
Output) signals control the PDB and BISTEN pins. In this ap-
plication the RFB pin is tied Low to latch data on the falling
edge of the CLKIN. In this example the cable is long, therefore
the VODSEL pin is tied High and a De-Emphasis value is se-
lected by the resistor R1. The interface to the host is with 1.8
V LVCMOS levels, thus the VDDIO pin is connected also to
the 1.8V rail. The optional Serial Bus control is not used in this
example, thus the SCL, SDA and ID[x] pins are left open. A
delay cap is placed on the PDB signal to delay the enabling
of the device until power is stable.
DISPLAY APPLICATION
The DS92LV2411/DS92LV2412 chipset is intended for inter-
face between a host (graphics processor) and a Display. It
supports an 24-bit color depth (RGB888). In a RGB888 ap-
plication, 24 color bits (D[23:0), Pixel Clock (CLKIN) and three
control bits (C1, C2, C3) are supported across the serial link
with CLK rates from 5 to 50 MHz. The chipset may also be
used in 18-bit color applications. In this application three to
six general purpose signals may also be sent from host to
display.
The Des is expected to be located close to its target device.
The interconnect between the Des and the target device is
typically in the 1 to 3 inch separation range. The input capac-
itance of the target device is expected to be in the 5 to 10 pF
range. Care should be taken on the CLK output trace as this
signal is edge sensitive and strobes the data. It is also as-
sumed that the fanout of the Des is one. If additional loads
need to be driven, a logic buffer or mux device is recom-
mended.
30065344
FIGURE 32. DS92LV2411 Typical Connection Diagram — Pin Control
www.national.com
36
Figure 33 shows a typical connection diagram of the
DS92LV2412 Des in pin/strap control mode for a 24-bit ap-
plication. The CML inputs utilize 0.1 µF coupling capacitors to
the line and the receiver provides internal termination. Bypass
capacitors are placed near the power supply pins. At a mini-
mum, seven 0.1 µF capacitors and two 4.7 µF capacitors
should be used for local device bypassing. System GPO
(General Purpose Output) signals control the PDB and the
BISTEN pins. In this application the RFB pin is tied Low to
strobe the data on the falling edge of the CLKOUT.
STRAP pull-up on DO23. The receiver input equalizer is also
enabled and set to provide 7.5 dB of gain, this is accomplished
with EQ[3:0] set to 1001'b with STRAP pull ups on DO12 and
DO15. To reduce parallel bus EMI, the SSCG feature is en-
abled and set to fmod = CLK/2168 and ±1% with SSC[3:0] set
to 0010'b and a STRAP pull-up on DO4. The desired features
are set with the use of the four pull up resistors.
The interface to the target display is with 3.3V LVCMOS lev-
els, thus the VDDIO pin is connected to the 3.3 V rail. The
optional Serial Bus Control is not used in this example, thus
the SCL, SDA and ID[x] pins are left open. A delay cap is
placed on the PDB signal to delay the enabling of the device
until power is stable.
Since the device in the Pin/STRAP mode, four 10 kΩ pull up
resistors are used on the parallel output bus to select the de-
sired device features. CFEN is set to 1 for Normal Mode with
Control Signal Filter enabled, this is accomplished with the
30065345
FIGURE 33. DS92LV2412 Typical Connection Diagram — Pin Control
37
www.national.com
Power Up Requirements and PDB Pin
quency switching noise. It is recommended to connect power
and ground pins directly to the power and ground planes with
bypass capacitors connected to the plane with via on both
ends of the capacitor. Connecting power or ground pins to an
external bypass capacitor will increase the inductance of the
path.
The VDD (VDDn and VDDIO) supply ramp should be faster than
1.5 ms with a monotonic rise. If slower then 1.5 ms then a
capacitor on the PDB pin is needed to ensure PDB arrives
after all the VDD have settled to the recommended operating
voltage. When PDB pin is pulled to VDDIO, it is recommended
to use a 10 kΩ pull-up and a 22 uF cap to GND to delay the
PDB input signal.
A small body size X7R chip capacitor, such as 0603, is rec-
ommended for external bypass. Its small body size reduces
the parasitic inductance of the capacitor. The user must pay
attention to the resonance frequency of these external bypass
capacitors, usually in the range of 20-30 MHz. To provide ef-
fective bypassing, multiple capacitors are often used to
achieve low impedance between the supply rails over the fre-
quency of interest. At high frequency, it is also a common
practice to use two vias from power and ground pins to the
planes, reducing the impedance at high frequency.
TRANSMISSION MEDIA
The Ser/Des chip set is intended to be used in a point-to-point
configuration, through a PCB trace, through twisted pair cable
or through 50Ω coaxial cables. The Ser and Des provide in-
ternal terminations providing a clean signaling environment.
The interconnect for the differential serial interface should
present a differential impedance of 100Ω. Use cables and
connectors that have matched differential impedance to min-
imize impedance discontinuities. Shielded or un-shielded ca-
bles may be used depending upon the noise environment and
application requirements.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some cas-
es, an external filter many be used to provide clean power to
sensitive circuits such as PLLs.
For 50Ω coaxial cable serial interfaces, any unused input or
output pin must be terminated with an 0.1 µF AC coupling
capacitor and a 50Ω resistor to ground. The PCB traces and
serial interconnect should have a single ended impedance of
50Ω.
Use at least a four layer board with a power and ground plane.
Locate LVCMOS signals away from the CML lines to prevent
coupling from the LVCMOS lines to the CML lines. Closely-
coupled differential lines of 100 Ohms are typically recom-
mended for differential interconnect. The closely coupled
lines help to ensure that coupled noise will appear as com-
mon-mode and thus is rejected by the receivers. The tightly
coupled lines will also radiate less.
LIVE LINK INSERTION
The Ser and Des devices support live pluggable applications.
The automatic receiver lock to random data “plug & go” hot
insertion capability allows the DS92LV2412 to attain lock to
the active data stream during a live insertion event.
PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS
Information on the LLP style package is provided in National
Application Note: AN-1187.
Circuit board layout and stack-up for the Ser/Des devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high frequency
or high-level inputs and outputs to minimize unwanted stray
noise pickup, feedback and interference. Power system per-
formance may be greatly improved by using thin dielectrics (2
to 4 mils) for power / ground sandwiches. This arrangement
provides plane capacitance for the PCB power system with
low-inductance parasitics, which has proven especially effec-
tive at high frequencies, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum elec-
trolytic types. RF capacitors may use values in the range of
0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2 uF
to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
SERIAL INTERCONNECT GUIDELINES
See AN-1108 and AN-905 for full details.
•
•
Use 100Ω coupled differential pairs
Use the S/2S/3S rule in spacings
– S = space between the pair
– 2S = space between pairs
– 3S = space to LVCMOS signal
•
•
Minimize the number of Vias
Use differential connectors when operating above
500Mbps line speed
•
•
•
Maintain balance of the traces
Minimize skew within the pair
Terminate as close to the TX outputs and RX inputs as
possible
Surface mount capacitors are recommended due to their
smaller parasitics. When using multiple capacitors per supply
pin, locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low fre-
Additional general guidance can be found in the LVDS
Owner’s Manual - available in PDF format from the National
web site at: www.national.com/lvds
www.national.com
38
Physical Dimensions inches (millimeters) unless otherwise noted
48–pin LLP Package (7.0 mm x 7.0 mm x 0.8 mm, 0.5 mm pitch)
NS Package Number SQA48A
60–pin LLP Package (9.0 mm x 9.0 mm x 0.8 mm, 0.5 mm pitch)
NS Package Number SQA60B
39
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