DS92LV18TVV [NSC]
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz; 18位总线LVDS串行器/解串器 - 15-66兆赫
| 型号： | DS92LV18TVV |
| 厂家： | 
National Semiconductor |
| 描述： | 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz |
| 文件： | 总20页 (文件大小：466K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 2003
DS92LV18
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz
General Description
Features
n 15–66 MHz 18:1/1:18 Serializer/Deserializer (2.376
Gbps full duplex throughput)
The DS92LV18 Serializer/Deserializer (SERDES) pair trans-
parently translates a 18–bit parallel bus into a BLVDS serial
stream with embedded clock information. This single serial
stream simplifies transferring a 18-bit, or less, bus over PCB
traces and cables by eliminating the skew problems between
parallel data and clock paths. It saves system cost by nar-
rowing data paths that in turn reduce PCB layers, cable
width, and connector size and pins.
n Independent transmitter and receiver operation with
separate clock, enable, and power down pins
n Hot plug protection (power up high impedance) and
synchronization (receiver locks to random data)
n Wide 5% reference clock frequency tolerance for easy
system design using locally-generated clocks
n Line and local loopback modes
n Robust BLVDS serial transmission across backplanes
and cables for low EMI
n No external coding required
This SERDES pair includes built-in system and device test
capability. The line loopback feature enables the user to
check the integrity of the serial data transmission paths of
the transmitter and receiver while deserializing the serial
data to parallel data at the receiver outputs. The local loop-
back feature enables the user to check the integrity of the
transceiver from the local parallel-bus side.
n Internal PLL, no external PLL components required
n Single +3.3V power supply
n Low power: 90mA (typ) transmitter, 100mA (typ) at 66
MHz with PRBS-15 pattern
The DS92LV18 incorporates modified BLVDS signaling on
the high-speed I/O. BLVDS provides a low power and low
noise environment for reliably transferring data over a serial
transmission path. The equal and opposite currents through
the differential data path control EMI by coupling the result-
ing fringing fields together.
n
100 mV receiver input threshold
n Loss of lock detection and reporting pin
n Industrial −40 to +85˚C temperature range
>
n
2.0kV HBM ESD
n Compact, standard 80-pin PQFP package
Block Diagram
DS92LV18
20031201
© 2003 National Semiconductor Corporation
DS200312
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Absolute Maximum Ratings (Note 1)
Maximum Package Power Dissipation Capacity
Package Derating:
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
23.2 mW/˚C above
80L PQFP
+25˚C
43˚C/W
Supply Voltage (VCC
)
−0.3V to +4V
−0.3V to (VCC +0.3V)
−0.3V to (VCC +0.3V)
−0.3V to +3.9V
θJA
LVCMOS/LVTTL Input
Voltage
θJC
11.1˚C/W
>
ESD Rating (HBM)
2.0kV
LVCMOS/LVTTL Output
Voltage
Recommended Operating
Conditions
Bus LVDS Receiver Input
Voltage
Bus LVDS Driver Output
Voltage
Min Nom Max Units
−0.3V to +3.9V
Supply Voltage (VCC
Operating Free Air
Temperature (TA)
Clock Rate
)
3.15
−40
15
3.3
3.45
V
Bus LVDS Output Short
Circuit Duration
Junction Temperature
Storage Temperature
Lead Temperature
(Soldering, 4 seconds)
+25
+85
˚C
10ms
+150˚C
66
MHz
mV
−65˚C to +150˚C
Supply Noise
100
(p-p)
+260˚C
Electrical Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Conditions
Pin/Freq.
Min
Typ
Max Units
LVCMOS/LVTTL DC Specifications
VIH
VIL
High Level Input Voltage
Low Level Input Voltage
2.0
VCC
0.8
V
V
DEN, TCLK,
TPWDN, DIN,
SYNC, RCLK_R/F,
REN, REFCLK,
RPWDN
GND
VCL
Input Clamp Voltage
ICL = −18 mA
-0.7
−1.5
V
IIN
Input Current
VIN = 0V or 3.6V
IOH = −9 mA
IOL = 9 mA
−10
2.3
2
3.0
+10
VCC
0.5
µA
V
VOH
VOL
IOS
High Level Output Voltage
Low Level Output Voltage
Output Short Circuit Current
R
OUT, RCLK, LOCK
ROUT, RCLK
GND
−15
0.33
−48
V
VOUT = 0V
−85
mA
PWRDN or REN =
0.8V, VOUT = 0V or
VCC
IOZ
TRI-STATE Output Current
−10
0.4
+10
µA
Bus LVDS DC specifications
Differential Threshold High
VTH
VTL
+100 mV
mV
Voltage
Differential Threshold Low
Voltage
VCM = +1.1V
RI+, RI-
−100
−10
VIN = +2.4V, VCC
3.6V or 0V
=
5
5
+10
+10
µA
µA
IIN
Input Current
VIN = 0V, VCC = 3.6V
or 0V
−10
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2
Electrical Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Output Differential Voltage
(DO+) - (DO-)
Conditions
Pin/Freq.
Min
Typ
Max Units
VOD
Figure 18, RL = 100Ω
350
500
550
15
mV
mV
Output Differential Voltage
Unbalance
∆VOD
2
VOS
Offset Voltage
1.05
-35
1.2
2.7
1.25
15
V
∆VOS
Offset Voltage Unbalance
mV
DO = 0V, Din = H,
TPWDN and DEN =
2.4V
DO+, DO-
IOS
Output Short Circuit Current
-50
-70
mA
TPWDN or DEN =
0.8V, DO = 0V OR
VDD
IOZ
TRI-STATE Output Current
Power-Off Output Current
-10
-10
1
1
10
10
µA
µA
VDD = 0V, DO = 0V
or 3.6V
IOX
SER/DES SUPPLY CURRENT (DVDD, PVDD and AVDD pins)
CL = 15pF,
f = 66 MHz,
PRBS-15 pattern
f = 66 MHz, Worst
case pattern
190
220
1.5
mA
mA
mA
RL = 100 Ω
Total Supply Current (includes
ICCT
load current)
CL = 15 pF,
320
3.0
RL = 100 Ω
(Checker-board
pattern)
PWRDN = 0.8V,
REN = 0.8V
ICCX
Supply Current Powerdown
Serializer Timing Requirements for TCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tTCP
Parameter
Transmit Clock Period
Transmit Clock High Time
Transmit Clock Low Time
TCLK Input Transition
Time
Conditions
Min
15.2
0.4T
0.4T
Typ
T
Max
66.7
0.6T
0.6T
Units
ns
tTCIH
0.5T
0.5T
ns
tTCIL
ns
tCLKT
tJIT
3
6
ns
ps
TCLK Input Jitter
(Note 8)
80
(RMS)
Serializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
Bus LVDS Low-to-High
Transition Time
Conditions
Min
Typ
Max
Units
tLLHT
0.2
0.4
ns
Figure 3, (Note 8)
RL = 100Ω,
CL=10pF to GND
Bus LVDS High-to-Low
Transition Time
tLHLT
tDIS
0.2
0.4
ns
ns
ns
DIN (0-17) Setup to TCLK
DIN (0-17) Hold from
TCLK
2.4
0
Figure 6, (Note 8)
RL = 100Ω,
CL=10pF to GND
tDIH
3
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Serializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
DO HIGH to
Conditions
Min
Typ
Max
Units
tHZD
2.3
10
ns
TRI-STATE Delay
DO LOW to
tLZD
tZHD
tZLD
tSPW
1.9
1.0
1.0
10
10
ns
ns
ns
ns
ns
Figure 7 (Note 4)
RL = 100Ω,
CL=10pF to GND
TRI-STATE Delay
DO TRI-STATE to
HIGH Delay
DO TRI-STATE to
LOW Delay
10
Figure 9,
RL = 100Ω
SYNC Pulse Width
5*tTCP
6*tTCP
Figure 8,
tPLD
tSD
Serializer PLL Lock Time
Serializer Delay
510*tTCP
1024*tTCP
tTCP + 4.0
RL = 100Ω
Figure 10 , RL = 100Ω
Room Temp., 3.3V,
66 MHz
tTCP + 1.0
tTCP + 2.0
4.5
ns
ps
tRJIT
Random Jitter
(RMS)
ps
15 MHz
-430
-40
190
70
Deterministic Jitter
tDJIT
Figure 16, (Note 8)
66 MHz
ps
Deserializer Timing Requirements for REFCLK
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRFCP
Parameter
REFCLK Period
REFCLK Duty Cycle
Ratio of REFCLK to
TCLK
Conditions
Min
15.2
40
Typ
T
Max
66.7
60
Units
ns
tRFDC
50
%
tRFCP
tTCP
/
0.95
1.05
6
tRFTT
REFCLK Transition Time
ns
Deserializer Switching Characteristics
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
tRCP
Parameter
Receiver out Clock
Period
Conditions
Pin/Freq.
RCLK
Min
15.2
45
Typ
Max
66.7
55
Units
ns
tRCP = tTCP
tRDC
RCLK Duty Cycle
CMOS/TTL
RCLK
50
%
tCLH
Low-to-High
2.2
4
4
ns
ns
Transition Time
CMOS/TTL
CL = 15 pF
Figure 4
ROUT(0-17),
LOCK,
tCHL
High-to-Low
2.2
Transition Time
ROUT (0-9) Setup
Data to RCLK
ROUT (0-9) Hold
Data to RCLK
RCLK
tROS
tROH
0.35*tRCP
0.5*tRCP
ns
ns
Figure 12
−0.35*tRCP
−0.5*tRCP
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4
Deserializer Switching Characteristics (Continued)
Over recommended operating supply and temperature ranges unless otherwise specified.
Symbol
Parameter
HIGH to TRI-STATE
Delay
Conditions
Pin/Freq.
Min
Typ
Max
Units
tHZR
2.2
10
ns
LOW to TRI-STATE
Delay
tLZR
tZHR
tZLR
tDD
2.2
2.3
2.9
10
10
10
ns
ns
ROUT(0-17),
LOCK
Figure 13
TRI-STATE to HIGH
Delay
TRI-STATE to LOW
Delay
ns
ns
µs
Deserializer Delay
Deserializer PLL
Lock Time from
Powerdown (with
SYNCPAT)
RCLK
1.75*tRCP + 2.1 1.75*tRCP + 4.0 1.75*tRCP + 6.1
15MHz
3.7
1.9
10
4
Figure 14,
tDSR1
(Note 7) (Note 8)
66 MHz
µs
Deserializer PLL
Lock time from
SYNCPAT
15MHz
1.5
0.9
5
2
µs
µs
Figure 15,
tDSR2
(Note 7) (Note 8)
66 MHz
15 MHz
66 MHz
15 MHz
66 MHz
15 MHz
66 MHz
1490
180
ps
ps
ps
ps
ps
ps
Ideal Deserializer
Figure 17
tRNMI-R
tRNMI-L
tJI
Noise Margin Right
(Note 6) (Note 8)
1460
330
Ideal Deserializer
Noise Margin Left
Figure 17
(Note 6) (Note 8)
1060
160
Total Interconnect
Jitter Budget
(Note 9)
Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices
should be operated at these limits. The table of “Electrical Characteristics” specifies conditions of device operation.
Note 2: Typical values are given for V
= 3.3V and T = +25˚C.
A
CC
Note 3: Current into device pins is defined as positive. Current out of device pins is defined as negative. Voltages are referenced to ground except VOD, ∆VOD,
VTH and VTL which are differential voltages.
Note 4: Due to TRI-STATE of the Serializer, the Deserializer will lose PLL lock and have to resynchronize before data transfer.
Note 5: t
is the time required by the deserializer to obtain lock when exiting powerdown mode. t
is specified with synchronization patterns (SYNCPATs)
DSR1
DSR1
present at the LVDS inputs (RI+ and RI-) before exiting powerdown mode. t
is the time required to obtain lock for the powered-up and enabled deserializer when
DSR2
the LVDS input (RI+ and RI-) conditions change from not receiving data to receiving synchronization patterns. Both t
running and stable.
and t
are specified with the REFCLK
DSR1
DSR2
Note 6: t
is a measure of how much phase noise (jitter) the deserializer can tolerate in the incoming data stream before bit errors occur. It is a measurement
RNMI
in reference with the ideal bit position, please see National’s AN-1217 for detail.
Note 7: A sync pattern is a fixed pattern with 9-bits of data high followed by 9-bits of data low. The SYNC pattern is automatically generated by the transmitter when
the SYNC pin is pulled high.
Note 8: Guaranteed by Design (GBD) using statistical analysis.
Note 9: Total Interconnect Jitter Budget (t ) specifies the allowable jitter added by the interconnect assuming both transmitter and receiver are DS92LV18 circuits.
JI
t
is GBD using statistical analysis.
JI
5
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AC Timing Diagrams and Test Circuits
20031203
FIGURE 1. “Worst Case” Serializer ICC Test Pattern
20031204
FIGURE 2. “Worst Case” Deserializer ICC Test Pattern
20031205
FIGURE 3. Serializer Bus LVDS Distributed Output Load and Transition Times
20031206
FIGURE 4. Deserializer CMOS/TTL Distributed Output Load and Transition Times
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AC Timing Diagrams and Test Circuits (Continued)
20031207
FIGURE 5. Serializer Input Clock Transition Time
20031208
FIGURE 6. Serializer Setup/Hold Times
20031209
FIGURE 7. Serializer TRI-STATE Test Circuit and Timing
7
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AC Timing Diagrams and Test Circuits (Continued)
20031210
FIGURE 8. Serializer PLL Lock Time, and PWRDN TRI-STATE Delays
20031234
FIGURE 9. SYNC Timing Delay
20031211
FIGURE 10. Serializer Delay
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8
AC Timing Diagrams and Test Circuits (Continued)
20031212
FIGURE 11. Deserializer Delay
20031213
FIGURE 12. Deserializer Setup and Hold Times
20031214
FIGURE 13. Deserializer TRI-STATE Test Circuit and Timing
9
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AC Timing Diagrams and Test Circuits (Continued)
20031215
FIGURE 14. Deserializer PLL Lock Times and PWRDN TRI-STATE Delays
20031222
FIGURE 15. Deserializer PLL Lock Time from SYNCPAT
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AC Timing Diagrams and Test Circuits (Continued)
20031229
FIGURE 16. Deterministic Jitter and Ideal Bit Position
20031232
t
t
is the noise margin on the left of the figure above.
is the noise margin on the right of the above figure.
RNMI-L
RNMI-R
FIGURE 17. Deserializer Noise Margin (tRNMI) and Sampling window
11
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AC Timing Diagrams and Test Circuits (Continued)
20031216
+
−
V
OD
= (DO )–(DO ).
Differential output signal is shown as (DO+)–(DO−), device in Data Transfer mode.
FIGURE 18. VOD Diagram
20031235
FIGURE 19. Typical ICC vs. Frequency with PRBS-15 Pattern (Transmitter Only)
20031236
FIGURE 20. Typical ICC vs. Frequency with PRBS-15 Pattern (Receiver Only)
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Functional Description
The DS92LV18 combines a serializer and deserializer onto a
single chip. The serializer accepts an 18-bit LVCMOS or
LVTTL data bus and transforms it into a BLVDS serial data
stream with embedded clock information. The deserializer
then recovers the clock and data to deliver the resulting
18-bit wide words to the output.
clock, the LOCK pin goes low and valid data appears on the
output. Note that the LOCK signal is synchronous to valid
data appearing on the outputs.
The user’s application determines whether SYNC or lock-to-
random-data mode is the preferred method for synchroniza-
tion. If sync-patterns are preferred, the associated Deserial-
izer’s LOCK pin is a convenient way to provide control of the
Serializer’s SYNC pin.
The device has a separate transmit block and receive block
that can operate independently of each other. Each has a
power down control to enable efficient operation in various
applications. For example, the transceiver can operate as a
standby in a redundant data path but still conserve power.
The part can be configured as a Serializer, Deserializer, or
as a Full Duplex SER/DES.
Data Transfer
After initialization, the DS92LV18 Serializer is able to transfer
data to the Deserializer. The serial data stream includes a
start bit and stop bit appended by the serializer, which
frames the eighteen data bits. The start bit is always high
and the stop bit is always low. The start and stop bits also
function as clock bits embedded in the serial stream.
The DS92LV18 serializer and deserializer blocks each have
three operating states. They are the Initialization, Data
Transfer, and Resynchronization states. In addition, there
are two passive states: Powerdown and TRI-STATE.
The Serializer block accepts data from the DIN0-DIN17 par-
allel inputs. The TCLK signal latches the incoming data on
the rising edge. If the SYNC input is high for 6 TCLK cycles,
the DS92LV18 does not latch data from DIN0-DIN17.
The following sections describe each operation mode and
passive state.
Initialization
The Serializer transmits the data and clock bits (18+2 bits) at
20 times the TCLK frequency. For example, if TCLK is 60
MHz, the serial rate is 60 X 20= 1200 Mbps. Since only 18
bits are from input data, the serial ’payload’ rate is 18 times
the TCLK frequency. For instance, if TCLK = 60 MHz, the
payload data rate is 60 X 18 = 1080 Mbps. TCLK is provided
by the data source and must be in the range of 15 MHz to 66
MHz.
Before the DS92LV18 sends or receives data, it must initial-
ize the links to and from another DS92LV18. Initialization
refers to synchronizing the Serializer’s and Deserializer’s
PLL’s to local clocks. The local clocks must be the same
frequency or within a specified range if from different
sources. After the Serializers synchronize to the local clocks,
the Deserializers synchronize to the Serializers as the sec-
ond and final initialization step.
When the Deserializer channel synchronizes to the input
from a Serializer, it drives its LOCK pin low and synchro-
nously delivers valid data on the output. The Deserializer
locks to the embedded clock, uses it to generate multiple
internal data strobes, and then drives the recovered clock to
the RCLK pin. The recovered clock (RCLK output pin) is
synchronous to the data on the ROUT[0:17] pins. While
LOCK is low, data on ROUT[0:17] is valid. Otherwise,
ROUT[0:17] is invalid.
Step 1: When VCC is applied to both Serializer and/or Dese-
rializer, the respective outputs are held in TRI-STATE and
internal circuitry is disabled by on-chip power-on circuitry.
When VCC reaches VCC OK (2.2V) the PLL in each device
begins locking to a local clock. For the Serializer, the local
clock is the transmit clock, TCLK. For the Deserializer, the
local clock is applied to the REFCLK pin. A local on-board
oscillator or other source provides the specified clock input
to the TCLK and REFCLK pin.
ROUT[0:17], LOCK, and RCLK signals will drive a minimum
of three CMOS input gates (15pF total load) at a 66 MHz
clock rate. This drive capacity allows bussing outputs of
multiple Deserializers to multiple destination ASIC inputs.
REN controls TRI-STATE for ROUTn and the RCLK pin on
the Deserializer.
The Serializer outputs are held in TRI-STATE while the PLL
locks to the TCLK. After locking to TCLK, the Serializer block
is now ready to send data or synchronization patterns. If the
SYNC pin is high, then the Serializer block generates and
sends the synchronization patterns (sync-pattern).
The Deserializer output will remain in TRI-STATE while its
PLL locks to the REFCLK. Also, the Deserializer LOCK
output will remain high until its PLL locks to incoming data or
a sync-pattern on the RIN pins.
The Deserializer input pins are high impedance during re-
ceiver powerdown (RPWDN low) and power-off (VCC = 0V).
Resynchronization
Step 2: The Deserializer PLL must synchronize to the Seri-
alizer to complete the initialization. The Serializer that is
generating the stream to the Deserializer must send random
(non-repetitive) data patterns or sync-patterns during this
step of the Initialization State. The Deserializer will lock onto
sync-patterns within a specified amount of time. The lock to
random data depends on the data patterns and therefore,
the lock time is unspecified.
If the Deserializer loses lock, it will automatically try to re-
synchronize. For example, if the embedded clock edge is not
detected two times in succession, the PLL loses lock and the
LOCK pin is driven high. The Deserializer then enters the
operating mode where it tries to lock to a random data
stream. It looks for the embedded clock edge, identifies it
and then proceeds through the synchronization process.
The logic state of the LOCK signal indicates whether the
data on ROUT is valid; when it is low, the data is valid. The
system must monitor the LOCK pin to determine whether
data on the ROUT is valid. Because there is a short delay in
the LOCK signal’s response to the PLL losing synchroniza-
tion to the incoming data stream, the system must determine
the validity of data for the cycles before the LOCK signal
goes high.
In order to lock to the incoming LVDS data stream, the
Deserializer identifies the rising clock edge in a sync-pattern
and locks to it. If the Deserializer is locking to a random data
stream from the Serializer, then it performs a series of op-
erations to identify the rising clock edge and locks to it.
Because this locking procedure depends on the data pat-
tern, it is not possible to specify how long it will take. At the
point when the Deserializer’s PLL locks to the embedded
13
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DEN signal high, the Serializer output will return to the
previous state as long as all other control and data input pins
remain in the same condition before DEN was driven low.
Resynchronization (Continued)
The user can choose to resynchronize to the random data
stream or to force fast synchronization by pulsing the Seri-
alizer’s SYNC pin. Lock times depend on serial data stream
characteristics. The primary constraint on the "random" lock
time is the initial phase relation between the incoming data
and the REFCLK when the Deserializer powers up. An ad-
vantage of using the SYNC pattern to force synchronization
is the ability for the user to predict the delay before the PLL
regains lock. This scheme is left up to the user discretion.
One recommendation is to provide a feedback loop using the
LOCK pin itself to control the sync request of the Serializer,
which is the SYNC pin.
Loopback Test Operation
The DS92LV18 includes two Loopback modes for testing the
device functionality and the transmission line continuity. As-
serting the Line Loopback control signal connects the serial
data input (RIN ) to the serial data output (DO ) and to the
parallel data output (ROUT[0:17]). The serial data goes
through deserializer and serializer blocks.
Asserting the Local Loopback control signal connects the
parallel data input (DIN[0:17]) back to the parallel data out-
put (ROUT[0:17]). The connection route includes all the
functional blocks of the SER/DES Pair. The serial data out-
put (DO ) is automatically disabled during the Local Loop-
back operating mode.
If a specific pattern is repetitive, the Deserializer’s PLL will
not lock in order to prevent the Deserializer from locking to
the data pattern rather than the clock. We refer to such
pattern as a repetitive multi-transition, RMT. This occurs
when more than one Low-High transition takes places in a
clock cycle over multiple cycles. This occurs when any bit,
except DIN 17, is held at a low state and the adjacent bit is
held high, creating a 0-1 transition. The internal circuitry
accomplishes this by detecting more than one potential po-
sition for clocking bits. Upon detection, the circuitry will pre-
vent the LOCK output from becoming active until the RMT
pattern changes. Once the RMT pattern changes and the
internal circuitry recognizes the clock bits in the serial data
stream, the PLL of the Deserializer will lock, which will drive
the LOCK output to low and the output data ROUTn will
become valid.
Please note that when switching between normal, line, or
loopback modes, the deserializer will need to relock. In order
for the serializer and deserializer to resync, the TCLK and
REFCLK frequencies must be within 5% of each other.
Application Information
USING THE DS92LV18
The DS92LV18 combines a Serializer and Deserializer onto
a single chip that sends 18 bits of parallel TTL data over a
serial Bus LVDS link up to 1.32 Gbps. Serialization of the
input data is accomplished using an on-board PLL at the
Serializer which embeds two clock bits with the data. The
Deserializer uses a separate reference clock (REFCLK) and
an on-board PLL to extract the clock information from the
incoming data stream and deserialize the data. The Deseri-
alizer monitors the incoming clock information to determine
lock status and will indicate loss of lock by asserting the
LOCK output high.
Powerdown
The Powerdown state is a low power sleep mode that the
Serializer and Deserializer will occupy while waiting for ini-
tialization. You can also use TPWDN and RPWDN to reduce
power when there are no pending data transfers. The Dese-
rializer enters powerdown mode when RPWDN is driven low.
In powerdown mode, the PLL stops and the outputs enter
TRI-STATE, which reduces supply current to the µA range.
POWER CONSIDERATIONS
An all CMOS design of the Serializer and Deserializer makes
them inherently low power devices. Additionally, the constant
current source nature of the LVDS outputs minimize the
slope of the speed vs. ICC curve of CMOS designs.
To bring the Deserializer block out of the Powerdown state,
the system drives RPWDN high. When the Deserializer exits
Powerdown, it automatically enters the Initialization state.
The system must then allow time for Initialization before data
transfer can begin.
POWERING UP THE DESERIALIZER
The TPWDN pin driven low forces the Serializer block into
low power consumption, where the supply current is in the
µA range. The Serializer PLL stops and the output goes into
a TRI-STATE condition.
The REFCLK input can be running before the Deserializer is
powered up and it must be running in order for the Deseri-
alizer to lock to incoming data. The Deserializer outputs will
remain in TRI-STATE until the Deserializer detects data
transmission at its inputs and locks to the incoming serial
data stream.
To bring the Serializer block out of the powerdown state, the
system drives TPWDN high. When the Serializer exits Pow-
erdown, its PLL must lock to TCLK before it is ready for the
Initialization state. The system must then allow time for
Initialization before data transfer can begin.
NOISE MARGIN
The Deserializer noise margin is the amount of input jitter
(phase noise) that the Deserializer can tolerate and still
reliably recover data. Various environmental and systematic
factors include:
TRI-STATE
When the system drives the REN pin low, the Deserializer’s
outputs enter TRI-STATE. This will TRI-STATE the receiver
output pins (ROUT[0:17]) and RCLK. When the system
drives REN high, the Deserializer will return to the previous
state as long as all other control pins remain static (RP-
WDN).
Serializer: TCLK jitter, VCC noise (noise bandwidth and
out-of-band noise)
Media: ISI, VCM noise
Deserializer: VCC noise
For a graphical representation of noise margin, please see
Figure 17.
When the system drives the DEN pin low, the Serializer’s
LVDS outputs enter TRI-STATE. When the system drives the
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14
via on both ends of the capacitor. Connecting power or
ground pins to an external bypass capacitor will increase the
inductance of the path.
Application Information (Continued)
RECOVERING FROM LOCK LOSS
In the case where the Serializer loses lock during data
transmission, up to 5 cycles of data that were previously
received could be invalid. This is due to a delay in the lock
detection circuit. The lock detect circuit requires that invalid
clock information be received 2 times in a row to indicate
loss of lock. Since clock information has been lost, it is
possible that data was also lost during these cycles. If the
Deserializer LOCK pin goes low, data from at least the
previous 5 cycles should be resent upon regaining lock.
A small body size X7R chip capacitor, such as 0603, is
recommended for external bypass. Its small body size re-
duces the parasitic inductance of the capacitor. The user
must pay attention to the resonance frequency of these
external bypass capacitors, usually in the range of 20-30
MHz range. To provide effective bypassing, multiple capaci-
tors are often used to achieve low impedance between the
supply rails over the frequency of interest. At high frequency,
it is also a common practice to use two vias from power and
ground pins to the planes, reducing the impedance at high
frequency.
Lock can be regained at the Deserializer by causing the
Serializer to resend SYNC patterns as described above or
by random data locking which can take more time depending
upon the data patterns being received.
Some devices provide separate power and ground pins for
different portions of the circuit. This is done to isolate switch-
ing noise effects between different sections of the circuit.
Separate planes on the PCB are typically not required. Pin
Description tables typically provide guidance on which circuit
blocks are connected to which power pin pairs. In some
cases, an external filter many be used to provide clean
power to sensitive circuits such as PLLs.
INPUT FAILSAFE
In the event that the Deserializer is disconnected from the
Serializer, the failsafe circuitry is designed to reject a certain
amount of noise from being interpreted as data or clock. The
outputs will enter TRI-STATE and the Deserializer will lose
lock.
Use at least a four layer board with a power and ground
plane. Locate CMOS (TTL) signals away from the LVDS
lines to prevent coupling from the CMOS lines to the LVDS
lines. Closely-coupled differential lines of 100 Ohms are
typically recommended for LVDS interconnect. The closely-
coupled lines help to ensure that coupled noise will appear
as common-mode and thus is rejected by the receivers. The
tightly coupled lines will also radiate less.
HOT INSERTION
All of National’s LVDS devices are hot pluggable if you follow
a few rules. When inserting, ensure the Ground pin(s) makes
contact first, then the VCC pin(s), then the I/O pin(s). When
removing, the I/O pins should be unplugged first, then VCC,
then Ground.
Termination of the LVDS interconnect is required. For point-
to-point applications, termination should be located at the
load end. Nominal value is 100 Ohms to match the line’s
differential impedance. Place the resistor as close to the
receiver inputs as possible to minimize the resulting stub
between the termination resistor and receiver.
PCB LAYOUT AND POWER SYSTEM
CONSIDERATIONS
Circuit board layout and stack-up for the BLVDS devices
should be designed to provide low-noise power feed to the
device. Good layout practice will also separate high-
frequency or high-level inputs and outputs to minimize un-
wanted stray noise pickup, feedback and interference.
Power system performance may be greatly improved by
using thin dielectrics (2 to 4 mils) for power / ground sand-
wiches. This arrangement provides plane capacitance for
the PCB power system with low-inductance parasitics, which
has proven especially effective at high frequencies above
approximately 50MHz, and makes the value and placement
of external bypass capacitors less critical. External bypass
capacitors should include both RF ceramic and tantalum
electrolytic types. RF capacitors may use values in the range
of 0.01 uF to 0.1 uF. Tantalum capacitors may be in the 2.2
uF to 10 uF range. Voltage rating of the tantalum capacitors
should be at least 5X the power supply voltage being used.
Additional general guidance can be found in the LVDS Own-
er’s Manual - available in PDF format from the national web
site at: www.national.com/lvds
Specific guidance for this device is provided next.
DS92LV18 BLVDS SER/DES PAIR
General device specific guidance is given below. Exact guid-
ance can not be given as it is dictated by other board level
/system level criteria. This includes the density of the board,
power rails, power supply, and other integrated circuit power
supply needs.
DVDD = DIGITAL SECTION POWER SUPPLY
These pins supply the digital portion of the device as well as
the receiver output buffers. The Deserializer’s DVDD re-
quires more bypass to power the outputs under synchronous
switching conditions. The Serializer’s DVDD is less critical.
The receiver’s DVDD pins power 4 outputs from each DVDD
pin. An estimate of local capacitance required indicates a
minimum of 22nF is required. This is calculated by taking 4
times the maximum short current (4 X 70 = 280mA), multi-
plying by the rise time of the part (4ns), and dividing by the
maximum allowed droop in VDD (assume 50mV) yields
22.4nF. Rounding up to a standard value, 0.1uF is selected
for each DVDD pin.
It is a recommended practice to use two vias at each power
pin as well as at all RF bypass capacitor terminals. Dual vias
reduce the interconnect inductance by up to half, thereby
reducing interconnect inductance and extending the effec-
tive frequency range of the bypass components. Locate RF
capacitors as close as possible to the supply pins, and use
wide low impedance traces (not 50 Ohm traces). Surface
mount capacitors are recommended due to their smaller
parasitics. When using multiple capacitors per supply pin,
locate the smaller value closer to the pin. A large bulk
capacitor is recommend at the point of power entry. This is
typically in the 50uF to 100uF range and will smooth low
frequency switching noise. It is recommended to connect
power and ground pins directly to the power and ground
planes with bypass capacitors connected to the plane with
15
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capacitor is sufficient for these pins. If space is available, a
0.01uF capacitor may be used in parallel with the 0.1uF
capacitor for additional high frequency filtering.
Application Information (Continued)
PVDD = PLL SECTION POWER SUPPLY
The PVDD pin supplies the PLL circuit. Note that the
DS92LV18 has two separate PLL and supply pins. The
PLL(s) require clean power for the minimization of Jitter. A
supply noise frequency in the 300 kHz to 1 MHz range can
cause increased output jitter. Certain power supplies may
have switching frequencies or high harmonic content in this
range. If this is the case, filtering of this noise spectrum may
be required. A notch filter response is best to provide a stable
VDD, suppression of the noise band, and good high-
frequency response (clock fundamental). This may be ac-
complished with a pie filter (CRC or CLC). If employed, a
separate pie filter is recommended for each PLL to minimize
drop in potential due to the series resistance. The pie filter
should be located close to the PVDD power pin. Separate
power planes for the PVDD pins is typically not required.
GROUNDS
The AGND pin should be connected to the signal common in
the cable for the return path of any common-mode current.
Most of the LVDS current will be odd-mode and return within
the interconnect pair. A small amount of current may be
even-mode due to coupled noise and driver imbalances.
This current should return via a low impedance known path.
A solid ground plane is recommended for both DVDD, PVDD
or AVDD. Using a split plane may cause ground loops or a
difference in ground potential at various ground pins of the
device.
AVDD = LVDS SECTION POWER SUPPLY
The AVDD pins power the LVDS portion of the circuit. The
DS92LV18 has four AVDD pins. Due to the nature of the
design, current draw is not excessive on these pins. A 0.1uF
Truth Tables
Transmitter Truth Table
TPWDN (Pin 42)
DEN (Pin 19)
TX PLL Status (Internal)
LVDS Outputs (Pins 13 and 14)
L
H
H
H
X
L
X
X
Hi Z
Hi Z
H
H
Not Locked
Locked
Hi Z
Serialized Data with Embedded Clock
Receiver Truth Table
RPWDN (Pin 01) REN (Pin 02) RX PLL Status (Internal) ROUTn & RCLK (See Pin Diagram)
LOCK (Pin 63)
L
X
X
Hi Z
Hi Z
L = PLL Locked;
H
L
X
Hi Z
H = PLL Unlocked
H
H
H
H
Not Locked
Locked
H
H
L
Data & CLK Active
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16
Footprint Changes between the DS92LV16 and the DS92LV18
DS92LV16 vs. DS92LV18 Footprint Changes
Pin Number
DS92LV16
CONFIG1
CONFIG2
DVDD
DS92LV18
DIN17
3
18
62
80
DIN16
ROUT16
ROUT17
DGND
PCB Compatibility Between the DS92LV16 and DS92LV18
20031233
FIGURE 21.
17
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Pin Diagram
DS92LV18TVV
Top View
20031202
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18
Pin Descriptions
Pin #
Pin Name
I/O
Description
1
RPWDN
CMOS, I RPWDN = Low will put the Receiver in low power, stand-by, mode.
Note: The Receiver PLL will lose lock.(Note 10)
CMOS, I REN = Low will disable the Receiver outputs. Receiver PLL
remains locked. (See LOCK pin description)(Note 10)
CMOS, I Frequency reference clock input for the receiver.
Analog Voltage Supply
2
REN
4
REFCLK
AVDD
AGND
RIN+
5, 10, 11, 15
6,9,12,16
Analog Ground
7
8
LVDS, I Receiver LVDS True Input
RIN-
LVDS, I Receiver LVDS Inverting Input
13
14
17
DO+
LVDS, O Transmitter LVDS True Output
DO-
LVDS, O Transmitter LVDS Inverting Output
TCLK
CMOS, I Transmitter reference clock. Used to strobe data at the DIN Inputs
and to drive the transmitter PLL. See TCLK Timing Requirements.
CMOS, I DEN = Low will disable the Transmitter outputs. The transmitter
PLL will remain locked.(Note 10)
19
20
DEN
SYNC
CMOS, I SYNC = High will cause the transmitter to ignore the data inputs
and send SYNC patterns to provide a locking reference to
receiver(s). See Functional Description.(Note 10)
CMOS, I Transmitter data inputs.(Note 10)
3, 18,21, 22, 23, 24, 25,
26, 27, 28, 33, 34, 35,
36, 37, 38, 39, 40
29,32
DIN (0:17)
PGND
PVDD
DGND
PLL Ground.
30,31
PLL Voltage supply.
Digital Ground.
41, 44, 51, 52, 59, 60,
61, 68
42
TPWDN
CMOS, I TPWDN = Low will put the Transmitter in low power, stand-by
mode. Note: The transmitter PLL will lose lock.(Note 10)
Digital Voltage Supplies.
43, 50, 53, 58, 69
45, 46, 47, 48, 54, 55,
56, 57, 62, 64, 65, 66,
67, 70, 71, 72, 73, 80
49
DVDD
ROUT (0:17)
CMOS, O Receiver Outputs.
RCLK
LOCK
CMOS, O Recovered Clock. Parallel data rate clock recovered from
embedded clock. Used to strobe ROUT (0:17). LVCMOS Level
output.
63
CMOS, O LOCK indicates the status of the receiver PLL. LOCK = H -
receiver PLL is unlocked, LOCK = L - receiver PLL is locked.
PLL Grounds.
74,76
75,77
78
PGND
PVDD
PLL Voltage Supplies.
LINE_LE
CMOS, I LINE_LE = High enables the receiver loopback mode. Data
received at the RIN inputs is fed back through the DO
outputs.(Note 10)
79
LOCAL_LE
CMOS, I LOCAL_LE = High enables the transmitter loopback mode. Data
received at the DIN inputs is fed back through the ROUT
outputs.(Note 10)
Note 10: Input defaults to "low" state when left open due to an internal on-chip pull-down circuit.
19
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Physical Dimensions inches (millimeters) unless otherwise noted
Dimensions shown in millimeters only
Order Number DS92LV18TVV
NS Package Number VHG80A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and
whose failure to perform when properly used in
accordance with instructions for use provided in the
labeling, can be reasonably expected to result in a
significant injury to the user.
2. A critical component is any component of a life
support device or system whose failure to perform
can be reasonably expected to cause the failure of
the life support device or system, or to affect its
safety or effectiveness.
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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