DS78LS120 [NSC]
Dual Differential Line Receiver (Noise Filtering and Fail-Safe); 双路差动线路接收器（噪音过滤和故障保护）
| 型号： | DS78LS120 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual Differential Line Receiver (Noise Filtering and Fail-Safe) |
| 文件： | 总9页 (文件大小：609K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1999
DS78LS120
Dual Differential Line Receiver (Noise Filtering and
Fail-Safe)
Input specifications meet or exceed those of the popular
DS7820 line receiver.
General Description
The DS78LS120 is a high performance, dual differential, TTL
compatible line receiver for both balanced and unbalanced
digital data transmission. The inputs are compatible with
EIA, Federal and MIL standards.
Features
n Meets EIA standards RS232-C, RS422 and RS423,
Federal Standards 1020, 1030 and MIL-188-114
n Input voltage range of 15V (differential or
common-mode)
The line receiver will discriminate a 200 mV input signal
over a common-mode range of 10V and a 300 mV signal
over a range of 15V.
n Separate strobe input for each receiver
n 5k typical input impedance
n Optional 180Ω termination resistor
n 50mV input hysteresis
n 200mV input threshold
n Separate fail-safe mode
Circuit features include hysteresis and response control for
applications where controlled rise and fall times and/or high
frequency noise rejection are desirable. Threshold offset
control is provided for fail-safe detection, should the input be
open or short. Each receiver includes an optional 180Ω
terminating resistor and the output gate contains a logic
strobe for time discrimination. The DS78LS120 is specified
over a −55˚C to +125˚C temperature range.
Connection Diagram
Dual-In-Line-Package
00749901
Top View
see RETS Data Sheet.
Order Number DS78LS120J/883 or DS78LS120W/883
See NS Package Number J16A or W16A
© 2004 National Semiconductor Corporation
DS007499
www.national.com
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Lead Temperature (Soldering, 4 sec)
260˚C
Operating Conditions
Min
Max
5.5
Units
V
Supply Voltage
7V
Supply Voltage (VCC
)
4.5
−55
−15
Input Voltage
25V
7V
Temperature (TA)
+125
+15
˚C
Strobe Voltage
Common-Mode Voltage (VCM
)
V
Output Sink Current
Storage Temperature Range
Maximum Power Dissipation at 25˚C
(Note 1)
50 mA
−65˚C to +150˚C
1433 mV
Electrical Characteristics (Notes 3, 4)
Symbol
Parameter
Conditions
Min Typ Max Units
VTH
Differential Threshold Voltage
IOUT = −400 µA, VOUT ≥ 2.5V
−7V ≤ VCM ≤ 7V
−15 ≤ VCM ≤15V
−7V ≤ VCM ≤7V
0.06 0.2
0.06 0.3
−0.08 −0.2
−0.08 −0.3
V
V
V
V
VTL
Differential Threshold Voltage
IOUT = 4 mA, VOUT ≤ 0.5V
−15V ≤ VCM
≤
15V
VTH
VTL
RIN
RT
Differential Threshold Voltage
with Fail-Safe Offset = 5V
Input Resistance
IOUT = −400 µA, VOUT ≥ 2.5V
IOUT = 4 mA, VOUT ≤ 0.5V
−15V ≤ VCM ≤ 15V, 0V ≤ VCC ≤ 7V
TA = 25˚C
−7V ≤ VCM ≤ 7V
−7V ≤ VCM ≤ 7V
0.47 0.7
V
V
−0.2 −0.42
4
5
kΩ
Ω
Line Termination Resistance
Offset Control Resistance
Data Input Current (Unterminated)
100 180 300
RO
TA = 25˚C
42
56
2
70
kΩ
mA
IIND
VCM = 10V
3.1
VCM = 0V
0V ≤ VCC ≤ 7V
−7V ≤ VCM 7V
−7V ≤ VCM ≤ 7V
0
−0.5 mA
−3.1 mA
VCM = −10V
−2
0.1
VTHB
Input Balance
(Note 6)
IOUT = −400 µA, VOUT ≥ 2.5V,
RS = 500Ω
0.4
V
IOUT = 4 mA, VOUT ≤ 0.5V,
RS = 500Ω
−0.1 −0.4
V
VOH
VOL
ICC
Logical “1” Output Voltage
Logical “0” Output Voltage
Power Supply Current
IOUT = −400 µA, VDIFF = 1V, VCC = 4.5V
IOUT = 4 mA, VDIFF = −1V, VCC = 4.5V
2.5
3
V
0.35 0.5
V
VCC = 5.5V
VCM = 15V
VCM = −15V
10
10
1
16
16
mA
mA
µA
VDIFF = −0.5V, (Both Receivers)
VSTROBE = 5.5V, VDIFF = 3V
VSTROBE = 0V, VDIFF = −3V
VOL ≤ 0.5, IOUT = 4mA
IIN (1)
IIN (0)
VIH
Logical “1” Strobe Input Current
Logical “0” Strobe Input Current
Logical “1” Strobe Input Voltage
Logical “0” Strobe Input Voltage
Output Short-Circuit Current
100
−290 −400 µA
2.0 1.12
1.12 0.8
V
V
VIL
VOH ≥ 2.5V, IOUT, = −400 µA
IOS
VOUT = 0V, VCC = 5.5V, VSTROBE = 0V,(Note 5)
−30 −100 −170 mA
Note 1: Derate cavity package 9.6 mW/˚C above 25˚C.
Note 2: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. Except for “Operating Temperature Range”
they are not meant to imply that the devices should be operated at these limits. The table of “Electrical Characteristics” provides conditions for actual device
operation.
Note 3: Unless otherwise specified min/max limits apply across the −55˚C to +125˚C temperature range for the DS78LS120. All typical values are for T = 25˚C,
A
V
= 5V and V
= 0V.
CC
CM
Note 4: All currents into device pins shown as positive, out of device pins as negative, all voltages referenced to ground unless otherwise noted. All values shown
as max or min on absolute value basis.
Note 5: Only one output at a time should be shorted.
Note 6: Refer to EIA-RS422 for exact conditions.
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2
Switching Characteristics
VCC = 5V, TA = 25˚C
Symbol
tpd0(D)
Parameter
Conditions
Min
Typ
38
Max
60
Units
ns
Differential Input to “0” Output
Differential Input to “1” Output
Strobe Input to “0” Output
Strobe Input to “1” Output
tpd1(D)
Response Pin Open, CL = 15 pF, RL = 2 kΩ
38
60
ns
tpd0(S)
16
25
ns
tpd1(S)
12
25
ns
AC Test Circuit and Switching Time Waveforms
Differential and Strobe Input Signal
00749903
Includes probe and test fixture capacitance
00749904
Note: Optimum switching response is obtained by minimizing stray capacitance on Response Control pin (no external connection).
Application Hints
Balanced Data Transmission
00749905
3
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Application Hints (Continued)
Unbalanced Data Transmission
00749906
RESPONSE CONTROL AND HYSTERESIS
In unbalanced (RS-232/RS-423) applications it is recom-
mended that the rise time and fall time of the line driver be
controlled to reduce cross-talk. Elimination of switching
noise is accomplished in the DS78LS120 by the 50 mV of
hysteresis incorporated in the output gate. This eliminates
the oscillations which may appear in a line receiver due to
the input signal slowly varying about the threshold level for
extended periods of time.
High frequency noise which is superimposed on the input
signal which may exceed 50 mV can be reduced in ampli-
tude by filtering the device input. On the DS78LS120, a high
impedance response control pin in the input amplifier is
available to filter the input signal without affecting the termi-
nation impedance of the transmission line. Noise pulse width
rejection vs the value of the response control capacitor is
shown in Figure 1 and Figure 2. This combination of filters
followed by hysteresis will optimize performance in a worse
case noise environment.
00749907
Logic Level Translator
00749908
The DS78LS120 may be used as a level translator to inter-
face between 12V MOS, ECL, TTL and CMOS. To config-
1
ure, bias either input to a voltage equal to
⁄2 the voltage of
the input signal, and the other input to the driving gate.
LINE DRIVERS
Line drivers which will interface with the DS78LS120 are
listed below.
Balanced Drivers
00749909
DS26LS31: Quad RS-422 Line Driver, Dual CMOS
DS7830, DS8830: Dual TTL
FIGURE 1. Noise Pulse Width vs
Response Control Capacitor
DS7831, DS8831: Dual TRI-STATE TTL
DS7832, DS8832: Dual TRI-STATE TTL
DS1691A, DS3691: Quad RS-423/Dual RS-422 TTL
DS1692, DS3692: Quad RS-423/Dual TRI-STATE RS-422
TTL
DS3487: Quad TRI-STATE RS-422
Unbalanced Drivers
DS1488: Quad RS-232
DS75150: Dual RS-232
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4
mode if the transmission line is open or shorted. To facilitate
the detection of input opens or shorts, the DS78LS120 in-
corporates an input threshold voltage offset. This feature will
force the line receiver to a specific logic state if presence of
either fault is a condition.
Application Hints (Continued)
Given that the receiver input threshold is 200 mV, an input
signal greater than 200 mV insures the receiver will be in a
specific logic state. When the offset control input (pins 1 and
15) is connected to VCC = 5V, the input thresholds are offset
from 200 mV to 700 mV, referred to the non-inverting input,
or −200 mV to −700 mV, referred to the inverting input.
Therefore, if the input is open or shorted, the input will be
greater than the input threshold and the receiver will remain
in a specified logic state.
The input circuit of the receiver consists of a 5k resistor
terminated to ground through 120Ω on both inputs. This
network acts as an attenuator, and permits operation with
common-mode input voltages greater than 15V. The offset
control input is actually another input to the attenuator, but its
resistor value is 56k. The offset control input is connected to
the inverting input side of the attenuator, and the input
voltage to the amplifier is the sum of the inverting input plus
0.09 times the voltage on the offset control input. When the
offset control input is connected to 5V the input amplifier will
see VIN(INVERTING) +0.45V or VIN(INVERTING) +0.9V when the
control input is connected to 10V. The offset control input will
not significantly affect the differential performance of the
receiver over its common-mode operating range, and will not
change the input impedance balance of the receiver.
00749910
FIGURE 2.
TRANSMISSION LINE TERMINATION
On a transmission line which is electrically long, it is advis-
able to terminate the line in its characteristic impedance to
prevent signal reflection and its associated noise/cross-talk.
A 180Ω termination resistor is provided in the DS78LS120
line receiver. To use the termination resistor, connect pins 2
and 3 together and pins 13 and 14 together. The 180Ω
resistor provides a good compromise between line reflec-
tions, power dissipation in the driver, and IR drop in the
transmission line. If power dissipation and IR drop are still a
concern, a capacitor may be connected in series with the
resistor to minimize power loss.
It is recommended that the receiver be terminated (500Ω or
less) to insure it will detect an open circuit in the presence of
noise.
The offset control can be used to insure fail-safe operation
for unbalanced interface (RS-423) or for balanced interface
(RS-422) operation.
For unbalanced operation, the receiver would be in an inde-
terminate logic state if the offset control input was open.
Connecting the fail-safe offset pin to 5V, offsets the receiver
threshold to 0.45V. The output is forced to a logic zero state
if the input is open or shorted.
The value of the capacitor is recommended to be the line
length (time) divided by 3 times the resistor value. Example:
if the transmission line is 1,000 feet long, (approximately
1000 ns), and the termination resistor value is 180Ω, the
capacitor value should be 1852 pF. For additional application
details, refer to application notes AN-22 and AN-108.
FAIL-SAFE OPERATION
Communication systems require elements of a system to
detect the presence of signals in the transmission lines, and
it is desirable to have the system shut-down in a fail-safe
Unbalanced RS-423 and RS-232 Fail-Safe
00749911
5
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Application Hints (Continued)
00749912
Balanced RS-422 Fail-Safe
00749913
00749914
For balanced operation with inputs open or shorted, receiver
C will be in an indeterminate logic state. Receivers A and B
will be in a logic zero state allowing the NOR gate to detect
the open or short condition. The strobe will disable receivers
A and B and may therefore be used to sample the fail-safe
detector. Another method of fail-safe detection consists of
filtering the output of NOR gate D so it would not indicate a
fault condition when receiver inputs pass through the thresh-
old region, generating an output transient.
In a communications system, only the control signals are
required to detect input fault conditions. Advantages of a
balanced data transmission system over an unbalanced
transmission system are:
1. High noise immunity
2. High data ratio
3. Long line lengths
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6
Truth Table
(For Balanced Fail-Safe)
Input
Strobe
A-Out
B-Out
C-Out
D-Out
0
1
X
0
1
X
1
1
1
0
0
0
0
1
0
1
1
1
1
0
0
1
1
1
0
1
X
0
0
0
0
0
1
0
0
0
Schematic Diagram
00749902
7
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Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DS78LS120J/883
NS Package Number J16A
Ceramic Dual-In-Line Package (W)
Order Number DS78LS120W/883
NS Package Number W16A
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8
Notes
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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