DP8404D [NSC]
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDACs); DP8402A / DP8403 / DP8404 / DP8405 32位并行错误检测和校正电路( EDACS )型号: | DP8404D |
厂家: | National Semiconductor |
描述: | DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel Error Detection and Correction Circuits (EDACs) |
文件: | 总18页 (文件大小:320K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
PRELIMINARY
August 1989
DP8402A/DP8403/DP8404/DP8405 32-Bit Parallel
Error Detection and Correction Circuits (EDAC’s)
General Description
The DP8402A, DP8403, DP8404 and DP8405 devices are
32-bit parallel error detection and correction circuits
(EDACs) in 52-pin DP8402A and DP8403 or 48-pin DP8404
and DP8405 600-mil packages. The EDACs use a modified
Hamming code to generate a 7-bit check word from a 32-bit
data word. This check word is stored along with the data
word during the memory write cycle. During the memory
read cycle, the 39-bit words from memory are processed by
the EDACs to determine if errors have occurred in memory.
condition of all lows or all highs from memory will be detect-
ed. Otherwise, errors in three or more bits of the 39-bit word
are beyond the capabilities of these devices to detect.
Read-modify-write (byte-control) operations can be per-
formed with the DP8402A and DP8403 EDACs by using out-
put latch enable, LEDBO, and the individual OEB0 thru
OEB3 byte control pins.
Diagnostics are performed on the EDACs by controls and
internal paths that allow the user to read the contents of the
DB and CB input latches. These will determine if the failure
occurred in memory or in the EDAC.
Single-bit errors in the 32-bit data word are flagged and cor-
rected.
Single-bit errors in the 7-bit check word are flagged, and the
CPU sends the EDAC through the correction cycle even
though the 32-bit data word is not in error. The correction
cycle will simply pass along the original 32-bit data word in
this case and produce error syndrome bits to pinpoint the
error-generating location.
Features
Y
Detects and corrects single-bit errors
Y
Detects and flags double-bit errors
Y
Built-in diagnostic capability
Y
Fast write and read cycle processing times
Double bit errors are flagged but not corrected. These er-
rors may occur in any two bits of the 39-bit word from mem-
ory (two errors in the 32-bit data word, two errors in the 7-bit
check word, or one error in each word). The gross-error
Y
Byte-write capability . . . DP8402A and DP8403
Y
Fully pin and function compatible with TI’s
SN74ALS632A thru SN74ALS635 series
System Environment
TL/F/8535–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corp.
C
1995 National Semiconductor Corporation
TL/F/8535
RRD-B30M105/Printed in U. S. A.
Simplified Functional Block and Connection Diagrams
TL/F/8535–2
Device
Package
Byte-Write
Output
DP8402A
DP8403
DP8404
DP8405
52-pin
52-pin
48-pin
48-pin
yes
yes
no
TRI-STATE
É
Open-Collector
TRI-STATE
no
Open-Collector
Dual-In-Line Packages
Plastic Chip Carrier
TL/F/8535–11
Top View
Order Number DP8402AV
See NS Package Number V68A
TL/F/8535–3
TL/F/8535–10
Top View
Top View
Order Number DP8402AD,
DP8403D, DP8404D or DP8405D
See NS Package Number D48A or D52A
2
Mode Definitions
PCC Pin Definitions DP8402A
MODE PIN NAME DESCRIPTION
S1 S0 MODE
WRITE
pin 1
V
pin 35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
OECB
CB3
CC
OPERATION
Input dataword and output
checkword
2
LEDBO
MERR
ERR
DB0
DB1
DB2
NC
0
1
L
L
L
3
CB2
4
CB1
H
DIAGNOSTICS Input various data words
against latched
5
CB0
6
DB16
DB17
NC
checkword/output valid
error flags.
7
8
2
3
H
H
L
READ & FLAG Input dataword and output
error flags
CORRECT
9
NC
NC
H
Latched input data and
checkword/output
corrected data and
syndrome code
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
NC
DB18
DB19
DB20
DB21
OEB2
DB22
DB23
GND
GND
DB24
DB25
OEB3
DB26
DB27
DB28
NC
DB3
DB4
DB5
OEBO
DB6
DB7
GND
GND
DB8
DB9
OEB1
DB10
DB11
DB12
DB13
DB14
NC
Pin Definitions
S0, S1
Control of EDAC mode, see preceding
Mode Definitions
DB0 thru DB31 I/O port for 32 bit dataword.
CB0 thru CB6 I/O port for 7 bit checkword. Also output
port for the syndrome error code during
error correction mode.
OEB0 thru
OEB3
(DP8402A,
DP8403)
Dataword output buffer enable. When high,
output buffers are at TRI-STATE. Each pin
controls 8 I/O ports. OEB0 controls DB0
thru DB7, OEB1 controls DB8 thru DB15,
OEB2 controls DB16 thru DB23 and OEB3
controls DB24 thru DB31.
NC
LEDBO
(DP8402A,
DP8403)
OEDB
(DP8404,
DP8405)
OECB
Data word output Latch enable. When high
it inhibits input to the Latch. Operates on all
32 bits of the dataword.
TRI-STATE control for the data I/O port.
When high output buffers are at
TRI-STATE.
Checkword output buffer enable. When
high the output buffers are in TRI-STATE
mode.
NC
NC
NC
NC
DB29
DB30
DB31
S0
DB15
NC
CB6
CB5
CB4
S1
V
CC
ERR
Single error output flag, a low indicates at
least a single bit error.
MERR
Multiple error output flag, a low indicates
two or more errors present.
TABLE I. Write Control Function
DB Control
OEBn or
OEDB
DB Output Latch
DP8402A, DP8403
LEDBO
CB
Memory
Cycle
EDAC
Control
S1 S0
Error Flags
Data I/O
Check I/O
Control
OECB
Function
ERR MERR
Generate
Output
Write
L
L
Input
H
X
L
H
H
²
check word
check bits
²
See Table II for details on check bit generation.
Memory Write Cycle Details
During a memory write cycle, the check bits (CB0 thru CB6)
are generated internally in the EDAC by seven 16-input pari-
ty generators using the 32-bit data word as defined in Table
2. These seven check bits are stored in memory along with
the original 32-bit data word. This 32-bit word will later be
used in the memory read cycle for error detection and cor-
rection.
3
TABLE II. Parity Algorithm
32-Bit Data Word
Check Word
Bit
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
CB0
CB1
CB2
CB3
CB4
CB5
CB6
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
The seven check bits are parity bits derived from the matrix of data bits as indicated by ‘‘X’’ for each bit.
Check bits 0, 1, 2 are odd parity or the exclusive NORing of the ‘‘X’’ed bits for the particular check bit. Check bits 3, 4, 5, 6 are even parity or the exclusive ORing of
the ‘‘X’’ed bits for the particular check bit.
Memory Read Cycle (Error
Detection & Correction Details)
During a memory read cycle, the 7-bit check word is re-
trieved along with the actual data. In order to be able to
determine whether the data from the memory is acceptable
to use as presented on the bus, the error flags must be
tested to determine if they are at the high level.
next two cases of single-bit errors give a high on MERR and
a low on ERR, which is the signal for a correctable error,
and the EDAC should be sent through the correction cycle.
The last three cases of double-bit errors will cause the
EDAC to signal lows on both ERR and MERR, which is the
interrupt indication for the CPU.
The first case in Table III represents the normal, no-error
conditions. The EDAC presents highs on both flags. The
TABLE III. Error Function
Total Number of Errors
Error Flags
Data Correction
ERR MERR
32-Bit Data Word 7-Bit Check Word
0
1
0
1
2
0
0
0
1
1
0
2
H
L
L
L
L
L
H
H
H
L
Not applicable
Correction
Correction
Interrupt
Interrupt
Interrupt
L
L
The DP8402 check bit syndrome matrix can be seen in TA-
BLE II. The horizontal rows of this matrix generate the
check bits by selecting different combinations of data bits,
indicated by ‘‘X’’s in the matrix, and generating parity from
them. For instance, parity check bit ‘‘0’’ is generated by
EXCLUSIVE NORing the following data bits together; 31,
29, 28, 26, 21, 19, 18, 17, 14, 11, 9, 8, 7, 6, 4, and 0. For
example, the data word ‘‘00000001H’’ would generate the
During a READ operation (mode 2, error detection) the data
and check bits that were stored in memory, now possibly in
error, are input through the data and check bit I/O ports.
New check bits are internally generated from the data word.
These new check bits are then compared, by an EXCLU-
SIVE NOR operation, with the original check bits that were
stored in memory. The EXCLUSIVE NOR of the original
check bits, that were stored in memory, with the new check
bits is called the syndrome word. If the original check bits
are the same as the new check bits, a no error condition,
then a syndrome word of all ones is produced and both
error flags (ERR and MERR) will be high. The DP8402 ma-
trix encodes errors as follows:
e
and check bits 3, 4, 5, 6 are even parity).
check bits CB6–0
48H (Check bits 0, 1, 2 are odd parity
During a WRITE operation (mode 0) the data enters the
DP8402 and check bits are generated at the check bit in-
put/output port. Both the data word and the check bits are
then written to memory.
TABLE IV. Read, Flag, and Correct Function
DB Control
OEBn or
OEDB
DB Output Latch CB
DP8402A, DP8403 Check I/O Control
Memory
Cycle
EDAC
Function
Control
S1 S0
Error Flags
ERR MERR
Data I/O
LEDBO
OECB
²
²
Read
Read
Read & flag
H
H
L
Input
H
X
Input
H
Enabled
Enabled
Latch input
data and check
bits
Input
data
latched
Input
check word
latched
H
H
L
H
L
Output
corrected data
& syndrome bits
Output
corrected
data word
Output
syndrome
²
Read
H
H
L
X
Enabled
³
bits
²
³
See Table III for error description.
See Table V for error location.
4
Memory Read Cycle (Error Detection & Correction Details) (Continued)
1) Single data bit errors cause 3 or 5 bits in the syndrome
word to go low. The columns of the check bit syndrome
matrix (TABLE II) are the syndrome words for all single bit
data errors in the 32 bit word (also see TABLE V). The
data bit in error corresponds to the column in the check
bit syndrome matrix that matches the syndrome word.
For instance, the syndrome word indicating that data bit
2) A single check bit error will cause that particular check bit
to go low in the syndrome word.
3) A double bit error will cause an even number of bits in the
syndrome word to go low. The syndrome word will then
be the EXCLUSIVE NOR of the two individual syndrome
words corresponding to the 2 bits in error. The two-bit
error is not correctable since the parity tree can only
identify single bit errors.
e
31 is in error would be (CB6-CB0)
column for data bit 31 in TABLE II, or see TABLE V.
‘‘0001010’’, see the
If any of the bits in the syndrome word are low the ‘‘ERR’’
flag goes low. The ‘‘MERR’’ (dual error) flag goes low during
any double bit error conditions. (See Table III).
e
e
1) the syndrome word is
During mode 3 (S0
S1
decoded, during single data bit errors, and used to invert
the bit in error thus correcting the data word. The correct-
ed word is made available on the data I/O port (DB0 thru
DB31), the check word I/O port (CB0 thru CB6) presents
the 7-bit syndrome error code. This syndrome error code
can be used to locate the bad memory chip.
Three or more simultaneous bit errors can cause the EDAC
to believe that no error, a correctable error, or an uncorrect-
able error has occurred and will produce erroneous results
in all three cases. It should be noted that the gross-error
conditions of all lows and all highs will be detected.
TABLE V. Syndrome Decoding
Syndrome Bits
Syndrome Bits
Syndrome Bits
Syndrome Bits
Error
Error
Error
Error
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
6
5
4
3
2
1
0
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
unc
2-bit
2-bit
unc
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
2-bit
unc
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
2-bit
unc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
L
unc
2-bit
2-bit
DB23
H
H
H
H
DB7
2-bit
H
H
unc
H
H
H
H
H
2-bit
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
2-bit
unc
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
DB6
2-bit
2-bit
DB5
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
unc
2-bit
2-bit
unc
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
H
L
2-bit
DB22
DB21
2-bit
H
H
unc
H
H
H
H
H
H
H
2-bit
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
L
2-bit
unc
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
L
DB4
2-bit
2-bit
DB3
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
L
unc
2-bit
2-bit
DB15
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
H
L
2-bit
DB20
DB19
2-bit
H
H
DB31
2-bit
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
unc
2-bit
2-bit
DB30
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
2-bit
DB2
unc
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
2-bit
unc
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
H
L
DB18
2-bit
2-bit
CB4
H
H
H
H
H
H
DB14
2-bit
H
H
H
H
2-bit
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
2-bit
unc
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
DB0
2-bit
2-bit
unc
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
unc
2-bit
2-bit
DB13
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
H
L
2-bit
DB16
unc
H
H
DB29
2-bit
H
H
H
H
H
H
H
H
H
H
2-bit
L
L
L
L
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
DB28
2-bit
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
2-bit
DB1
unc
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
2-bit
DB12
DB11
2-bit
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
H
H
H
H
L
L
L
H
L
DB17
2-bit
2-bit
CB3
H
H
2-bit
H
H
H
H
H
H
H
DB27
H
2-bit
H
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
DB26
2-bit
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
2-bit
unc
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
2-bit
DB10
DB9
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
L
L
L
L
H
L
unc
2-bit
2-bit
CB2
H
H
2-bit
H
H
unc
H
H
H
H
H
DB25
H
2-bit
H
2-bit
H
L
L
L
L
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
2-bit
DB24
unc
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
unc
2-bit
2-bit
CB6
H
H
H
H
L
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
DB8
2-bit
2-bit
CB5
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
L
H
L
2-bit
CB1
CB0
none
H
H
H
H
H
H
H
H
H
2-bit
H
H
H
e
e
CB X
DB Y
2-bit
error in check bit X
error in data bit Y
double-bit error
e
e
unc
uncorrectable multibit error
5
TABLE VI. Read-Modify-Write Function
DB OUTPUT
LATCH
MEMORY
CYCLE
CONTROL
CB
ERROR FLAG
ERR MERR
²
²
EDAC FUNCTION
BYTEn
OEBn
CHECK I/O
S1
S0
LEDBO
CONTROL
Read
Read & Flag
H
L
Input
H
X
Input
H
H
H
L
Enabled
Input
data
Input
check word
latched
Latch input data
& check bits
Read
H
H
H
H
H
H
L
Enabled
latched
Output
data
Hi-Z
Latch corrected
data word into
output latch
Output
Syndrome
bits
Read
H
Enabled
word
latched
Input
Modify appropriate
byte or bytes &
generate new
check word
modified
BYTE0
H
L
Modify
/write
Output
L
L
H
L
H
H
check word
Ouput
unchanged
BYTE0
²
OEB0 controls DB –DB (BYTE0), OEB1 controls DB –DB (BYTE1), OEB2 controls DB16–DB23 (BYTE2), OEB3 controls DB24–DB31 (BYTE3).
15
0
7
8
Read-Modify-Write (Byte Control)
Operations
The DP8402A and DP8403 devices are capable of byte-
write operations. The 39-bit word from memory must first be
latched into the DB and CB input latches. This is easily ac-
Diagnostic Operations
The DP8402A thru DP8405 are capable of diagnostics that
allow the user to determine whether the EDAC or the mem-
ory is failing. The diagnostic function tables will help the
user to see the possibilities for diagnostic control.
e
e
H), the checkword is
In the diagnostic mode (S1
L, S0
e
H, S0 H). The
complished by switching from the read and flag mode (S1
e
latched into the input latch while the data input remains
transparent. This lets the user apply various data words
against a fixed known checkword. If the user applies a diag-
nostic data word with an error in any bit location, the ERR
flag should be low. If a diagnostic data word with two errors
in any bit location is applied, the MERR flag should be low.
After the checkword is latched into the input latch, it can be
verified by taking OECB low. This outputs the latched
checkword. With the DP8402A and DP8403, the diagnostic
data word can be latched into the output data latch and
verified. It should be noted that the DP8404 and DP8405 do
not have this pass-through capability because they do not
contain an output data latch. By changing from the diagnos-
e
e
H, SO
L) to the latch input mode (S1
EDAC will then make any corrections, if necessary, to the
data word and place it at the input of the output data latch.
This data word must then be latched into the output data
latch by taking LEDBO from a low to a high.
Byte control can now be employed on the data word
through the OEB0 through OEB3 controls. OEB0 controls
DB0–DB7 (byte 0), OEB1 controls DB8–DB15 (byte 1),
OEB2 controls DB16–DB23 (byte 2), and OEB3 controls
DB24–DB31 (byte 3). Placing a high on the byte control will
disable the output and the user can modify the byte. If a low
is placed on the byte control, then the original byte is al-
lowed to pass onto the data bus unchanged. If the original
data word is altered through byte control, a new check word
must be generated before it is written back into memory.
This is easily accomplished by taking control S1 and S0 low.
Table VI lists the read-modify-write functions.
e
e
e
H,
H), the user can verify that the EDAC will correct the
tic mode (S1
L, S0
H) to the correction mode (S1
e
S0
diagnostic data word. Also, the syndrome bits can be pro-
duced to verify that the EDAC pinpoints the error location.
Table VII DP8402A and DP8403 and Table VIII DP8404 and
DP8405 list the diagnostic functions.
6
TABLE VII. DP8402A, DP8403 Diagnostic Function
DB BYTE DB OUTPUT
CB
ERROR FLAGS
CONTROL
S1 S0
CONTROL
OEBn
LATCH
LEDBO
CHECK I/O
CONTROL
OECB
EDAC FUNCTION
DATA I/O
ERR
MERR
Input correct
data word
Input correct
check bits
Read & flag
H
L
H
H
X
L
H
H
H
H
Latch input check
word while data
input latch remains
transparent
Input
Input
check bits
latched
L
H
diagnostic
Enabled
²
data word
Latch diagnostic
data word into
output latch
Input
Output latched
check bits
L
L
H
H
diagnostic
H
H
H
H
Enabled
Enabled
²
data word
Hi-Z
H
Input
Output
syndrome
bits
Latch diagnostic
data word into
input latch
H
diagnostic
data word
latched
L
H
L
Hi-Z
Output
syndrome
bits
Output diagnostic
data word &
Output
H
H
H
H
diagnostic
data word
L
L
H
L
Enabled
Enabled
syndrome bits
Hi-Z
H
L
Output corrected
diagnostic data
word & output
syndrome bits
Output
Output
syndrome
bits
corrected
diagnostic
data word
Hi-Z
H
²
Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in
two bit locations.
TABLE VIII. DP8404, DP8405 Diagnostic Function
DB CONTROL
CONTROL
DB CONTROL
OECB
ERROR FLAGS
EDAC FUNCTION
DATA I/O
CHECK I/O
S1
S0
OEDB
ERR
MERR
Input correct
data word
Input correct
check bits
Read & flag
H
L
H
H
H
H
Latch input check
bits while data
input latch remains
transparent
Input
Input
L
L
H
H
H
diagnostic
H
H
H
check bits
latched
H
Enabled
²
data word
Input
Output input
check bits
Output input
check bits
diagnostic
L
Enabled
Enabled
²
data word
Input
Output
Latch diagnostic
L
diagnostic
data word
latched
syndrome bits
data into
input latch
H
Hi-Z
H
Output corrected
diagnostic
Output corrected
diagnostic
Output
L
H
H
L
syndrome bits
Enabled
data word
data word
Hi-Z
H
²
Diagnostic data is a data word with an error in one bit location except when testing the MERR error flag. In this case, the diagnostic data word will contain errors in
two bit locations.
7
DP8402A, DP8403 Logic Diagram (Positive Logic)
TL/F/8535–4
8
DP8404, DP8405 Logic Diagram (Positive Logic)
TL/F/8535–5
9
Absolute Maximum Ratings
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Over Operating Free-Air Temperature Range (unless otherwise noted)
b a
Operating Free-Air Temperature: Military 55 C to 125 C
Supply Voltage, V (See Note 1)
CC
7V
§
§
a
Commercial 0 to 70 C
Input Voltage: CB and DB
All Others
5.5V
7V
§
65 C to 150 C
§
§
b
a
Storage Temperature Range
§
Recommended Operating Conditions
Military
Commercial
Symbol
Parameter
Conditions
Units
Min Typ Max Min Typ Max
V
CC
V
IH
V
IL
Supply Voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
High-Level Input Voltage
Low-Level Input Voltage
0.8
0.8
b
b
ERR Or MERR
0.4
0.4
2.6
I
I
High-Level Output Current
mA
OH
OL
b
b
DB Or CB DP8402A, DP8404
ERR Or MERR
1
4
8
Low-Level Output Current
Pulse Duration
mA
ns
DB or CB
12
24
t
LEDBO Low
25
15
45
0
25
10
45
0
w
(1) Data And Check Word Before S0
e
u
(S1
H)
e
²
(2) SO High Before LEDBO (S1
H)
u
(3) LEDBO High Before The Earlier
²
of S0 or S1
v v
t
Setup Time
ns
su
e
(4) LEDBO High Before S1 (S0
H)
0
0
u
(5) Diagnostic Data Word Before S1
u
15
10
e
(S0
H)
(6) Diagnostic Check Word Before
15
10
The Later Of S1 or S0
v u
(7) Diagnostic Data Word Before
e
H)
25
35
20
20
20
20
30
15
15
15
e
³
LEDBO (S1
L and S0
u
(8) Read-Mode, S0 Low And S1 High
(9) Data And Check Word After
e
S0 (S1
H)
u
(10) Data Word After S1 (S0
e
H)
u
(11) Check Word After The Later
t
t
Hold Time
ns
ns
h
of S1 or S0
v u
(12) Diagnostic Data Word After
e
H)
0
0
e
³
LEDBO (S1
u
L And S0
Correction Time (seeFigure 1)*
65
58
0
corr
b
T
Operating Free-Air Temperature
55
125
70
C
§
A
*This specification may be interpreted as the maximum delay to guarantee valid corrected data at the output and includes the t setup delay.
su
²
These times ensure that corrected data is saved in the output data latch.
³
These times ensure that the diagnostic data word is saved in the output data latch.
10
DP8402A, DP8404 Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
Military
Commercial
Symbol
Parameter
Test Conditions
Units
²
²
Min
Typ
Max
Min
Typ
Max
e
e
e
e
e
e
e
e
e
e
e b
4.5V, I
I
b
b
1.5
V
V
V
V
V
V
V
V
V
V
V
18 mA
e b
1.5
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
CC
b
b
2
All outputs
DB or CB
4.5V to 5.5V, I
OH
0.4 mA
V
2
V
CC
CC
e b
e b
V
OH
4.5V, I
4.5V, I
4.5V, I
4.5V, I
4.5V, I
4.5V, I
1 mA
2.6 mA
2.4
3.3
V
OH
OH
OL
OL
OL
OL
2.4
3.2
e
e
e
e
4 mA
0.25
0.25
0.4
0.25
0.35
0.25
0.35
0.4
ERR or MERR
DB or CB
8 mA
0.5
0.4
0.5
0.1
0.1
20
V
OL
V
12 mA
24 mA
0.4
e
S0 or S1
All others
S0 or S1
5.5V, V
7V
0.1
0.1
20
I
I
I
I
I
mA
mA
mA
I
e
5.5V, V
5.5V
e
e
e
V
V
5.5V, V
2.7V
IH
IL
CC
CC
I
³
³
All others
S0 or S1
All others
20
20
b
b
0.4
0.1
0.4
0.1
e
5.5V, V
5.5V, V
0.4V
I
b
b
õ
e
e
e
O
b
b
b
b
112
I
I
V
V
2.25V
30
112
30
mA
mA
O
CC
5.5V, (See Note 1)
150
250
150
250
CC
CC
DP8403, DP8405 Electrical Characteristics
Over Recommended Operating Free-Air Temperature Range (unless otherwise noted)
Military
Commercial
Symbol
Parameter
Test Conditions
Units
²
²
Min
Typ
Max
Min
Typ
Max
e
e
e
e
e
e
e
e
e
e b
4.5V, I
I
b
b
1.5
V
V
V
V
V
V
V
V
V
V
V
18 mA
e b
1.5
V
V
IK
CC
CC
CC
CC
CC
CC
CC
CC
CC
b
b
2
ERR or MERR
DB or CB
4.5V to 5.5V, I
OH
0.4 mA
V
2
V
CC
OH
CC
e
I
4.5V, V
OH
5.5V
0.1
0.1
mA
OH
e
4.5V, I
4.5V, I
4.5V, I
4.5V, I
4 mA
0.25
0.25
0.4
0.25
0.35
0.25
0.35
0.4
0.5
0.4
0.5
OL
OL
OL
OL
ERR or MERR
DB or CB
e
e
e
8 mA
V
OL
V
12 mA
24 mA
0.4
e
7V
S0 or S1
All others
S0 or S1
5.5V, V
I
I
I
I
I
mA
mA
mA
I
e
5.5V, V
5.5V
e
e
V
V
5.5V, V
2.7V
IH
IL
CC
I
³
³
All others
S0 or S1
All others
e
e
e
5.5V, V
5.5V, V
0.4V
CC
I
õ
e
O
b
b
b
b
112
I
I
ERR or MERR
V
V
2.25V
30
112
30
mA
mA
O
CC
e
e
5.5V, (See Note 1)
150
150
CC
CC
e
a
²
³
All typical values are at V
CC
5V, T
25 C.
§
A
For I/O ports (Q through Q ), the parameters I and I include the off-state output current.
IH IL
A
H
õ
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, I
.
OS
Note 1: I
CC
is measured with S0 and S1 at 4.5V and all CB and DB pins grounded.
11
DP8402A Switching Characteristics
e
e
e
50 pF, T Min to Max (unless otherwise noted)
A
V
CC
4.5V to 5.5V, C
L
Military
Min
Commercial
From
To
Symbol
Test Conditions
Units
ns
(Input)
(Output)
Max
43
43
67
67
60
60
35
60
30
30
30
30
Min
10
10
15
15
10
10
7
Max
40
40
55
55
48
48
30
50
25
25
25
25
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
DB and CB
DB
ERR
ERR
MERR
MERR
CB
S1
S1
S1
S1
R1
S1
S1
S0
S0
S0
S0
S0
H, S0
L, S0
H, S0
L, S0
L, R
H, R
L, R
H, R
500X
500X
500X
500X
10
10
15
15
10
10
7
L
L
L
L
t
t
pd
DB and CB
DB
ns
pd
e
t
pd
t
pd
t
pd
t
pd
t
en
t
dis
t
en
t
dis
S0 and S1
v
DB
R2
500X
ns
ns
ns
ns
ns
ns
ns
ns
v
e
e
e
e
e
e
e
e
e
e
CB
L, S0
X, S0
H, R1
H, S1
H, S1
H, S1
H, S1
L, R1
H, R1
R2
R2
500X
500X
e
LEDB0
S1
DB
v
u
e
CB
R2
500X
10
2
10
2
e
e
e
e
e
e
e
e
OECB
CB
X, R1
X, R1
X, R1
X, R1
R2
R2
R2
R2
500X
500X
500X
500X
v
OECB
CB
2
2
u
OEB0 thru OEB3
OEB0 thru OEB3
DB
2
2
v
u
DB
2
2
DP8403 Switching Characteristics
e
e
e
50 pF, T Min to Max (unless otherwise noted)
A
V
CC
4.5V to 5.5V, C
L
Military
Commercial
From
To
Test Conditions
Units
Symbol
(Input)
(Output)
²
²
Min Typ
Max Min Typ
Max
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
DB and CB
DB
ERR
ERR
S1
S1
S1
S1
H, S0
L, S0
H, S0
L, S0
680X
L, S0
X, S0
L, R
H, R
L, R
H, R
500X
500X
500X
500X
26
26
40
40
40
40
26
40
24
24
24
24
26
26
40
40
40
40
26
40
24
24
24
24
L
L
L
L
t
ns
pd
pd
t
DB and CB
MERR
ns
t
t
t
t
t
t
t
t
S0 and S1
v
DB
CB
CB
DB
CB
CB
CB
DB
DB
R
L
ns
ns
ns
ns
ns
ns
ns
ns
v
pd
e
e
e
e
e
e
e
e
e
S1
S1
S0
S1
S1
S1
S1
L, R
680X
680X
pd
L
LEDB0
S1
H, R
L
v
u
pd
H, R
L
680X
pd
e
e
e
e
OECB
X, S0
X, S0
X, S0
X, S0
H, R
L
680X
680X
680X
680X
u
PLH
PHL
PLH
PHL
OECB
H, R
L
v
OEB0 thru OEB3
H, R
L
u
v
5V, T
OEB0 thru OEB3
H, R
L
e
e a
25 C.
²
All typical values are at V
§
CC
A
12
e
e
e
50 pF, T
A
DP8404 Switching Characteristics, V
4.5V to 5.5V, C
Min to Max
Commercial
CC
L
Military
From
To
Symbol
Test Conditions
Units
ns
(Input)
(Output)
²
²
Min Typ
Max Min Typ
Max
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
S1
S1
S1
S1
R1
S1
S0
S1
S1
S1
S1
H, S0
L, S0
H, S0
L, S0
L, R
H, R
L, R
H, R
500X
500X
500X
500X
26
26
40
40
35
35
35
18
18
18
18
26
26
40
40
35
35
35
18
18
18
18
L
L
L
L
t
t
DB and CB
ERR
pd
pd
DB and CB
MERR
ns
e
t
pd
t
pd
t
pd
t
en
t
dis
t
en
t
dis
S0 and S1
v
DB
CB
CB
CB
CB
CB
DB
DB
R2
500X
ns
ns
ns
ns
ns
ns
ns
v
e
e
e
e
e
e
e
e
R2 500X
L, S0
H, R1
X, S0
X, S0
X, S0
X, S0
L, R1
e
S1
R2
500X
u
e
e
e
e
e
e
e
e
OECB
OECB
OECB
OECB
H, R1
H, R1
H, R1
H, R1
R2
R2
R2
R2
500X
500X
500X
500X
v
u
v
u
e
e
e
DP8405 Switching Characteristics, V
4.5V to 5.5V, C
50 pF, T
Min to Max
CC
L
A
Military
Commercial
From
To
Test Conditions
Units
ns
Symbol
(Input)
(Output)
²
²
Min
500X
Typ
26
26
40
40
40
40
40
24
24
24
24
Max
Min
Typ
26
26
40
40
40
40
40
24
24
24
24
Max
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
e
DB and CB
DB
ERR
ERR
S1
S1
S1
S1
H, S0
L, S0
H, S0
L, S0
680X
L, S0
L, R
H, R
L, R
H, R
L
L
L
L
t
t
pd
500X
500X
DB and CB
MERR
ns
pd
500X
t
t
t
t
t
t
t
S0 and S1
v
CB
CB
DB
CB
CB
DB
DB
R
L
ns
ns
ns
ns
ns
ns
ns
v
pd
e
e
e
e
e
e
e
DB
S1
S1
S0
S1
S1
S1
S1
L, R
680X
pd
L
H, R
L
680X
u
pd
e
e
e
e
OECB
OECB
OEDB
OEDB
X, S0
X, S0
X, S0
X, S0
H, R
L
500X
680X
680X
680X
u
v
u
v
PLH
PHL
PLH
PHL
H, R
L
H, R
L
H, R
L
e
e a
25 C.
²
All typical values are at V
5V, T
§
CC
A
13
Switching Waveforms
TL/F/8535–6
FIGURE 1. Read, Flag, and Correct Mode
TL/F/8535–7
FIGURE 2. Read, Correct Modify Mode
14
Switching Waveforms (Continued)
TL/F/8535–8
FIGURE 3. Diagnostic Mode
15
DP8402A Interfaced to the DP8418/19/28/29 System Diagram
TL/F/8535–9
16
DP8402A Interfaced to the DP8420A/21A/22A System Diagram
Tl/F/8535–12
Physical Dimensions inches (millimeters)
Hermetic Dual-In-Line (D)
Order Number DP8402AD or DP8403D
NS Package Number D52A
17
Physical Dimensions inches (millimeters) (Continued)
Ý
Lit. 103062
Plastic Chip Carrier (V)
Order Number DP8402AV
NS Package Number V68A
48 Lead Hermetic DIP (D)
Order Number DP8404D or DP8405D
NS Package Number D48A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
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Japan Ltd.
a
1111 West Bardin Road
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Tel: 1(800) 272-9959
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