DM74180 [NSC]
9-Bit Parity Generators/Checkers; 9位奇偶发生器/跳棋
| 型号： | DM74180 |
| 厂家： | 
National Semiconductor |
| 描述： | 9-Bit Parity Generators/Checkers |
| 文件： | 总6页 (文件大小：108K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
DM54180/DM74180 9-Bit Parity Generators/Checkers
General Description
These universal 9-bit (8 data bits plus 1 parity bit) parity
generators/checkers feature odd/even outputs and control
inputs to facilitate operation in either odd or even parity ap-
plications. Depending on whether even or odd parity is be-
ing generated or checked, the even or odd input can be
utilized as the parity or 9th-bit input. The word-length capa-
bility is easily expanded by cascading.
Input buffers are provided so that each data input repre-
sents only one normalized series 54/74 load. A full fan-out
to 10 normalized series 54/74 loads is available from each
of the outputs at a low logic level. A fan-out to 20 normal-
ized loads is provided at a high logic level to facilitate the
connection of unused inputs to used inputs.
Connection Diagram
Dual-In-Line Package
TL/F/6559–1
Order Number DM54180J, DM54180W or DM74180N
See NS Package Number J14A, N14A or W14B
Function Table
Inputs
Outputs
R of H’s at
R
R
Even
Odd
A thru H
Even
Odd
Even
Odd
Even
Odd
X
H
L
H
L
L
H
H
L
H
L
L
H
L
L
H
H
L
H
H
L
X
L
L
H
H
e
e
e
Low Level, X Don’t Care
H
High Level, L
C
1995 National Semiconductor Corporation
TL/F/6559
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
5.5V
Operating Free Air Temperature Range
b
b
a
55 C to 125 C
DM54
DM74
§
0 C to 70 C
§
a
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54180
DM74180
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
IH
0.8
0.8
V
IL
b
b
I
I
0.8
16
125
0.8
16
70
mA
mA
OH
OL
b
T
A
55
0
C
§
Electrical Characteristics over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
12 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
OH
CC
OH
2.4
e
e
Max, V
IL
IH
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
CC
OL
0.4
V
e
e
Min, V
Max
IH
IL
@
Input Current Max
e
e
I
I
I
V
Max, V
5.5V
I
CC
1
mA
mA
Input Voltage
e
High Level Input
Current
V
V
Max
Odd or Even
Data
80
40
IH
CC
e
2.4V
I
e
b
I
I
I
Low Level Input
Current
V
V
Max
Odd or Even
Data
3.2
1.6
IL
CC
mA
mA
mA
e
0.4V
I
b
e
(Note 2)
b
b
b
b
Short Circuit
V
CC
Max
DM54
20
18
55
55
OS
CC
Output Current
DM74
e
(Note 3)
Supply Current
V
CC
Max
DM54
34
34
49
56
DM74
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time.
Note 3: I is measured with EVEN and ODD inputs at 4.5V, all other inputs and outputs open.
A
CC
2
e
e
25 C (See Section 1 for Test Waveforms and Output Load)
Switching Characteristics at V
5V and T
§
CC
A
From (Input)
To (Output)
Symbol
Parameter
Conditions
Min
Max
60
68
48
38
48
38
60
68
20
10
Units
ns
e
e
t
t
t
t
t
t
t
t
t
t
Propagation Delay Time
Low to High Level Output
Data to
C
15 pF
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
L
R Even
R
400X
L
Odd Input Low
Propagation Delay Time
High to Low Level Output
Data to
ns
R Even
Propagation Delay Time
Low to High Level Output
Data to
ns
R Odd
Propagation Delay Time
High to Low Level Output
Data to
ns
R Odd
e
e
Propagation Delay Time
Low to High Level Output
Data to
C
15 pF
L
ns
R Even
R
400X
L
Odd Input High
Propagation Delay Time
High to Low Level Output
Data to
ns
R Even
Propagation Delay Time
Low to High Level Output
Data to
ns
R Odd
Propagation Delay Time
High to Low Level Output
Data to
ns
R Odd
e
e
Propagation Delay Time
Low to High Level Output
Even or Odd to
C
15 pF
L
ns
R Even or R Odd
R
400X
L
Propagation Delay Time
High to Low Level Output
Even or Odd to
ns
R Even or R Odd
Logic Diagram
TL/F/6559–2
3
4
Physical Dimensions inches (millimeters)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54180J
NS Package Number J14A
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74180N
NS Package Number N14A
5
Physical Dimensions inches (millimeters)
14-Lead Ceramic Flat Package (W)
Order Number DM54180W
NS Package Number W14B
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Tel: 1(800) 272-9959
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Fax:
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@
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