DAC1008LCN [NSC]
レP Compatible, Double-Buffered D to A Converters; レP兼容，双缓冲模数转换器
| 型号： | DAC1008LCN |
| 厂家： | 
National Semiconductor |
| 描述： | レP Compatible, Double-Buffered D to A Converters |
| 文件： | 总22页 (文件大小：369K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
January 1995
DAC1006/DAC1007/DAC1008 mP Compatible,
Double-Buffered D to A Converters
General Description
Features
Y
Uses easy to adjust END POINT specs, NOT BEST
STRAIGHT LINE FIT
The DAC1006/7/8 are advanced CMOS/Si-Cr 10-, 9- and
8-bit accurate multiplying DACs which are designed to inter-
face directly with the 8080, 8048, 8085, Z-80 and other pop-
ular microprocessors. These DACs appear as a memory lo-
cation or an I/O port to the mP and no interfacing logic is
needed.
Y
Y
Y
Y
Low power consumption
Direct interface to all popular microprocessors
Integrated thin film on CMOS structure
Double-buffered, single-buffered or flow through digital
data inputs
These devices, combined with an external amplifier and
voltage reference, can be used as standard D/A converters;
and they are very attractive for multiplying applications
(such as digitally controlled gain blocks) since their linearity
error is essentially independent of the voltage reference.
They become equally attractive in audio signal processing
equipment as audio gain controls or as programmable at-
tenuators which marry high quality audio signal processing
to digitally based systems under microprocessor control.
Y
Y
Loads two 8-bit bytes or a single 10-bit word
Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
Y
g
Works with 10V referenceÐfull 4-quadrant multiplica-
tion
Y
Y
Y
Operates STAND ALONE (without mP) if desired
Available in 0.3 standard 20-pin package
×
Differential non-linearity selection available as special
order
All of these DACs are double buffered. They can load all 10
bits or two 8-bit bytes and the data format is left justified.
The analog section of these DACs is essentially the same
as that of the DAC1020.
Key Specifications
Y
Output Current Settling Time
500 ns
10 bits
The DAC1006 series are the 10-bit members of a family of
microprocessor-compatible DAC’s (MICRO-DACTM’s). For
applications requiring other resolutions, the DAC0830 series
(8 bits) and the DAC1208 and DAC1230 (12 bits) are avail-
able alternatives.
Y
Resolution
Y
Linearity
10, 9, and 8 bits
(guaranteed over temp.)
Y
b
Gain Tempco
0.0003% of FS/ C
§
20 mW
Y
Low Power Dissipation
Accuracy
(including ladder)
Ý
Part
Pin Description
(bits)
Y
Single Power Supply
5 to 15 V
DC
DAC1006
DAC1007
DAC1008
10
9
For left-
20
justified
data
8
MICRO-DACTM and BI-FETTM are trademarks of National Semiconductor Corp.
Typical Application
DAC1006/1007/1008
OF BUS
ECTION 6.0
TL/H/5688–1
C
1995 National Semiconductor Corporation
TL/H/5688
RRD-B30M115/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 & 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
ESD Susceptibility (Note 11)
800V
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
260 C
§
Supply Voltage (V
)
CC
17 V
DC
300 C
§
Voltage at Any Digital Input
Voltage at V Input
V
to GND
CC
Operating Ratings (Note 1)
Temperature Range
Part numbers with
‘‘LCN’’ and ‘‘LCWN’’ suffix
g
25V
REF
Storage Temperature Range
s
s
T
MIN
T
A
T
MAX
b
a
65 C to 150 C
§
§
500 mW
e
Package Dissipation at T
25 C (Note 3)
§
or I
A
0 C to 70 C
§
CC
§
to GND
DC Voltage Applied to I
(Note 4)
OUT1
OUT2
Voltage at Any Digital Input
V
b
100 mV to V
CC
Electrical Characteristics
e
e
e
10.000 V
Tested at V
4.75 V
and 15.75 V , T
DC
25 C, V
§
unless otherwise noted
DC
CC
DC
A
REF
e
g
5%
V
12V
CC
to 15V
DC
e
g
See
Note
V
5V
5%
Max.
CC
DC
g
Parameter
Conditions
5%
Units
DC
Typ.
Min.
Max.
Min.
Typ.
Resolution
10
10
bits
Linearity Error
Endpoint adjust only
4,7
6
5
k
k
T
MAX
T
b
T
MIN
A
s
s
a
10V
V
REF
10V
DAC1006
DAC1007
DAC1008
0.05
0.1
0.2
0.05
0.1
0.2
% of FSR
% of FSR
% of FSR
Differential
Nonlinearity
Endpoint adjust only
4,7
6
5
k
k
T
MAX
T
b
T
MIN
A
s
s
a
10V
V
REF
10V
DAC1006
DAC1007
DAC1008
0.1
0.2
0.4
0.1
0.2
0.4
% of FSR
% of FSR
% of FSR
k
k
T
MAX
Monotonicity
T
b
T
A
4,6
5
MIN
s
s
a
10V
V
REF
10V
10V
DAC1006
DAC1007
DAC1008
10
9
8
10
9
8
bits
bits
bits
Gain Error
Using internal R
s
fb
s
b
a
b
b
1.0
g
g
0.3
10V
V
REF
5
1.0
0.3
1.0
1.0
% of FS
k
k
T
MAX
Gain Error Tempco
T
T
6
9
MIN
A
b
b
b
b
Using internal R
0.0003
0.001
0.0006
0.002 % of FS/ C
§
fb
Power Supply
Rejection
All digital inputs
latched high
e
V
14.5V to 15.5V
11.5V to 12.5V
4.75V to 5.25V
0.003
0.004
0.008
0.010
% FSR/V
% FSR/V
% FSR/V
CC
0.033
15
0.10
Reference Input
Resistance
10
15
90
20
10
20
kX
e
All data inputs
e
20V , f 100 kHz
Output Feedthrough
Error
V
REF
p-p
90
mV
p-p
latched low
Output
Capacitance
I
I
I
I
All data inputs
latched low
All data inputs
latched high
60
250
250
60
60
250
250
60
pF
OUT1
OUT2
OUT1
OUT2
pF
pF
pF
s
s
T
MAX
Supply Current Drain
T
MIN
T
A
6
0.5
3.5
0.5
3.5
mA
2
Electrical Characteristics
e
e
e
10.000 V
REF
Tested at V
4.75 V
and 15.75 V , T
DC
25 C, V
§
unless otherwise noted (Continued)
DC
CC
DC
A
e
to 15V
g
5%
V
12V
CC
DC
e
g
See
Note
V
5V
5%
CC
DC
g
Parameter
Conditions
5%
Units
DC
Typ.
Min.
Max.
Min.
Typ.
Max.
s
s
T
MAX
Output Leakage
I
T
T
6
MIN
A
Current
All data inputs
latched low
OUT1
10
200
200
200
200
nA
nA
I
All data inputs
latched high
OUT2
s
Low level
s
T
MAX
Digital Input
Voltages
T
MIN
T
A
6
6
LCN and LCWM suffix
High level (all parts)
0.8, 0.8
0.7, 0.8
V
DC
V
DC
2.0
2.0
s
s
T
MAX
Digital Input
Currents
T
MIN
T
A
k
b
40
1.0
b
a
b
40
1.0
b
150
Digital inputs 0.8V
150
10
mA
DC
mA
DC
l
Digital inputs 2.0V
a
10
e
e
Current Settling
Time
t
t
V
V
0V, V
5V
500
500
ns
S
IL
IH
e
T
e
Write and XFER
Pulse Width
0V, V
5V,
W
IL
IH
25 C
e
8
9
150
320
60
100
320
500
200
250
ns
ns
§
A
s
s
T
MAX
T
V
T
A
MIN
e
T
e
5V,
Data Set Up Time
Data Hold Time
t
t
t
t
0V, V
IH
DS
DH
CS
CH
IL
e
25 C
9
9
9
9
150
320
80
120
320
500
170
250
ns
ns
§
A
s
s
T
V
T
A
T
MAX
MIN
e
T
e
5V
OV, V
IL
IH
e
25 C
200
250
100
120
320
500
220
320
ns
ns
§
A
s
s
T
MAX
T
V
T
A
MIN
e
T
e
Control Set Up
Time
0V, V
5V,
IL
IL
25 C
e
150
320
60
100
320
500
180
260
ns
ns
§
A
s
s
T
MAX
T
V
T
A
MIN
e
T
e
5V,
Control Hold Time
0V, V
IH
IL
e
25 C
10
10
0
0
10
10
0
0
ns
ns
§
A
s
s
T
MAX
T
T
A
MIN
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: This 500 mW specification applies for all packages. The low intrinsic power dissipation of this part (and the fact that there is no way to significantly modify
the power dissipation) removes concern for heat sinking.
Note 4: For current switching applications, both I
d
and I
must go to ground or the ‘‘Virtual Ground’’ of an operational amplifier. The linearity error is
OUT2
OUT1
. For example, if V
e
degraded by approximately V
OS
V
10V then a 1 mV offset, V , on I
OS OUT1
or I will introduce an additional 0.01% linearity error.
OUT2
REF
10 V
REF
1 V
DC
e
e
g
g
Note 5: Guaranteed at V
REF
and V
.
DC
REF
e
e
70 C for ‘‘LCN’’ and ‘‘LCWM’’ suffix parts.
Note 6:
Note 7: The unit ‘‘FSR’’ stands for ‘‘Full Scale Range.’’ ‘‘Linearity Error’’ and ‘‘Power Supply Rejection’’ specs are based on this unit to eliminate dependence on a
particular V value and to indicate the true performance of the part. The ‘‘Linearity Error’’ specification of the DAC1006 is ‘‘0.05% of FSR (MAX).’’ This
T
0 C and T
§
§
MIN
MAX
REF
guarantees that after performing a zero and full scale adjustment (See Sections 2.5 and 2.6), the plot of the 1024 analog voltage outputs will each be within
c
0.05%
V
of a straight line which passes through zero and full scale.
REF
Note 8: This specification implies that all parts are guaranteed to operate with a write pulse or transfer pulse width (t ) of 320 ns. A typical part will operate with t
W
W
of only 100 ns. The entire write pulse must occur within the valid data interval for the specified t , t , t , and t to apply.
DS DH
W
S
Note 9: Guaranteed by design but not tested.
b
9
3
c
e
e
c
10V corresponds to a zero error of (200 10
c c d
20 10 ) 100 10 which is 0.04% of FS.
Note 10: A 200 nA leakage current with R
20K and V
fb
REF
Note 11: Human body model, 100 pF discharged through a 1.5 kX resistor.
3
Switching Waveforms
TL/H/5688–2
Typical Performance Characteristics
Errors vs. Supply Voltage
Errors vs. Temperature
Write Width, t
W
TL/H/5688–3
4
Block and Connection Diagrams
DAC1006/1007/1008 (20-Pin Parts)
DAC1006/1007/1008
(20-Pin Parts)
Dual-In-Line Package
TL/H/5688–28
Top View
See Ordering Information
TL/H/5688–5
DAC1006/1007/1008ÐSimple Hookup for a ‘‘Quick Look’’
TL/H/5688–7
Notes:
eb
1. For V
10.240 V
the output voltage steps are approximately 10 mV each.
DC
REF
2. SW1 is a normally closed switch. While SW1 is closed, the DAC register is latched and new data
can be loaded into the input latch via the 10 SW2 switches.
When SW1 is momentarily opened the new data is transferred from the input latch to the DAC register and is latched when SW1 again closes.
5
1.0 DEFINITION OF PACKAGE PINOUTS
1.1 Control Signals (All control signals are level actuated.)
CS: Chip Select Ð active low, it will enable WR.
R
: Feedback Resistor Ð This is provided on the IC chip
FB
for use as the shunt feedback resistor when an external op
amp is used to provide an output voltage for the DAC. This
on-chip resistor should always be used (not an external re-
sistor) because it matches the resistors used in the on-chip
R-2R ladder and tracks these resistors over temperature.
WR: Write Ð The active low WR is used to load the digital
data bits (DI) into the input latch. The data in the input latch
is latched when WR is high. The 10-bit input latch is split
into two latches; one holds 8 bits and the other holds 2 bits.
The Byte1/Byte2 control pin is used to select both input
V : Reference Voltage Input Ð This is the connection for
REF
the external precision voltage source which drives the R-2R
e
latches when Byte1/Byte2 1 or to overwrite the 2-bit input
latch when in the low state.
b a
can range from 10 to 10 volts. This is also
ladder. V
REF
the analog voltage input for a 4-quadrant multiplying DAC
application.
Byte1/Byte2: Byte Sequence Control Ð When this control
is high, all ten locations of the input latch are enabled. When
low, only two locations of the input latch are enabled and
these two locations are overwritten on the second byte
write. On the DAC1006, 1007, and 1008, the Byte1/Byte2
must be low to transfer the 10-bit data in the input latch to
the DAC register.
V : Digital Supply Voltage Ð This is the power supply pin
for the part. V can be from 5 to 15 V . Operation is
CC
a
a
optimum for 15V. The input threshold voltages are nearly
CC DC
a
independent of V . (See Typical Performance Characteris-
CC
tics and Description in Section 3.0, T L compatible logic
inputs.)
2
XFER: Transfer Control Signal, active low Ð This signal, in
combination with others, is used to transfer the 10-bit data
which is available in the input latch to the DAC register Ð
see timing diagrams.
GND: Ground Ð the ground pin for the part.
1.3 Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC1006
1.2 Other Pin Functions
10
has 2 or 1024 steps and therefore has 10-bit resolution.
e
DI (i 0 to 9): Digital Inputs Ð DI is the least significant bit
(LSB) and DI is the most significant bit (MSB).
i
0
Linearity Error: Linearity error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting
for zero and full-scale. Linearity error is a parameter intrinsic
to the device and cannot be externally adjusted.
g
I
: DAC Current Output 1 Ð I
OUT1
is a maximum for a
OUT1
digital input code of all 1s and is zero for a digital input code
of all 0s.
I
: DAC Current Output 2 Ð I
OUT2
, or
is a constant minus
OUT2
National’s linearity test (a) and the ‘‘best straight line’’ test
(b) used by other suppliers are illustrated below. The ‘‘best
straight line’’ requires a special zero and FS adjustment for
each part, which is almost impossible for user to determine.
The ‘‘end point test’’ uses a standard zero and FS adjust-
ment procedure and is a much more stringent test for DAC
linearity.
I
OUT1
1023 V
REF
a
e
OUT2
I
I
OUT1
1024 R
15 kX.
j
where R
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output (which is the worst case).
a. End Point Test After Zero and FS Adj.
b. Best Straight Line
TL/H/5688–8
6
Settling Time: Settling time is the time required from a code
g
3.0 TTL COMPATIBLE LOGIC INPUTS
transition until the DAC output reaches within (/2 LSB of
the final output value. Full-scale settling time requires a zero
to full-scale or full-scale to zero output change.
To guarantee TTL voltage compatibility of the logic inputs, a
novel bipolar (NPN) regulator circuit is used. This makes the
input logic thresholds equal to the forward drop of two di-
odes (and also matches the temperature variation) as oc-
curs naturally in TTL. The basic circuit is shown in Figure 1.
A curve of digital input threshold as a function of power
supply voltage is shown in the Typical Performance Charac-
teristics section.
Full-Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
b
Ideally, for the DAC1006 series, full-scale is V
1 LSB.
FULL-SCA-
10.0000V 9.8mV 9.9902V. Full-scale error is adjust-
REF
eb
For
V
10V and unipolar operation, V
REF
e
b
e
LE
able to zero.
4.0 APPLICATION HINTS
Monotonicity: If the output of a DAC increases for increas-
ing digital input code, then the DAC is monotonic. A 10-bit
DAC with 10-bit monotonicity will produce an increasing an-
alog output when all 10 digital inputs are exercised. A 10-bit
DAC with 9-bit monotonicity will be monotonic when only
the most significant 9 bits are exercised. Similarly, 8-bit
monotonicity is guaranteed when only the most significant 8
bits are exercised.
The DC stability of the V
REF
source is the most important
factor to maintain accuracy of the DAC over time and tem-
perature changes. A good single point ground for the analog
signals is next in importance.
These MICRO-DAC converters are CMOS products and
reasonable care should be exercised in handling them prior
to final mounting on a PC board. The digital inputs are pro-
tected, but permanent damage may occur if the part is sub-
jected to high electrostatic fields. Store unused parts in con-
ductive foam or anti-static rails.
2.0 DOUBLE BUFFERING
These DACs are double-buffered, microprocessor compati-
ble versions of the DAC1020 10-bit multiplying DAC. The
addition of the buffers for the digital input data not only al-
lows for storage of this data, but also provides a way to
assemble the 10-bit input data word from two write cycles
when using an 8-bit data bus. Thus, the next data update for
the DAC output can be made with the complete new set of
10-bit data. Further, the double buffering allows many DACs
in a system to store current data and also the next data. The
updating of the new data for each DAC is also not time
critical. When all DACs are updated, a common strobe sig-
nal can then be used to cause all DACs to switch to their
new analog output levels.
4.1 Power Supply Sequencing & Decoupling
Some IC amplifiers draw excessive current from the Analog
b
inputs to V when the supplies are first turned on. To pre-
vent damage to the DAC Ð an external Schottky diode con-
nected from I
or I
OUT2
to ground may be required to
or I . If an LM741
OUT1
prevent destructive currents in I
OUT1
or LF356 is used Ð these diodes are not required.
OUT2
The standard power supply decoupling capacitors which are
used for the op amp are adequate for the DAC.
TL/H/5688–9
FIGURE 1. Basic Logic Threshold Loop
7
4.2 Op Amp Bias Current & Input Leads
able ladder current to the I
output pin. These MOS
OUT1
switches operate in the current mode with a small voltage
drop across them and can therefore switch currents of ei-
ther polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
The op amp bias current (I ) CAN CAUSE DC ERRORS. BI-
B
FETTM op amps have very low bias current, and therefore
the error introduced is negligible. BI-FET op amps are
strongly recommended for these DACs.
The distance from the I
OUT1
input of the op amp should be kept as short as possible to
prevent inadvertent noise pickup.
pin of the DAC to the inverting
5.1.1 Providing a Unipolar Output Voltage with the
DAC in the Current Switching Mode
A voltage output is provided by making use of an external
op amp as a current-to-voltage converter. The idea is to use
5.0 ANALOG APPLICATIONS
the internal feedback resistor, R , from the output of the
FB
The analog section of these DACs uses an R-2R ladder
which can be operated both in the current switching mode
and in the voltage switching mode.
b
op amp to the inverting ( ) input. Now, when current is
entered at this inverting input, the feedback action of the op
amp keeps that input at ground potential. This causes the
applied input current to be diverted to the feedback resistor.
The output voltage of the op amp is forced to a voltage
given by:
The major product changes (compared with the DAC1020)
have been made in the digital functioning of the DAC. The
analog functioning is reviewed here for completeness. For
additional analog applications, such as multipliers, attenua-
tors, digitally controlled amplifiers and low frequency sine
wave oscillators, refer to the DAC1020 data sheet. Some
basic circuit ideas are presented in this section in addition to
complete applications circuits.
e b
c
R
FB
V
(I
)
OUT
OUT1
Notice that the sign of the output voltage depends on the
direction of current flow through the feedback resistor.
In current switching mode applications, both current output
) should be operated at 0 V . This is
DC
pins (I
OUT1
and I
OUT2
5.1 Operation in Current Switching Mode
accomplished as shown in Figure 3. The capacitor, C , is
C
The analog circuitry, Figure 2, consists of a silicon-chromi-
um (Si-Cr) thin film R-2R ladder which is deposited on the
surface oxide of the monolithic chip. As a result, there is no
used to compensate for the output capacitance of the DAC
and the input capacitance of the op amp. The required feed-
back resistor, R , is available on the chip (one end is inter-
FB
parasitic diode connected to the V
pin as would exist if
diffused resistors were used. The reference voltage input
REF
nally tied to I ) and must be used since an external
OUT1
resistor will not provide the needed matching and tempera-
ture tracking. This circuit can therefore be simplified as
b a
(V ) can therefore range from 10V to 10V.
REF
The digital input code to the DAC simply controls the posi-
tion of the SPDT current switches, SW0 to SW9. A logical 1
digital input causes the current switch to steer the avail-
DIGITAL INPUT CODE
mS
TL/H/5688–10
%
%
FIGURE 3. Converting I
to V
OUT
LF356
LF351
LF357
22
24
3
4
OUT
10 2.4k 1.5
8
shown in Figure 4, where the sign of the reference voltage
has been changed to provide a positive output voltage. Note
where V can be positive or negative and D is the signed
decimal equivalent of the 2’s complement processor data.
REF
s
s
s s
b
a
511 or 1000000000
that the output current, I
pin.
, now flows through the R
OUT1 FB
(
512
applied digital input is interpreted as the decimal equivalent
of a true binary word, V can be found by:
D
D 0111111111). If the
OUT
5.1.2 Providing a Bipolar Output Voltage with the
DAC in the Current Switching Mode
b
D
512
s
s
1023
e
V
V
0
D
O
REF
512
#
J
The addition of a second op amp to the circuit of Figure 4
can be used to generate a bipolar output voltage from a
fixed reference voltage Figure 5. This, in effect, gives sign
significance to the MSB of the digital input word to allow two
quadrant multiplication of the reference voltage. The polarity
of the reference can also be reversed to realize the full four-
quadrant multiplication.
With this configuration, only the offset voltage of amplifier 1
need be nulled to preserve linearity of the DAC. The offset
voltage error of the second op amp has no effect on lineari-
ty. It presents a constant output voltage error and should be
nulled only if absolute accuracy is needed. Another advan-
tage of this configuration is that the values of the external
resistors required do not have to match the value of the
internal DAC resistors; they need only to match and temper-
ature track each other.
The applied digital word is offset binary which includes a
code to output zero volts without the need of a large valued
resistor common to existing bipolar multiplying DAC circuits.
Offset binary code can be derived from 2’s complement
data (most common for signed processor arithmetic) by in-
verting the state of the MSB in either software or hardware.
After doing this the output then responds in accordance to
the following expression:
A thin film 4 resistor network available from Beckman Instru-
ments, Inc. (part no. 694-3-R10K-D) is ideally suited for this
application. Two of the four available 10 kX resistor can be
paralleled to form R in Figure 5 and the other two can be
used separately as the resistors labeled 2R.
Operation is summarized in the table below:
D
e
c
V
V
REF
O
512
Applied
2’s Comp.
(Decimal)
2’s Comp.
(Binary)
Applied
True Binary
(Decimal)
V
OUT
a
b
V
REF
Digital Input
V
REF
a
a
b
b
a
1 LSB
REF
511
256
0111111111
0100000000
0000000000
1111111111
1100000000
1000000000
1111111111
1100000000
1000000000
0111111111
0100000000
0000000000
1023
768
512
511
256
0
V
1 LSB
/2
V
REF
V
l
l
b
V
REF
0
/2
REF
0
l
l
0
b
b
b
b
b
b
a
1 LSB
1
1 LSB
a
a
256
512
V
/2
V
/2
REF
V
l
REF
V
l
REF
l
REF
l
V
l
REF
l
e
with: 1 LSB
512
TL/H/5688–11
FIGURE 5. Providing a Bipolar Output Voltage with the DAC in the Current Switching Mode
9
5.2 Analog Operation in the Voltage Switching Mode
Notice that this is unipolar operation since all voltages are
positive. A bipolar output voltage can be obtained by using a
single op amp as shown in Figure 10. For a digital input
Some useful application circuits result if the R-2R ladder is
operated in the voltage switching mode. There are two very
important things to remember when using the DAC in the
a
voltage mode. The reference voltage ( V) must always be
positive since there are parasitic diodes to ground on the
code of all zeros, the output voltage from the V
pin is
zero volts. The external op amp now has a single input of
REF
a
b
V and is operating with a gain of 1 to this input. The
b
output of the op amp therefore will be at V for a digital
input of all zeros. As the digital code increases, the output
I
pin which would turn on if the reference voltage went
OUT1
negative. To maintain a degradation of linearity less than
voltage at the V
pin increases.
s
a
REF
g
0.005%, keep
a
V
3 V
DC
and V at least 10V more
CC
positive than V. Figures 6 and 7 show these errors for the
voltage switching mode. This operation appears unusual,
Notice that the gain of the op amp to voltages which are
a
2 and the gain to voltages
a
applied to the ( ) input is
a
b
since a reference voltage ( V) is applied to the I pin
OUT1
pin. This basic idea is
which are applied to the input resistor, R, is 1. The output
voltage of the op amp depends on both of these inputs and
is given by:
and the voltage output is the V
shown in Figure 8.
REF
e a
(
b
V) ( 1)
a
a
V ( 2)
REF
This V range can be scaled by use of a non-inverting
OUT
gain stage as shown in Figure 9.
V
OUT
TL/H/5688–12
FIGURE 9. Amplifying the Voltage Mode Output (Single Supply Operation)
10
TL/H/5688–13
FIGURE 11. Increasing the Output Voltage Swing
The output voltage swing can be expanded by adding 2
resistors to Figure 10 as shown in Figure 11. These added
If the V is to be adjusted there are a few points to consid-
OS
er. Note that no ‘‘dc balancing’’ resistance should be used
in the grounded positive input lead of the op amp. This re-
sistance and the input current of the op amp can also create
errors. The low input biasing current of the BI-FET op amps
makes them ideal for use in DAC current to voltage applica-
a
resistors are used to attenuate the V voltage. The overall
gain, A ( ), from the V terminal to the output of the op
b
a
V
b
a
amp determines the most negative output voltage, 4( V)
input of the op amp is
a
(when the V
voltage at the
REF
zero) with the component values shown. The complete dy-
tions. The V
0 mA. A 1 kX resistor
can be temporarily connected from the inverting input to
of the op amp should be adjusted with a
e
OS
digital input of all zeros to force I
a
namic range of V
input of the op amp. As the voltage at the V
is provided by the gain from the (
pin ranges
from 0V to V(1023/1024) the output of the op amp will
)
OUT
OUT
REF
a
ground to provide a dc gain of approximately 15 to the V
of the op amp and make the zeroing easier to sense.
OS
b
a
to 10V (1023/1024) when using a
V voltage of 2.500 V . The 2.5 V reference voltage
range from 10 V
DC
a
a
DC DC
5.4 Full-Scale Adjust
can be easily developed by using the LM336 zener which
can be biased through the R internal resistor, connected
The full-scale adjust procedure depends on the application
circuit and whether the DAC is operated in the current
switching mode or in the voltage switching mode. Tech-
niques are given below for all of the possible application
circuits.
FB
to V
.
CC
5.3 Op Amp V Adjust (Zero Adjust) for Current
OS
Switching Mode
Proper operation of the ladder requires that all of the 2R
(ground). Therefore offset
5.4.1 Current Switching with Unipolar Output Voltage
legs always go to exactly 0 V
DC
voltage, V , of the external op amp cannot be tolerated as
After doing a ‘‘zero adjust,’’ set all of the digital input levels
for
OS
every millivolt of V will introduce 0.01% of added linearity
OS
HIGH and adjust the magnitude of V
REF
error. At first this seems unusually sensitive, until it becomes
clear the 1 mV is 0.01% of the 10V reference! High resolu-
tion converters of high accuracy require attention to every
detail in an application to achieve the available performance
which is inherent in the part. To prevent this source of error,
1023
eb
V
(ideal V )
REF
OUT
1024
This completes the DAC calibration.
the V
OS
of the op amp has to be initially zeroed. This is the
‘‘zero adjust’’ of the DAC calibration sequence and should
be done first.
11
5.4.2 Current Switching with Bipolar Output Voltage
5.4.3 Voltage Switching with a Unipolar Output Voltage
The circuit of Figure 12 shows the 3 adjustments needed.
The first step is to set all of the digital inputs LOW (to force
Refer to the circuit of Figure 13 and set all digital inputs
e
set all digital inputs HIGH and trim the ‘‘FS Adj.’’ for:
g
LOW. Trim the ‘‘zero adj.’’ for V
0 V
1 mV. Then
OUT
DC
I
to 0) and then trim ‘‘zero adj.’’ for zero volts at the
OUT1
inverting input (pin 2) of 0A1. Next, with a code of all zeros
R
R
1023
1024
1
e a a
V) 1
V
(
b
still applied, adjust ‘‘ FS adj.’’, the reference voltage, for
e
OUT
# J
2
g
V
OUT
(ideal V ) . The sign of the output voltage will
REF
l
l
be opposite that of the applied reference.
Finally, set all of the digital inputs HIGH and adjust ‘‘ FS
5.4.4 Voltage Switching with a Bipolar Output Voltage
a
Refer to Figure 14 and set all digital inputs LOW. Trim the
eb
e
b
‘‘ FS Adj.’’ for V
HIGH and trim the ‘‘ FS Adj.’’ for V
adj.’’ for V
V
(511/512). The sign of the output at
2.5 V . Then set all digital inputs
DC
OUT
this time will be the same as that of the reference voltage.
The addition of the 200X resistor in series with the V pin
REF
OUT
a
ea
2.5 (511/512)
OUT
V . Test the zero by setting the MS digital input HIGH and
DC
all the rest LOW. Adjust V
REF
of the DAC is to force the circuit gain error from the DAC to
Ý
of amp 3, if necessary, and
OS
be negative. This insures that adding resistance to R , with
fb
recheck the full-scale values.
the 500X pot, will always compensate the gain error of the
DAC.
TL/H/5688–14
FIGURE 13. Full Scale Adjust Ð Voltage Switching with a Unipolar Output Voltage
12
TL/H/5688-15
FIGURE 14. Voltage Switching with a Bipolar Output Voltage
6.0 DIGITAL CONTROL DESCRIPTION
The DAC1006 series of products can be used in a wide
variety of operating modes. Most of the options are shown
in Table 1. Also shown in this table are the section numbers
of this data sheet where each of the operating modes is
discussed. For example, if your main interest in interfacing
to a mP with an 8-bit data bus you will be directed to Section
6.1.0.
2) operating with a double digital data buffer for simulta-
neous transfer, or updating, of more than one DAC.
For operating without a mP in the stand alone mode, three
options are provided: 1) using only a single digital data buff-
er, 2) using both digital data buffers Ð ‘‘double buffered,’’ or
3) allowing the input digital data to ‘‘flow through’’ to provide
the analog output without the use of any data latches.
The first consideration is ‘‘will the DAC be interfaced to a mP
with an 8-bit or a 16-bit data bus or used in the stand-alone
mode?’’ For the 8-bit data bus, a second selection is made
on how the 2nd digital data buffer (the DAC Latch) is updat-
ed by a transfer from the 1st digital data buffer (the Input
Latch). Three options are provided: 1) an automatic transfer
when the 2nd data byte is written to the DAC, 2) a transfer
which is under the control of the mP and can include more
than one DAC in a simultaneous transfer, or 3) a transfer
which is under the control of external logic. Further, the data
format can be either left justified or right justified.
To reduce the required reading, only the applicable sections
of 6.1 through 6.4 need be considered.
6.1 Interfacing to an 8-Bit Data Bus
Transferring 10 bits of data over an 8-bit bus requires two
write cycles and provides four possible combinations which
depend upon two basic data format and protocol decisions:
1. Is the data to be left justified (considered as fractional
binary data with the binary point to the left) or right justi-
fied (considered as binary weighted data with the binary
point to the right)?
When interfacing to a mP with a 16-bit data bus only two
selections are available: 1) operating the DAC with a single
digital data buffer (the transfer of one DAC does not have to
be synchronized with any other DACs in the system), or
2. Which byte will be transferred first, the most significant
byte (MS byte) or the least significant byte (LS byte)?
Table 1
Operating Mode
Automatic Transfer
Section Figure No.
mP Control Transfer
External Transfer
Section Figure No.
Section
Figure No.
Data Bus
8-Bit Data Bus (6.1.0)
Left Justified (6.1.1)
6.2.1
16
17
6.2.2
16
6.2.3
16
Single Buffered
Double Buffered
Flow Through
16-Bit Data Bus (6.3.0)
Stand Alone (6.4.0)
6.3.1
6.3.2
17
Not Applicable
Flow Through
NA
Single Buffered
Double Buffered
6.4.1
17
6.4.2
17
13
These data possibilities are shown in Figure 15. Note that
the justification of data depends on how the 10-bit data
word is located within the 16-bit data source (CPU) register.
In either case, there is a surplus of 6 bits and these are
parts require the MS or Hi Byte data group to be transferred
on the 1st write cycle.
6.2 Controlling Data Transfer for an 8-Bit Data Bus
Three operating modes are possible for controlling the
transfer of data from the Input Latch to the DAC Register,
where it will update the analog output voltage. The simplest
is the automatic transfer mode, which causes the data
transfer to occur at the time of the 2nd write cycle. This is
recommended when the exact timing of the changes of the
DAC analog output are not critical. This typically happens
where each DAC is operating individually in a system and
the analog updating of one DAC is not required to be syn-
chronized to any other DAC. For synchronized DAC updat-
ing, two options are provided: mP control via a common
XFER strobe or external update timing control via an exter-
nal strobe. The details of these options are now shown.
c
shown as ‘‘don’t care’’ terms (‘‘ ’’) in this figure.
All of these DACs load 10 bits on the 1st write cycle. A
particular set of 2 bits is then overwritten on the 2nd write
cycle, depending on the justification of the data. For all left
justified data options, the 1st write cycle must contain the
MS or Hi Byte data group.
6.1.1 For Left Justified Data
For applications which require left justified data, DAC1006–
1008 can be used. A simplified logic diagram which shows
the external connections to the data bus and the internal
functions of both of the data buffer registers (Input Latch
and DAC Register) is shown in Figure 16. These
DAC1006/1007/1008 (20-Pin Parts for Left Justified Data)
TL/H/5688–16
FIGURE 15. Fitting a 10-Bit Data Word into 16 Available Bit Locations
TL/H/5688–17
FIGURE 16. Input Connections and Controls for DAC1006/1007/1008 Left Justified Data
14
6.2.1 Automatic Transfer
6.2.3 Transfer Using an External Strobe
This makes use of a double byte (double precision) write.
The first byte (8 bits) is strobed into the input latch and the
second byte causes a simultaneous strobe of the two re-
maining bits into the input latch and also the transfer of the
complete 10-bit word from the input latch to the DAC regis-
ter. This is shown in the following timing diagram; the point
in time where the analog output is updated is also indicated
on this diagram.
This is similar to the previous operation except the XFER
signal is not provided by the mP. The timing diagram for this
is:
DAC1006/1007/1008 (20-Pin Parts)
DAC1006/1007/1008 (20-Pin Parts)
TL/H/5688–20
TL/H/5688–18
6.3 Interfacing to a 16-Bit Data Bus
*SIGNIFIES CONTROL INPUTS WHICH ARE DRIVEN IN PARALLEL
The interface to a 16-bit data bus is easily handled by con-
necting to 10 of the available bus lines. This allows a wiring
selected right justified or left justified data format. This is
shown in the connection diagram of Figure 17, where the
use of DB6 to DB15 gives left justified data operation. Note
that any part number can be used and the Byte1/Byte2 con-
trol should be wired Hi.
6.2.2 Transfer Using mP Write Stroke
The input latch is loaded with the first two write strobes. The
XFER signal is provided by external logic, as shown below,
to cause the transfer to be accomplished on a third write
strobe. This is shown in the following diagram:
DAC1006/1007/1008 (20-Pin Parts)
TL/H/5688–19
15
TL/H/5688–21
FIGURE 17. Input Connections and Logic for DAC1006/1007/1008 with 16-Bit Data Bus
Three operating modes are possible: flow through, single 6.4 Stand Alone Operation
buffered, or double buffered. The timing diagrams for these
are shown below:
For applications for a DAC which are not under mP control
(stand alone) there are two basic operating modes, single
buffered and double buffered. The timing diagrams for these
are shown below:
6.3.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)
6.4.1 Single Buffered
DAC1006/1007/1008 (20-Pin Parts)
6
TL/H/5688–23
TL/H/5688–22
*For a connection diagram of this operating mode use Figure 16 for the Logic and Figure 17 for the Data Input connections.
16
7.0 MICROPROCESSOR INTERFACE
The logic functions of the DAC1006 family have been ori-
ented towards an ease of interface with all popular mPs. The
following sections discuss in detail a few useful interface
schemes.
The circuit will perform an automatic transfer of the 10 bits
of output data from the CPU to the DAC register as outlined
in Section 6.2.1, ‘‘Controlling Data Transfer for an 8-Bit Data
Bus.’’
Since a double byte write is necessary to control the DAC
with the INS8080A, a possible instruction to achieve this is a
PUSH of a register pair onto a ‘‘stack’’ in memory. The 16-
bit register pair word will contain the 10 bits of the eventual
DAC input data in the proper sequence to conform to both
7.1 DAC1001/1/2 to INS8080A Interface
Figure 18 illustrates the simplicity of interfacing the
DAC1006 to an INS8080A based microprocessor system.
TL/H/5688–24
NOTE: DOUBLE BYTE STORES CAN BE USED.
e.g. THE INSTRUCTION SHLD F001 STORES THE L
REG INTO B1 AND THE H REG INTO B2 AND
TRANSFERS THE RESULT TO THE DAC REGISTER.
THE OPERAND OF THE SHLD INSTRUCTION MUST
BE AN ODD ADDRESS FOR PROPER TRANSFER.
FIGURE 18. Interfacing the DAC1000 to the INS8080A CPU Group
17
the requirements of the DAC (with regard to left justified
data) and the implementation of the PUSH instruction which
will output the higher order byte of the register pair (i.e.,
register B of the BC pair) first. The DAC will actually appear
as a two-byte ‘‘stack’’ in memory to the CPU. The auto-dec-
rementing of the stack pointer during a PUSH allows using
address bit 0 of the stack pointer as the Byte1/Byte2 and
PIA, and the LOW byte is loaded into ORB. The 10-bit data
transfer to the DAC and the corresponding analog output
change occur simultaneously upon CB2 going LOW under
program control. The 10-bit data word in the DAC register
will be latched (and hence V
brought back HIGH.
will be fixed) when CB2 is
OUT
If both output ports of the PIA are not available, it is possible
to interface the DAC1006 through a single port without
much effort. However, additional logic at the CB2(or CA2)
lines or access to some of the 6800 system control lines will
be required.
b
XFER strobes if bit 0 of the stack pointer address
1,
b
(SP 1), is a ‘‘1’’ as presented to the DAC. Additional ad-
dress decoding by the DM8131 will generate a unique DAC
chip select (CS) and synchronize this CS to the two memory
write strobes of the PUSH instruction.
7.3 Noise Considerations
To reset the stack pointer so new data may be output to the
same DAC, a POP instruction followed by instructions to
insure that proper data is in the DAC data register pair be-
fore it is ‘‘PUSHED’’ to the DAC should be executed, as the
POP instruction will arbitrarily alter the contents of a register
pair.
A typical digital/microprocessor bus environment is a tre-
mendous potential source of high frequency noise which
can be coupled to sensitive analog circuitry. The fast edges
of the data and address bus signals generate frequency
components of 10’s of megahertz and can cause noise
spikes to appear at the DAC output. These noise spikes
occur when the data bus changes state or when data is
transferred between the latches of the device.
Another double byte write instruction is Store H and L Direct
(SHLD), where the HL register pair would temporarily con-
tain the DAC data and the two sequential addresses for the
DAC are specified by the instruction op code. The auto in-
crementing of the DAC address by the SHLD instruction
permits the same simple scheme of using address bit 0 to
generate the byte number and transfer strobes.
In low frequency or DC applications, low pass filtering can
reduce these noise spikes. This is accomplished by over-
compensating the DAC output amplifier by increasing the
value of the feedback capacitor (C in Figure 3 ).
C
In applications requiring a fast transient response from the
DAC and op amp, filtering may not be feasible. Adding a
latch, DM74LS374, as shown in Figure 20 isolates the de-
vice from the data bus, thus eliminating noise spikes that
occur every time the data bus changes state. Another meth-
od for eliminating noise spikes is to add a sample and hold
after the DAC op amp. This also has the advantage of elimi-
nating noise spikes when changing digital codes.
7.2 DAC1006 to MC6820/1 PIA Interface
In Figure 19 the DAC1006 is interfaced to an M6800 system
through an MC6820/1 Peripheral Interface Adapter (PIA). In
this case the CS pin of the DAC is grounded since the PIA is
already mapped in the 6800 system memory space and no
decoding is necessary. Furthermore, by using both Ports A
and B of the PIA the 10-bit data transfer, assumed left
justified again in two 8-bit bytes, is greatly simplified. The
HIGH byte is loaded into Output Register A (ORA) of the
TL/H/5688–25
FIGURE 19. DAC1000 to MC6820/1 PIA Interface
18
&
AT OF DM74LS374 ( 10 ns)
FIGUpling
TL/H/5688–26
FIGURE 21. Digitally Controlled Amplifier/Attenuator
7.4 Digitally Controlled Amplifier/Attenuator
e
An unusual application of the DAC, Figure 21, applies the
input voltage via the on-chip feedback resistor. The lower
Note that N 0 (or a digital code of all zeros) is not allowed
or this will cause the output amplifier to saturate at either
g
op amp automatically adjusts the V
REF IN
voltage such that
V
, depending on the sign of V .
MAX
IN
To provide a digitally controlled divider, the output op amp
I
is equal to the input current (V /Rf ). The magnitude
IN
OUT1
of this V
B
voltage depends on the digital word which is
REF IN
in the DAC register. I
can be eliminated. Ground the I
pin of the DAC and
is now taken from the lower op amp (which also drives
OUT2
then depends upon both the
OUT2
magnitude of V and the digital word. The second op amp
V
OUT
the V
IN
to a voltage, V
input of the DAC). The expression for V
is now
REF
given by
OUT
converts I
, which is given by:
OUT
OUT2
1023
b
N
V
IN
k
s
1023.
e
V
V
, where 0
N
eb
e
where M Digital input (expressed as a
fractional binary number).
OUT
IN
V
OUT
N
#
J
M
k
k
1.
0
M
19
TL/H/5688–27
FIGURE 22. Digital to Synchro Converter
Ordering Information
For Left Justified Data Ð 20-pin package.
Temperature Range
a
0 to 70 C
Accuracy
§
§
0.05% (10-bit)
0.10% (9-bit)
0.20% (8-bit)
DAC1006LCN
DAC1007LCN
DAC1008LCN
DAC1006LCWM
Package Outline
N20A
M20B
20
Physical Dimensions inches (millimeters)
Order Number DAC1006LCWM
NS Package Number M20B
21
Physical Dimensions inches (millimeters) (Continued)
Order Number DAC1006LCN, DAC1007LCN or DAC1008LCN
NS Package Number N20A
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NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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Fax:
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