DAC0832LCMX [NSC]
暂无描述;
| 型号： | DAC0832LCMX |
| 厂家： | 
National Semiconductor |
| 描述： | 暂无描述 |
| 文件： | 总28页 (文件大小：580K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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Texas Instruments.
Search http://www.ti.com/ for the latest technical
information and details on our current products and services.
May 1999
DAC0830/DAC0832
8-Bit µP Compatible, Double-Buffered D to A Converters
General Description
Features
n Double-buffered, single-buffered or flow-through digital
data inputs
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying
DAC designed to interface directly with the 8080, 8048,
8085, Z80®, and other popular microprocessors. A deposited
silicon-chromium R-2R resistor ladder network divides the
reference current and provides the circuit with excellent tem-
perature tracking characteristics (0.05% of Full Scale Range
maximum linearity error over temperature). The circuit uses
CMOS current switches and control logic to achieve low
power consumption and low output leakage current errors.
Special circuitry provides TTL logic input voltage level com-
patibility.
n Easy interchange and pin-compatible with 12-bit
DAC1230 series
n Direct interface to all popular microprocessors
n Linearity specified with zero and full scale adjust
only — NOT BEST STRAIGHT LINE FIT.
±
n Works with 10V reference-full 4-quadrant multiplication
n Can be used in the voltage switching mode
n Logic inputs which meet TTL voltage level specs (1.4V
logic threshold)
n Operates “STAND ALONE” (without µP) if desired
n Available in 20-pin small-outline or molded chip carrier
package
Double buffering allows these DACs to output a voltage cor-
responding to one digital word while holding the next digital
word. This permits the simultaneous updating of any number
of DACs.
The DAC0830 series are the 8-bit members of a family of
Key Specifications
n Current settling time: 1 µs
™
microprocessor-compatible DACs (MICRO-DAC ).
n Resolution: 8 bits
n Linearity: 8, 9, or 10 bits (guaranteed over temp.)
n Gain Tempco: 0.0002% FS/˚C
n Low power dissipation: 20 mW
n Single power supply: 5 to 15 VDC
Typical Application
DS005608-1
™
™
BI-FET and MICRO-DAC are trademarks of National Semiconductor Corporation.
Z80® is a registered trademark of Zilog Corporation.
© 1999 National Semiconductor Corporation
DS005608
www.national.com
Connection Diagrams (Top Views)
Dual-In-Line and
Molded Chip Carrier Package
Small-Outline Packages
DS005608-22
DS005608-21
www.national.com
2
Absolute Maximum Ratings (Notes 1, 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Lead Temperature (Soldering, 10 sec.)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
260˚C
300˚C
Vapor Phase (60 sec.)
215˚C
220˚C
Supply Voltage (VCC
)
17 VDC
Infrared (15 sec.)
Voltage at Any Digital Input
Voltage at VREF Input
VCC to GND
±
25V
Operating Conditions
Temperature Range
Storage Temperature Range
Package Dissipation
−65˚C to +150˚C
T
MIN≤TA≤TMAX
0˚C to +70˚C
0˚C to +70˚C
0˚C to +70˚C
=
at TA 25˚C (Note 3)
500 mW
Part numbers with “LCN” suffix
Part numbers with “LCWM” suffix
Part numbers with “LCV” suffix
Part numbers with “LCJ” suffix
Part numbers with “LJ” suffix
Voltage at Any Digital Input
DC Voltage Applied to
IOUT1 or IOUT2 (Note 4)
ESD Susceptability (Note 4)
−100 mV to VCC
800V
−40˚C to +85˚C
−55˚C to +125˚C
VCC to GND
Electrical Characteristics
=
VREF 10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
=
TA 25˚C.
=
±
VCC 5 VDC 5%
=
VCC 4.75 VDC
=
±
VCC 12 VDC 5%
=
VCC 15.75 VDC
±
to 15 VDC 5%
See
Note
Limit
Units
Parameter
Conditions
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Typ
(Note 12)
CONVERTER CHARACTERISTICS
Resolution
8
8
8
bits
Linearity Error Max
Zero and full scale adjusted
4, 8
−10V≤VREF≤+10V
DAC0830LJ & LCJ
DAC0832LJ & LCJ
0.05
0.2
0.05
0.2
% FSR
% FSR
% FSR
DAC0830LCN, LCWM &
LCV
0.05
0.05
DAC0831LCN
0.1
0.2
0.1
0.2
% FSR
% FSR
DAC0832LCN, LCWM &
LCV
Differential Nonlinearity
Max
Zero and full scale adjusted
4, 8
−10V≤VREF≤+10V
DAC0830LJ & LCJ
DAC0832LJ & LCJ
0.1
0.4
0.1
0.1
0.4
0.1
% FSR
% FSR
% FSR
DAC0830LCN, LCWM &
LCV
DAC0831LCN
0.2
0.4
0.2
0.4
% FSR
% FSR
DAC0832LCN, LCWM &
LCV
Monotonicity
−10V≤VREF
LJ & LCJ
4
7
8
8
8
bits
bits
≤+10V
LCN, LCWM & LCV
8
±
±
±
1
Gain Error Max
Using Internal Rfb
−10V≤VREF≤+10V
Using internal Rfb
0.2
1
% FS
Gain Error Tempco Max
Power Supply Rejection
0.0002
0.0006
%
FS/˚C
All digital inputs latched high
=
VCC 14.5V to 15.5V
0.0002
0.0006
0.013
15
0.0025
%
11.5V to 12.5V
4.5V to 5.5V
FSR/V
0.015
20
Reference
Input
Max
Min
20
10
kΩ
kΩ
15
10
=
=
Output Feedthrough Error
VREF 20 Vp-p, f 100 kHz
All data inputs latched low
3
mVp-p
3
www.national.com
Electrical Characteristics (Continued)
=
VREF 10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
=
TA 25˚C.
=
±
VCC 5 VDC 5%
=
VCC 4.75 VDC
=
±
VCC 12 VDC 5%
=
VCC 15.75 VDC
±
to 15 VDC 5%
See
Note
Limit
Units
Parameter
Conditions
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Typ
(Note 12)
CONVERTER CHARACTERISTICS
Output Leakage
Current Max
IOUT1
All data inputs
latched low
LJ & LCJ
10
100
50
100
100
100
100
nA
nA
pF
pF
LCN, LCWM & LCV
IOUT2
All data inputs
latched high
All data inputs
latched low
LJ & LCJ
100
50
LCN, LCWM & LCV
Output
IOUT1
IOUT2
IOUT1
IOUT2
45
115
130
30
Capacitance
All data inputs
latched high
DIGITAL AND DC CHARACTERISTICS
Digital Input
Voltages
Max
Logic Low
LJ: 4.75V
0.6
0.8
0.7
0.8
0.95
2.0
1.9
LJ: 15.75V
LCJ: 4.75V
LCJ: 15.75V
LCN, LCWM, LCV
LJ & LCJ
VDC
0.8
2.0
2.0
Min
Logic High
VDC
LCN, LCWM, LCV
<
Digital Input
Currents
Max
Digital inputs 0.8V
LJ & LCJ
−50
−200
−200
−200
µA
µA
LCN, LCWM, LCV
−160
>
Digital inputs 2.0V
LJ & LCJ
0.1
1.2
+10
+8
+10
+10
3.5
µA
LCN, LCWM, LCV
LJ & LCJ
Supply Current
Drain
Max
3.5
1.7
mA
LCN, LCWM, LCV
2.0
Electrical Characteristics
=
VREF 10.000 VDC unless otherwise noted. Boldface limits apply over temperature, TMIN≤TA≤TMAX. For all other limits
=
TA 25˚C.
=
=
5
±
VCC 12 VDC 5%
VCC
=
=
VCC 4.75 VDC
VCC 15.75 VDC
±
±
to 15 VDC 5%
VDC 5%
See
Note
Limit
Units
Symbol
Parameter
Conditions
Tested
Limit
(Note 5)
Tested
Limit
(Note 5)
Design
Limit
(Note 6)
Typ
(Note 12)
Design Limit
(Note 6)
Typ
(Note 12)
AC CHARACTERISTICS
=
=
ts
Current Setting
Time
VIL 0V, VIH 5V
1.0
100
100
1.0
375
375
µs
=
=
tW
Write and XFER
Pulse Width Min
Data Setup Time
Min
VIL 0V, VIH 5V
11
9
250
320
250
320
30
600
900
600
900
50
320
320
900
900
=
=
tDS
tDH
tCS
tCH
VIL 0V, VIH 5V
9
=
=
Data Hold Time
Min
VIL 0V, VIH 5V
9
9
9
ns
30
50
=
=
Control Setup Time
Min
VIL 0V, VIH 5V
110
0
250
320
0
600
0
900
1100
0
320
10
1100
= =
VIL 0V, VIH 5V
Control Hold Time
Min
0
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
www.national.com
4
Electrical Characteristics (Continued)
Note 3: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
, θ , and the ambient temperature, T . The maximum
JMAX JA
A
=
allowable power dissipation at any temperature is P
(T
JMAX
− T )/θ or the number given in the Absolute Maximum Ratings, whichever is lower. For this device,
JA
D
A
=
T
125˚C (plastic) or 150˚C (ceramic), and the typical junction-to-ambient thermal resistance of the J package when board mounted is 80˚C/W. For the N pack-
age, this number increases to 100˚C/W and for the V package this number is 120˚C/W.
Note 4: For current switching applications, both I and I must go to ground or the “Virtual Ground” of an operational amplifier. The linearity error is degraded
JMAX
OUT1
OUT2
÷
=
10V then a 1 mV offset, V , on I
OS OUT1
by approximately V
OS
V
. For example, if V
REF REF
or I will introduce an additional 0.01% linearity error.
OUT2
Note 5: Tested limits are guaranteed to National’s AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
=
=
±
1 V
DC
±
Note 7: Guaranteed at V
REF
10 V
DC
and V
REF
.
Note 8: The unit “FSR” stands for “Full Scale Range.” “Linearity Error” and “Power Supply Rejection” specs are based on this unit to eliminate dependence on a par-
ticular V value and to indicate the true performance of the part. The “Linearity Error” specification of the DAC0830 is “0.05% of FSR (MAX)”. This guarantees that
REF
after performing a zero and full scale adjustment (see Sections 2.5 and 2.6), the plot of the 256 analog voltage outputs will each be within 0.05%xV
line which passes through zero and full scale.
of a straight
REF
Note 9: Boldface tested limits apply to the LJ and LCJ suffix parts only.
−9
=
10V corresponds to a zero error of (100x10 x20x10 )x100/10 which is 0.02% of FS.
3
=
Note 10: A 100nA leakage current with R 20k and V
fb REF
Note 11: The entire write pulse must occur within the valid data interval for the specified t , t , t , and t to apply.
DS DH
W
S
Note 12: Typicals are at 25˚C and represent most likely parametric norm.
Note 13: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Switching Waveform
DS005608-2
5
www.national.com
vided on the IC chip for use as the shunt feedback
resistor for the external op amp which is used to
provide an output voltage for the DAC. This on-
chip resistor should always be used (not an exter-
nal resistor) since it matches the resistors which
are used in the on-chip R-2R ladder and tracks
these resistors over temperature.
Definition of Package Pinouts
Control Signals (All control signals level actuated)
CS:
Chip Select (active low). The CS in combination
with ILE will enable WR1.
ILE:
Input Latch Enable (active high). The ILE in combi-
nation with CS enables WR1.
VREF
:
Reference Voltage Input. This input connects an
external precision voltage source to the internal
R-2R ladder. VREF can be selected over the range
of +10 to −10V. This is also the analog voltage in-
put for a 4-quadrant multiplying DAC application.
WR1: Write 1. The active low WR1 is used to load the digi-
tal input data bits (DI) into the input latch. The data
in the input latch is latched when WR1 is high. To
update the input latch–CS and WR1 must be low
while ILE is high.
VCC
:
Digital Supply Voltage. This is the power supply
WR2: Write 2 (active low). This signal, in combination with
XFER, causes the 8-bit data which is available in
the input latch to transfer to the DAC register.
pin for the part. VCC can be from +5 to +15VDC
Operation is optimum for +15VDC
.
GND:
The pin 10 voltage must be at the same ground
potential as IOUT1 and IOUT2 for current switching
applications. Any difference of potential (VOS pin
10) will result in a linearity change of
XFER: Transfer control signal (active low). The XFER will
enable WR2.
Other Pin Functions
DI0-DI7: Digital Inputs. DI0 is the least significant bit (LSB)
and DI7 is the most significant bit (MSB).
IOUT1
:
DAC Current Output 1. IOUT1 is a maximum for a
digital code of all 1’s in the DAC register, and is
zero for all 0’s in DAC register.
For example, if VREF = 10V and pin 10 is 9mV offset from
IOUT1 and IOUT2 the linearity change will be 0.03%.
IOUT2
:
DAC Current Output 2. IOUT2 is a constant minus
±
Pin 3 can be offset 100mV with no linearity change, but the
=
I
OUT1 , or IOUT1 + IOUT2 constant (I full scale for
logic input threshold will shift.
a fixed reference voltage).
Rfb
:
Feedback Resistor. The feedback resistor is pro-
Linearity Error
DS005608-23
DS005608-24
a) End point test after
DS005608-25
b) Best straight line
zero and fs adj.
c) Shifting fs adj. to pass
best straight line test
Definition of Terms
Resolution: Resolution is directly related to the number of
switches or bits within the DAC. For example, the DAC0830
has 28 or 256 steps and therefore has 8-bit resolution.
iterations of the adjustment.) The “end point test’’ uses a
standard zero and F.S. adjustment procedure and is a much
more stringent test for DAC linearity.
Linearity Error: Linearity Error is the maximum deviation
from a straight line passing through the endpoints of the
DAC transfer characteristic. It is measured after adjusting for
zero and full-scale. Linearity error is a parameter intrinsic to
the device and cannot be externally adjusted.
Power Supply Sensitivity: Power supply sensitivity is a
measure of the effect of power supply changes on the DAC
full-scale output.
Settling Time: Settling time is the time required from a code
1
±
transition until the DAC output reaches within
⁄
2LSB of the
National’s linearity “end point test” (a) and the “best straight
line” test (b,c) used by other suppliers are illustrated above.
The “end point test’’ greatly simplifies the adjustment proce-
dure by eliminating the need for multiple iterations of check-
ing the linearity and then adjusting full scale until the linearity
is met. The “end point test’’ guarantees that linearity is met
after a single full scale adjust. (One adjustment vs. multiple
final output value. Full-scale settling time requires a zero to
full-scale or full-scale to zero output change.
Full Scale Error: Full scale error is a measure of the output
error between an ideal DAC and the actual device output.
Ideally, for the DAC0830 series, full scale is VREF −1LSB.
=
=
For VREF
10V and unipolar operation, VFULL-SCALE
10,0000V–39mV 9.961V. Full-scale error is adjustable to
zero.
www.national.com
6
Monotonic: If the output of a DAC increases for increasing
digital input code, then the DAC is monotonic. An 8-bit DAC
which is monotonic to 8 bits simply means that increasing
digital input codes will produce an increasing analog output.
Definition of Terms (Continued)
Differential Nonlinearity: The difference between any two
consecutive codes in the transfer curve from the theoretical
1 LSB to differential nonlinearity.
DS005608-4
FIGURE 1. DAC0830 Functional Diagram
Typical Performance Characteristics
Digital Input Threshold
vs. Temperature
Digital Input Threshold
vs. VCC
Gain and Linearity Error
Variation vs. Temperature
DS005608-26
DS005608-27
DS005608-28
7
www.national.com
Typical Performance Characteristics (Continued)
Gain and Linearity Error
Data Hold Time
Write Pulse Width
Variation vs. Supply Voltage
DS005608-31
DS005608-30
DS005608-29
The timing requirements and logic level convention of the
register control signals have been designed to minimize or
eliminate external interfacing logic when applied to most
popular microprocessors and development systems. It is
easy to think of these converters as 8-bit “write-only”
memory locations that provide an analog output quantity. All
inputs to these DAC’s meet TTL voltage level specs and can
also be driven directly with high voltage CMOS logic in
non-microprocessor based systems. To prevent damage to
the chip from static discharge, all unused digital inputs
should be tied to VCC or ground. If any of the digital inputs
are inadvertantly left floating, the DAC interprets the pin as a
logic “1”.
DAC0830 Series Application Hints
These DAC’s are the industry’s first microprocessor compat-
ible, double-buffered 8-bit multiplying D to A converters.
Double-buffering allows the utmost application flexibility from
a digital control point of view. This 20-pin device is also pin
for pin compatible (with one exception) with the DAC1230, a
12-bit MICRO-DAC. In the event that a system’s analog out-
put resolution and accuracy must be upgraded, substituting
the DAC1230 can be easily accomplished. By tying address
bit A0 to the ILE pin, a two-byte µP write instruction (double
precision) which automatically increments the address for
=
the second byte write (starting with A0 “1”) can be used.
This allows either an 8-bit or the 12-bit part to be used with
no hardware or software changes. For the simplest 8-bit ap-
plication, this pin should be tied to VCC (also see other uses
in section 1.1).
1.1 Double-Buffered Operation
Updating the analog output of these DAC’s in
a
double-buffered manner is basically a two step or double
write operation. In a microprocessor system two unique sys-
tem addresses must be decoded, one for the input latch con-
trolled by the CS pin and a second for the DAC latch which
is controlled by the XFER line. If more than one DAC is being
driven, Figure 2, the CS line of each DAC would typically be
decoded individually, but all of the converters could share a
common XFER address to allow simultaneous updating of
any number of DAC’s. The timing for this operation is shown,
Figure 3.
Analog signal control versatility is provided by a precision
R-2R ladder network which allows full 4-quadrant multiplica-
tion of a wide range bipolar reference voltage by an applied
digital word.
1.0 DIGITAL CONSIDERATIONS
A most unique characteristic of these DAC’s is that the 8-bit
digital input byte is double-buffered. This means that the
data must transfer through two independently controlled 8-bit
latching registers before being applied to the R-2R ladder
network to change the analog output. The addition of a sec-
ond register allows two useful control features. First, any
DAC in a system can simultaneously hold the current DAC
data in one register (DAC register) and the next data word in
the second register (input register) to allow fast updating of
the DAC output on demand. Second, and probably more im-
portant, double-buffering allows any number of DAC’s in a
system to be updated to their new analog output levels si-
multaneously via a common strobe signal.
It is important to note that the analog outputs that will change
after a simultaneous transfer are those from the DAC’s
whose input register had been modified prior to the XFER
command.
www.national.com
8
DAC0830 Series Application Hints (Continued)
DS005608-35
*
TIE TO LOGIC 1 IF NOT NEEDED (SEE SEC. 1.1).
FIGURE 2. Controlling Mutiple DACs
DS005608-36
FIGURE 3.
The ILE pin is an active high chip select which can be de-
coded from the address bus as a qualifier for the normal CS
signal generated during a write operation. This can be used
to provide a higher degree of decoding unique control sig-
nals for a particular DAC, and thereby create a more efficient
addressing scheme.
controlling the DAC’s to take over control of the data bus and
control lines. If this second system were to use the same ad-
dresses as those decoded for DAC control (but for a different
purpose) the ILE function would prevent the DAC’s from be-
ing erroneously altered.
In a “Stand-Alone” system the control signals are generated
by discrete logic. In this case double-buffering can be con-
trolled by simply taking CS and XFER to a logic “0”, ILE to a
logic “1” and pulling WR1 low to load data to the input latch.
Pulling WR2 low will then update the analog output. A logic
“1” on either of these lines will prevent the changing of the
analog output.
Another useful application of the ILE pin of each DAC in a
multiple DAC system is to tie these inputs together and use
this as a control line that can effectively “freeze” the outputs
of all the DAC’s at their present value. Pulling this line low
latches the input register and prevents new data from being
written to the DAC. This can be particularly useful in multi-
processing systems to allow a processor other than the one
9
www.national.com
DAC0830 Series Application Hints (Continued)
DS005608-7
=
ILE LOGIC “1”; WR2 and XFER GROUNDED
FIGURE 4.
1.2 Single-Buffered Operation
or erroneous data can be latched. This hold time is defined
as the length of time data must be held valid on the digital in-
puts after a qualified (via CS) WR strobe makes a low to high
transition to latch the applied data.
In a microprocessor controlled system where maximum data
throughput to the DAC is of primary concern, or when only
one DAC of several needs to be updated at a time, a
single-buffered configuration can be used. One of the two in-
ternal registers allows the data to flow through and the other
register will serve as the data latch.
If the controlling device or system does not inherently meet
these timing specs the DAC can be treated as a slow
memory or peripheral and utilize a technique to extend the
write strobe. A simple extension of the write time, by adding
a wait state, can simultaneously hold the write strobe active
and data valid on the bus to satisfy the minimum WR pulse-
width. If this does not provide a sufficient data hold time at
Digital signal feedthrough (see Section 1.5) is minimized if
the input register is used as the data latch. Timing for this
mode is shown in Figure 4.
Single-buffering in a “stand-alone” system is achieved by
strobing WR1 low to update the DAC with CS, WR2 and
XFER grounded and ILE tied high.
the end of the write cycle,
a negative edge triggered
one-shot can be included between the system write strobe
and the WR pin of the DAC. This is illustrated in Figure 5 for
an exemplary system which provides a 250ns WR strobe
time with a data hold time of less than 10ns.
1.3 Flow-Through Operation
Though primarily designed to provide microprocessor inter-
face compatibility, the MICRO-DAC’s can easily be config-
ured to allow the analog output to continuously reflect the
state of an applied digital input. This is most useful in appli-
cations where the DAC is used in a continuous feedback
control loop and is driven by a binary up-down counter, or in
function generation circuits where a ROM is continuously
providing DAC data.
The proper data set-up time prior to the latching edge (LO to
HI transition) of the WR strobe, is insured if the WR pulse-
width is within spec and the data is valid on the bus for the
duration of the DAC WR strobe.
1.5 Digital Signal Feedthrough
When data is latched in the internal registers, but the digital
inputs are changing state, a narrow spike of current may flow
out of the current output terminals. This spike is caused by
the rapid switching of internal logic gates that are responding
to the input changes.
Simply grounding CS, WR1, WR2, and XFER and tying ILE
high allows both internal registers to follow the applied digital
inputs (flow-through) and directly affect the DAC analog out-
put.
There are several recommendations to minimize this effect.
When latching data in the DAC, always use the input register
as the latch. Second, reducing the VCC supply for the DAC
from +15V to +5V offers a factor of 5 improvement in the
magnitude of the feedthrough, but at the expense of internal
logic switching speed. Finally, increasing CC (Figure 8) to a
value consistent with the actual circuit bandwidth require-
ments can provide a substantial damping effect on any out-
put spikes.
1.4 Control Signal Timing
When interfacing these MICRO-DAC to any microprocessor,
there are two important time relationships that must be con-
sidered to insure proper operation. The first is the minimum
WR strobe pulse width which is specified as 900 ns for all
valid operating conditions of supply voltage and ambient
temperature, but typically a pulse width of only 180ns is ad-
=
equate if VCC 15VDC. A second consideration is that the
guaranteed minimum data hold time of 50ns should be met
www.national.com
10
DAC0830 Series Application Hints (Continued)
DS005608-8
FIGURE 5. Accommodating a High Speed System
2.0 ANALOG CONSIDERATIONS
put level (“1” or “0”) respectively, as shown in Figure 6. The
MOS switches operate in the current mode with a small volt-
age drop across them and can therefore switch currents of
either polarity. This is the basis for the 4-quadrant multiplying
feature of this DAC.
The fundamental purpose of any D to A converter is to pro-
vide an accurate analog output quantity which is representa-
tive of the applied digital word. In the case of the DAC0830,
the output, IOUT1, is a current directly proportional to the
product of the applied reference voltage and the digital input
word. For application versatility, a second output, IOUT2, is
provided as a current directly proportional to the complement
of the digital input. Basically:
2.2 Basic Unipolar Output Voltage
To maintain linearity of output current with changes in the ap-
plied digital code, it is important that the voltages at both of
the current output pins be as near ground potential (0VDC
)
=
as possible. With VREF +10V every millivolt appearing at ei-
ther IOUT1 or IOUT2 will cause a 0.01% linearity error. In most
applications this output current is converted to a voltage by
using an op amp as shown in Figure 7.
The inverting input of the op amp is a “virtual ground” created
by the feedback from its output through the internal 15 kΩ re-
sistor, Rfb. All of the output current (determined by the digital
input and the reference voltage) will flow through Rfb to the
output of the amplifier. Two-quadrant operation can be ob-
tained by reversing the polarity of VREF thus causing IOUT1 to
flow into the DAC and be sourced from the output of the am-
plifier. The output voltage, in either case, is always equal to
where the digital input is the decimal (base 10) equivalent of
the applied 8-bit binary word (0 to 255), VREF is the voltage
at pin 8 and 15 kΩ is the nominal value of the internal resis-
tance, R, of the R-2R ladder network (discussed in Section
2.1).
Several factors external to the DAC itself must be consid-
ered to maintain analog accuracy and are covered in subse-
quent sections.
I
OUT1xRfb and is the opposite polarity of the reference volt-
age.
The reference can be either a stable DC voltage source or
an AC signal anywhere in the range from −10V to +10V. The
DAC can be thought of as a digitally controlled attenuator:
the output voltage is always less than or equal to the applied
reference voltage. The VREF terminal of the device presents
a nominal impedance of 15 kΩ to ground to external circuitry.
2.1 The Current Switching R-2R Ladder
The analog circuitry, Figure 6, consists of a silicon-chromium
(SiCr or Si-chrome) thin film R-2R ladder which is deposited
on the surface oxide of the monolithic chip. As a result, there
are no parasitic diode problems with the ladder (as there
may be with diffused resistors) so the reference voltage,
Always use the internal Rfb resistor to create an output volt-
age since this resistor matches (and tracks with tempera-
ture) the value of the resistors used to generate the output
current (IOUT1).
V
REF, can range −10V to +10V even if VCC for the device is
5VDC
.
The digital input code to the DAC simply controls the position
of the SPDT current switches and steers the available ladder
current to either IOUT1 or IOUT2 as determined by the logic in-
11
www.national.com
DAC0830 Series Application Hints (Continued)
DS005608-37
FIGURE 6.
DS005608-38
FIGURE 7.
2.3 Op Amp Considerations
This configuration features several improvements over exist-
ing circuits for bipolar outputs with other multiplying DACs.
Only the offset voltage of amplifier 1 has to be nulled to pre-
serve linearity of the DAC. The offset voltage error of the
second op amp (although a constant output voltage error)
has no effect on linearity. It should be nulled only if absolute
output accuracy is required. Finally, the values of the resis-
tors around the second amplifier do not have to match the in-
ternal DAC resistors, they need only to match and tempera-
ture track each other. A thin film 4-resistor network available
from Beckman Instruments, Inc. (part no. 694-3-R10K-D) is
ideally suited for this application. These resistors are
matched to 0.1% and exhibit only 5 ppm/˚C resistance track-
ing temperature coefficient. Two of the four available 10 kΩ
resistors can be paralleled to form R in Figure 9 and the
other two can be used independently as the resistances la-
beled 2R.
The op amp used in Figure 7 should have offset voltage null-
ing capability (See Section 2.5).
The selected op amp should have as low a value of input
bias current as possible. The product of the bias current
times the feedback resistance creates an output voltage er-
ror which can be significant in low reference voltage applica-
™
tions. BI-FET op amps are highly recommended for use
with these DACs because of their very low input current.
Transient response and settling time of the op amp are im-
portant in fast data throughput applications. The largest sta-
bility problem is the feedback pole created by the feedback
resistance, Rfb, and the output capacitance of the DAC. This
appears from the op amp output to the (−) input and includes
the stray capacitance at this node. Addition of a lead capaci-
tance, CC in Figure 8, greatly reduces overshoot and ringing
at the output for a step change in DAC output current.
Finally, the output voltage swing of the amplifier must be
greater than VREF to allow reaching the full scale output volt-
age. Depending on the loading on the output of the amplifier
2.5 Zero Adjustment
For accurate conversions, the input offset voltage of the out-
put amplifier must always be nulled. Amplifier offset errors
create an overall degradation of DAC linearity.
±
and the available op amp supply voltages (only 12 volts in
many development systems), a reference voltage less than
10 volts may be necessary to obtain the full analog output
voltage range.
The fundamental purpose of zeroing is to make the voltage
appearing at the DAC outputs as near 0VDC as possible.
This is accomplished for the typical DAC — op amp connec-
tion (Figure 7) by shorting out Rfb, the amplifier feedback re-
sistor, and adjusting the VOS nulling potentiometer of the op
amp until the output reads zero volts. This is done, of course,
with an applied digital code of all zeros if IOUT1 is driving the
op amp (all one’s for IOUT2). The short around Rfb is then re-
moved and the converter is zero adjusted.
2.4 Bipolar Output Voltage with a Fixed Reference
The addition of a second op amp to the previous circuitry can
be used to generate a bipolar output voltage from a fixed ref-
erence voltage. This, in effect, gives sign significance to the
MSB of the digital input word and allows two-quadrant multi-
plication of the reference voltage. The polarity of the refer-
ence can also be reversed to realize full 4-quadrant multipli-
=
±
±
x Digital Code VOUT. This circuit is shown
±
cation: VREF
in Figure 9.
www.national.com
12
DAC0830 Series Application Hints (Continued)
DS005608-39
ts
OP Amp
LF356
CC
(O to Full Scale)
22 pF
22 pF
10 pF
4 µs
5 µs
2 µs
LF351
LF357
*
*2.4 kΩ RESISTOR ADDED FROM−INPUT TO GROUND TO
INSURE STABILITY
FIGURE 8.
DS005608-40
Input Code
IDEAL VOUT
MSB
LSB
+VREF
−VREF
1
1
1
0
1
1
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
0
0
1
1
0
0
0
*THESE RESISTORS ARE AVAILABLE FROM BECKMAN INSTRUMENTS, INC. AS THEIR PART NO. 694-3-R10K-D
FIGURE 9.
2.6 Full-Scale Adjustment
In the case where the matching of Rfb to the R value of the
resistors, their temperature coefficients ideally would have to
match that of the internal DAC resistors, which is a highly im-
practical constraint. For the values shown in Figure 10, if the
resistor and the potentiometer each had a temperature coef-
±
R-2R ladder (typically 0.2%) is insufficient for full-scale ac-
curacy in a particular application, the VREF voltage can be
adjusted or an external resistor and potentiometer can be
added as shown in Figure 10 to provide a full-scale adjust-
ment.
±
ficient of 100 ppm/˚C maximum, the overall gain error tem-
perature coefficent would be degraded maximum of
0.0025%/˚C for an adjustment pot setting of less than 3% of
Rfb
a
.
The temperature coefficients of the resistors used for this ad-
justment are of an important concern. To prevent degrada-
tion of the gain error temperature coefficient by the external
13
www.national.com
The reference voltage is connected to one of the current out-
put terminals (IOUT1 for true binary digital control, IOUT2 is for
complementary binary) and the output voltage is taken from
the normal VREF pin. The converter output is now a voltage
in the range from 0V to 255/256 VREF as a function of the ap-
plied digital code as shown in Figure 11.
DAC0830 Series Application Hints
(Continued)
2.7 Using the DAC0830 in a Voltage Switching
Configuration
The R-2R ladder can also be operated as a voltage switch-
ing network. In this mode the ladder is used in an inverted
manner from the standard current switching configuration.
DS005608-11
FIGURE 10. Adding Full-Scale Adjustment
DS005608-12
FIGURE 11. Voltage Mode Switching
This configuration offers several useful application advan-
tages. Since the output is a voltage, an external op amp is
not necessarily required but the output impedance of the
DAC is fairly high (equal to the specified reference input re-
sistance of 10 kΩ to 20 kΩ) so an op amp may be used for
buffering purposes. Some of the advantages of this mode
are illustrated in Figures 12, 13, 14, 15.
There are two important things to keep in mind when using
this DAC in the voltage switching mode. The applied refer-
ence voltage must be positive since there are internal para-
sitic diodes from ground to the IOUT1 and IOUT2 terminals
which would turn on if the applied reference went negative.
There is also a dependence of conversion linearity and gain
error on the voltage difference between VCC and the voltage
applied to the normal current output terminals. This is a re-
sult of the voltage drive requirements of the ladder switches.
To ensure that all 8 switches turn on sufficiently (so as not to
add significant resistance to any leg of the ladder and
thereby introduce additional linearity and gain errors) it is
recommended that the applied reference voltage be kept
less than +5VDC and VCC be at least 9V more positive than
DS005608-41
•
•
Voltage switching mode eliminates output signal inver-
sion and therefore a need for a negative power supply.
Zero code output voltage is limited by the low level output
saturation voltage of the op amp. The 2 kΩ pull-down re-
sistor helps to reduce this voltage.
V
REF. These restrictions ensure less than 0.1% linearity and
gain error change. Figures 16, 17, 18 characterize the ef-
fects of bringing VREF and VCC closer together as well as
typical temperature performance of this voltage switching
configuration.
•
VOS of the op amp has no effect on DAC linearity.
FIGURE 12. Single Supply DAC
www.national.com
14
DAC0830 Series Application Hints (Continued)
DS005608-42
FIGURE 13. Obtaining a Bipolar Output from a Fixed
Reference with a Single Op Amp
DS005608-60
FIGURE 14. Bipolar Output with Increased Output Voltage Swing
15
www.national.com
DAC0830 Series Application Hints (Continued)
DS005608-14
FIGURE 15. Single Supply DAC with Level Shift and Span-
Adjustable Output
Gain and Linearity Error
Variation vs. Supply Voltage
Gain and Linearity Error
Variation vs. Reference Voltage
DS005608-32
DS005608-33
Note: For these curves, V
REF
is the voltage applied to pin 11 (I ) with
OUT1
FIGURE 17.
pin 12 (I
) grounded.
OUT2
FIGURE 16.
www.national.com
16
the output of the op amp to bias near the negative supply po-
tential. No harm is done to the DAC, however, as the on-chip
15 kΩ feedback resistor sufficiently limits the current flow
from IOUT1 when this lead is internally clamped to one diode
drop below ground.
DAC0830 Series Application Hints
(Continued)
Gain and Linearity Error
Variation vs. Temperature
Careful circuit construction with minimization of lead lengths
around the analog circuitry, is a primary concern. Good high
frequency supply decoupling will aid in preventing inadvert-
ant noise from appearing on the analog output.
Overall noise reduction and reference stability is of particular
concern when using the higher accuracy versions, the
DAC0830 and DAC0831, or their advantages are wasted.
3.0 GENERAL APPLICATION IDEAS
The connections for the control pins of the digital input regis-
ters are purposely omitted. Any of the control formats dis-
cussed in Section 1 of the accompanying text will work with
any of the circuits shown. The method used depends on the
overall system provisions and requirements.
DS005608-34
The digital input code is referred to as D and represents the
decimal equivalent value of the 8-bit binary input, for ex-
ample:
FIGURE 18.
2.8 Miscellaneous Application Hints
These converters are CMOS products and reasonable care
should be exercised in handling them to prevent catastrophic
failures due to static discharge.
Binary Input
D
Pin 13
MSB
Pin 7
LSB
Decimal
Equivalent
Conversion accuracy is only as good as the applied refer-
ence voltage so providing a stable source over time and tem-
perature changes is an important factor to consider.
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
1
0
1
0
0
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
255
128
16
2
0
0
1
0
A “good” ground is most desirable. A single point ground dis-
tribution technique for analog signals and supply returns
keeps other devices in a system from affecting the output of
the DACs.
0
During power-up supply voltage sequencing, the −15V (or
−12V) supply of the op amp may appear first. This will cause
17
www.national.com
Applications
DAC Controlled Amplifier (Volume Control)
Capacitance Multiplier
DS005608-43
DS005608-44
Variable fO, Variable QO, Constant BW Bandpass Filter
DS005608-17
www.national.com
18
Applications (Continued)
DAC Controlled Function Generator
DS005608-18
19
www.national.com
Applications (Continued)
Two Terminal Floating 4 to 20 mA Current Loop Controller
DS005608-19
=
DAC0830 linearly controls the current flow from the input terminal to the output terminal to be 4 mA (for D 0) to 19.94 mA (for
•
=
D
255).
•
•
•
Circuit operates with a terminal voltage differential of 16V to 55V.
P2 adjusts the magnitude of the output current and P1 adjusts the zero to full scale range of output current.
Digital inputs can be supplied from a processor using opto isolators on each input or the DAC latches can flow-through (con-
nect control lines to pins 3 and 10 of the DAC) and the input data can be set by SPST toggle switches to ground (pins 3 and
10).
www.national.com
20
Applications (Continued)
DAC Controlled Exponential Time Response
DS005608-20
=
Output responds exponentially to input changes and automatically stops when VOUT VIN
•
•
•
Output time constant is directly proportional to the DAC input code and capacitor C
Input voltage must be positive (See section 2.7)
Ordering Information
Temperature Range
0˚C to +70˚
−40˚C to
−55˚C to
+125˚C
+85˚C
0.05%
FSR
DAC0830LCN
DAC0830LCM
DAC0830LCV
DAC0832LCV
DAC0830LCJ
DAC0830LJ
Non
Linearity
0.1%
FSR
DAC0831LCN
DAC0832LCN
0.2%
FSR
DAC0832LCM
DAC0832LCJ
DAC0832LJ
Package Outline
N20A — Molded
DIP
M20B Small
Outline
V20A Chip Carrier
J20A — Ceramic DIP
21
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted
Ceramic Dual-In-Line Package (J)
Order Number DAC0830LCJ,
DAC0830LJ, DAC0832LJ or DAC0832LCJ
NS Package Number J20A
www.national.com
22
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Small Outline Package (M)
Order Number DAC0830LCM
or DAC0832LCM
NS Package Number M20B
Molded Dual-In-Line Package (N)
Order Number DAC0830LCN,
or DAC0832LCN
NS Package Number N20A
23
www.national.com
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Chip Carrier (V)
Order Number DAC0830LCV
or DAC0832LCV
NS Package Number V20A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL
COUNSEL OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
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2. A critical component is any component of a life
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National P/N DAC0830 - 8-bit Microprocessor Compatible, Double-Buffered D/A Converter
Products > Analog - Data Acquisition > Digital-to-Analog Converters > DAC0830
Product Folder
8-bit Microprocessor Compatible, Double-Buffered D/A Converter
DAC0830
Generic P/N 0830
Parametric Table
Contents
Resolution
Settling Time to 1/2 LSB (ns) 1000
Supply Voltage +5 V to +15 V
8-Bit
● General Description
● Features
● Key Specification
● Datasheet
● Package Availability, Models, Samples & Pricing
● Application Notes
General Description
The DAC0830 is an advanced CMOS/Si-Cr 8-bit multiplying DAC designed to interface directly with the
8080, 8048, 8085, Z80™, and other popular microprocessors. A deposited silicon-chromium R-2R
resistor ladder network divides the reference current and provides the circuit with excellent temperature
tracking characteristics (0.05% of Full Scale Range maximum linearity error over temperature). The
circuit uses CMOS current switches and control logic to achieve low power consumption and low output
leakage current errors. Special circuitry provides TTL logic input voltage level compatibility.
Double buffering allows these DACs to output a voltage corresponding to one digital word while holding
the next digital word. This permits the simultaneous updating of any number of DACs.
The DAC0830 series are the 8-bit members of a family of microprocessor-compatible DACs
(MICRO-DAC™).
Features
file:///d|/chechi/DAC0830.html (1 of 3) [10/11/2001 2:41:40 PM]
National P/N DAC0830 - 8-bit Microprocessor Compatible, Double-Buffered D/A Converter
● Double-buffered, single-buffered or flow-through digital data inputs
● Easy interchange and pin-compatible with 12-bit DAC1230 series
● Direct interface to all popular microprocessors
● Linearity specified with zero and full scale adjust only-NOT BEST STRAIGHT LINE FIT.
● Works with ±10V reference-full 4-quadrant multiplication
● Can be used in the voltage switching mode
● Logic inputs which meet TTL voltage level specs (1.4V logic threshold)
● Operates "STAND ALONE" (without µP) if desired
● Available in 20-pin small-outline or molded chip carrier package
Key Specification
● Current settling time: 1 µs
● Resolution: 8 bits
● Linearity: 8, 9, or 10 bits (guaranteed over temp.)
● Gain Tempco: 0.0002% FS/°C
● Low power dissipation: 20 mW
● Single power supply: 5 to 15 VDC
Datasheet
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(in
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DAC0830/DAC0832 8-Bit P Compatible, Double-Buffered D 532
30-Jun-99
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DAC0830/DAC0832 8-Bit P Compatible, Double-Buffered D
to A Converters (JAPANESE)
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Marking
&
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Status
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Orders
Type # pins
SPICE IBIS
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18
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National P/N DAC0830 - 8-bit Microprocessor Compatible, Double-Buffered D/A Converter
tray
of
N/A
Die
DAC0830 MDC
DAC0830 MWC
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Applying the New CMOS MICRO-DACs (JAPANESE)
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PARALLEL, 8 BITS INPUT LOADING, 1us SETTLING TIME, 8-BIT DAC, PQCC20, PLASTIC, CC-20
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