DAC0802 [NSC]
8-Bit Digital-to-Analog Converters; 8位数字 - 模拟转换器
| 型号： | DAC0802 |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Digital-to-Analog Converters |
| 文件： | 总11页 (文件大小：347K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1999
DAC0800/DAC0802
8-Bit Digital-to-Analog Converters
The DAC0800, DAC0802, DAC0800C and DAC0802C are a
direct replacement for the DAC-08, DAC-08A, DAC-08C,
and DAC-08H, respectively.
General Description
The DAC0800 series are monolithic 8-bit high-speed
current-output digital-to-analog converters (DAC) featuring
typical settling times of 100 ns. When used as a multiplying
DAC, monotonic performance over a 40 to 1 reference cur-
rent range is possible. The DAC0800 series also features
high compliance complementary current outputs to allow dif-
ferential output voltages of 20 Vp-p with simple resistor loads
as shown in Figure 1. The reference-to-full-scale current
Features
n Fast settling output current: 100 ns
±
n Full scale error:
1 LSB
±
n Nonlinearity over temperature:
0.1%
±
n Full scale current drift:
10 ppm/˚C
±
matching of better than 1 LSB eliminates the need for
n High output compliance: −10V to +18V
n Complementary current outputs
n Interface directly with TTL, CMOS, PMOS and others
n 2 quadrant wide range multiplying capability
full-scale trims in most applications while the nonlinearities
±
of better than 0.1% over temperature minimizes system er-
ror accumulations.
The noise immune inputs of the DAC0800 series will accept
TTL levels with the logic threshold pin, VLC, grounded.
Changing the VLC potential will allow direct interface to other
logic families. The performance and characteristics of the
±
±
4.5V to 18V
n Wide power supply range:
±
n Low power consumption: 33 mW at 5V
n Low cost
±
device are essentially unchanged over the full 4.5V to
±
18V power supply range; power dissipation is only 33 mW
±
with 5V supplies and is independent of the logic input
states.
Typical Applications
DS005686-1
±
FIGURE 1. 20 VP-P Output Digital-to-Analog Converter (Note 5)
Ordering Information
Non-Linearity
Temperature
Range
Order Numbers
J Package (J16A) (Note 1) N Package (N16E) (Note 1) SO Package (M16A)
±
0.1% FS
0˚C ≤ TA ≤ +70˚C
DAC0802LCJ DAC-08HQ DAC0802LCN DAC-08HP
DAC-08Q
DAC0800LCJ DAC-08EQ DAC0800LCN DAC-08EP
DAC0802LCM
±
±
0.19% FS
0.19% FS
−55˚C ≤ TA ≤ +125˚C DAC0800LJ
0˚C ≤ TA ≤ +70˚C
DAC0800LCM
Note 1: Devices may be ordered by using either order number.
© 1999 National Semiconductor Corporation
DS005686
www.national.com
Absolute Maximum Ratings (Note 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Storage Temperature
−65˚C to +150˚C
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
Dual-In-Line Package (ceramic)
Surface Mount Package
260˚C
300˚C
Supply Voltage (V+ − V−)
Power Dissipation (Note 3)
Reference Input Differential Voltage
(V14 to V15)
18V or 36V
500 mW
±
Vapor Phase (60 seconds)
Infrared (15 seconds)
215˚C
220˚C
V− to V+
Operating Conditions (Note 2)
Reference Input Common-Mode
Range (V14, V15)
V− to V+
5 mA
V− to V− plus 36V
Min
Max
Units
Reference Input Current
Logic Inputs
Temperature (TA)
DAC0800L
−55
0
+125
+70
˚C
˚C
˚C
Analog Current Outputs
DAC0800LC
DAC0802LC
=
(VS− −15V)
4.25 mA
TBD V
0
+70
ESD Susceptibility (Note 4)
Electrical Characteristics
=
.
=
15V, IREF 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output
±
The following specifications apply for VS
characteristics refer to both IOUT and IOUT
DAC0802LC
DAC0800L/
Symbol
Parameter
Conditions
DAC0800LC
Units
Min
8
Typ
8
Max
8
Min
8
Typ
8
Max
8
Resolution
Bits
Bits
%FS
ns
Monotonicity
Nonlinearity
Settling Time
8
8
8
8
8
8
±
±
0.19
0.1
1
±
ts
To
⁄
2
LSB, All Bits Switched
100
135
=
“ON” or “OFF”, TA 25˚C
DAC0800L
100
100
135
150
ns
ns
DAC0800LC
=
tPLH,
tPHL
Propagation Delay
Each Bit
TA 25˚C
35
35
60
60
35
35
60
60
ns
ns
All Bits Switched
Full Scale Tempco
Output Voltage Compliance
±
±
50
18
±
±
50
18
TCIFS
VOC
10
10
ppm/˚C
V
Full Scale Current Change
−10
−10
1
<
>
⁄2 LSB, ROUT 20 MΩ Typ
=
=
IFS4
Full Scale Current
VREF 10.000V, R14 5.000 kΩ
1.984
1.992
2.000
1.94
1.99
2.04
mA
=
=
R15 5.000 kΩ, TA 25˚C
±
±
±
±
IFSS
IZS
Full Scale Symmetry
Zero Scale Current
Output Current Range
IFS4−IFS2
0.5
4.0
1
8.0
µA
µA
0.1
1.0
0.2
2.0
2.0
2.0
IFSR
V− −5V
=
0
0
2.0
2.0
2.1
4.2
0
0
2.1
4.2
mA
mA
V− −8V to −18V
=
Logic Input Levels
Logic “0”
=
VIL
VIH
VLC 0V
0.8
0.8
V
V
Logic “1”
2.0
2.0
=
Logic Input Current
Logic “0”
VLC 0V
IIL
−10V≤VIN≤+0.8V
−2.0
−10
10
−2.0
−10
10
µA
µA
IIH
Logic “1”
2V≤VIN≤+18V
0.002
0.002
VIS
Logic Input Swing
Logic Threshold Range
Reference Bias Current
Reference Input Slew Rate
Power Supply Sensitivity
V− −15V
=
−10
−10
18
−10
−10
18
V
=
±
VTHR
I15
VS 15V
13.5
−3.0
13.5
−3.0
V
−1.0
8.0
−1.0
8.0
µA
dl/dt
PSSIFS+
PSSIFS−
(Figure 11)
4.0
4.0
mA/µs
%/%
%/%
4.5V≤V+≤18V
−4.5V≤V−≤18V
0.0001
0.0001
0.01
0.01
0.0001
0.0001
0.01
0.01
=
IREF 1mA
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2
Electrical Characteristics (Continued)
=
.
=
15V, IREF 2 mA and TMIN ≤ TA ≤ TMAX unless otherwise specified. Output
±
The following specifications apply for VS
characteristics refer to both IOUT and IOUT
DAC0802LC
Typ
DAC0800L/
DAC0800LC
Typ
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
=
=
±
Power Supply Current
VS 5V, IREF 1 mA
I+
I−
2.3
3.8
2.3
3.8
mA
mA
−4.3
−5.8
−4.3
−5.8
=
=
VS 5V, −15V, IREF 2 mA
I+
I−
2.4
3.8
2.4
3.8
mA
mA
−6.4
−7.8
−6.4
−7.8
=
=
±
VS 15V, IREF 2 mA
I+
2.5
−6.5
33
3.8
−7.8
48
2.5
−6.5
33
3.8
−7.8
48
mA
mA
I−
=
±
PD
Power Dissipation
5V, IREF 1 mA
mW
mW
mW
=
5V,−15V, IREF 2 mA
108
135
136
174
108
135
136
174
=
±
15V, IREF 2 mA
Note 2: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 3: The maximum junction temperature of the DAC0800 and DAC0802 is 125˚C. For operating at elevated temperatures, devices in the Dual-In-Line J package
must be derated based on a thermal resistance of 100˚C/W, junction-to-ambient, 175˚C/W for the molded Dual-In-Line N package and 100˚C/W for the Small Outline
M package.
Note 4: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
Note 5: Pin-out numbers for the DAC080X represent the Dual-In-Line package. The Small Outline package pin-out differs from the Dual-In-Line package.
Connection Diagrams
Dual-In-Line Package
Small Outline Package
DS005686-14
DS005686-13
Top View
Top View
See Ordering Information
3
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Block Diagram (Note 5)
DS005686-2
Typical Performance Characteristics
Full Scale Current
vs Reference Current
LSB Propagation Delay vs IFS
Reference Input
Frequency Response
DS005686-23
DS005686-24
DS005686-22
=
=
=
Curve 1: C 15 pF, V
2 Vp-p centered at 1V.
50 mVp-p centered at
C
IN
=
Curve 2: C 15 pF, V
C
IN
200 mV.
=
=
Curve 3: C 0 pF, V
100 mVp-p centered at
C
IN
0V and applied through 50Ω connected to pin
14.2V applied to R14.
Reference Amp
Common-Mode Range
Logic Input Current
vs Input Voltage
VTH — VLC vs Temperature
DS005686-27
DS005686-25
DS005686-26
Note. Positive common-mode range is always
(V+) − 1.5V.
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4
Typical Performance Characteristics (Continued)
Output Current vs Output
Output Voltage Compliance
Bit Transfer
Characteristics
Voltage (Output Voltage
vs Temperature
Compliance)
DS005686-29
DS005686-30
DS005686-28
Note. B1–B8 have identical transfer
characteristics. Bits are fully switched with less
1
±
⁄2 LSB error, at less than 100 mV from
than
actual threshold. These switching points are
guaranteed to lie between 0.8 and 2V over the
=
operating temperature range (V
0V).
LC
Power Supply Current
vs +V
Power Supply Current
vs −V
Power Supply Current
vs Temperature
DS005686-31
DS005686-32
DS005686-33
Equivalent Circuit
DS005686-15
FIGURE 2.
5
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Typical Applications
DS005686-5
=
I
+ I
O
I
for all logic states
O
FS
For fixed reference, TTL operation, typical values are:
=
=
V
R
10.000V
5.000k
REF
REF
R15 ≈ R
REF
=
C
C
0.01 µF
=
V
0V (Ground)
LC
FIGURE 3. Basic Positive Reference Operation (Note 5)
DS005686-16
DS005686-21
FIGURE 4. Recommended Full Scale Adjustment
Note. R
REF
sets I ; R15 is for bias current cancellation
FS
Circuit (Note 5)
FIGURE 5. Basic Negative Reference Operation
(Note 5)
DS005686-17
B1 B2 B3 B4 B5 B6 B7 B8 IO mA
IOmA
0.000
0.008
0.984
0.992
1.000
1.984
1.992
EO
EO
Full Scale
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
1.992
1.984
1.008
1.000
0.992
0.008
0.000
−9.960
−9.920
−5.040
−5.000
−4.960
−0.040
0.000
0.000
Full Scale−LSB
Half Scale+LSB
Half Scale
−0.040
−4.920
−4.960
−5.000
−9.920
−9.960
Half Scale−LSB
Zero Scale+LSB
Zero Scale
FIGURE 6. Basic Unipolar Negative Operation (Note 5)
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6
Typical Applications (Continued)
DS005686-6
B1 B2 B3 B4 B5 B6 B7 B8
EO
EO
Pos. Full Scale
Pos. Full Scale−LSB
Zero Scale+LSB
Zero Scale
1
1
1
1
0
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
1
0
0
1
0
0
1
0
1
0
1
1
0
−9.920 +10.000
−9.840 +9.920
−0.080 +0.160
0.000
+0.080
0.000
Zero Scale−LSB
Neg. Full Scale+LSB
Neg. Full Scale
+0.080
+9.920 −9.840
+10.000 −9.920
FIGURE 7. Basic Bipolar Output Operation (Note 5)
DS005686-18
=
±
If R
L
R
L
within 0.05%, output is symmetrical about ground
B1 B2 B3 B4 B5 B6 B7 B8
EO
Pos. Full Scale
Pos. Full Scale−LSB
(+)Zero Scale
1
1
1
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
+9.960
+9.880
+0.040
−0.040
−9.880
−9.960
(−)Zero Scale
Neg. Full Scale+LSB
Neg. Full Scale
FIGURE 8. Symmetrical Offset Binary Operation (Note 5)
DS005686-19
For complementary output (operation as negative logic DAC), connect inverting input of op amp to I (pin 2), connect I (pin 4) to ground.
O
O
FIGURE 9. Positive Low Impedance Output Operation (Note 5)
7
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Typical Applications (Continued)
DS005686-20
For complementary output (operation as a negative logic DAC) connect non-inverting input of op am to I (pin 2); connect I (pin 4) to ground.
O
O
FIGURE 10. Negative Low Impedance Output Operation (Note 5)
DS005686-10
=
=
10V
Typical values: R
IN
5k,+V
IN
FIGURE 11. Pulsed Reference Operation (Note 5)
DS005686-9
=
V
V
+ 1.4V
LC
TH
15V CMOS, HTL, HNIL
=
V
7.6V
TH
Note. Do not exceed negative logic input range of DAC.
FIGURE 12. Interfacing with Various Logic Families
DS005686-12
(b) +VREF must be above peak positive swing of VIN
DS005686-11
(a) IREF ≥ peak negative swing of IIN
FIGURE 13. Accommodating Bipolar References (Note 5)
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8
Typical Applications (Continued)
DS005686-7
FIGURE 14. Settling Time Measurement (Note 5)
DS005686-8
Note. For 1 µs conversion time with 8-bit resolution and 7-bit accuracy, an LM361 comparator replaces the LM319 and the reference current is doubled by
reducing R1, R2 and R3 to 2.5 kΩ and R4 to 2 MΩ.
FIGURE 15. A Complete 2 µs Conversion Time, 8-Bit A/D Converter (Note 5)
9
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Physical Dimensions inches (millimeters) unless otherwise noted
Molded Small Outline Package (SO)
Order Numbers DAC0800LCM,
or DAC0802LCM
NS Package Number M16A
Molded Small Outline Package (SO)
Order Numbers DAC0800LCM,
or DAC0802LCM
NS Package Number M16A
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10
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
Molded Dual-In-Line Package
Order Numbers DAC0800, DAC0802
NS Package Number N16E
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