CGS74CT2526N [NSC]
暂无描述;
| 型号： | CGS74CT2526N |
| 厂家： | 
National Semiconductor |
| 描述： | 暂无描述 时钟驱动器 |
| 文件： | 总10页 (文件大小：172K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1995
CGS74C2525 CGS74CT2525
#
CGS74C2526 CGS74CT2526
#
1-to-8 Minimum Skew Clock Driver
The CGS ’C/CT2525 is a minimum skew clock driver with
Features
Y
one input driving eight outputs specifically designed for sig-
nal generation and clock distribution applications. The ’2525
is designed to distribute a single clock to eight separate
receivers with low skew across all outputs during both the
These CGS devices implement National’s FACTTM
family
Y
Y
Y
Y
Y
Y
Y
Ideal for signal generation and clock distribution
Guaranteed pin to pin and part to part skew
Multiplexed clock input (’2526)
t
and t
transitions. The ’2526 is similar to the ’2525
PHL
PLH
but contains a multiplexed clock input to allow for systems
with dual clock speeds or systems where a separate test
clock has been implemented.
Guaranteed 2 kV minimum ESD protection
Symmetric output current drive of 24 mA for I /I
OL OH
’CT has TTL-compatible inputs
These products are identical to 74AC/ACT2525 and
2526
Y
Available as Mil/Aero versions
54AC/ACT2525
54AC/ACT2526
Logic Symbols
Connection Diagrams
’2525
Pin Assignment
for DIP and SOIC
’2525
TL/F/10684–1
’2526
TL/F/10684–3
’2526
TL/F/10684–2
TL/F/10684–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
FACTTM is a trademark of National Semiconductor Corporation.
C
1996 National Semiconductor Corporation
TL/F/10684
RRD-B30M106/Printed in U. S. A.
http://www.national.com
Functional Description
On the multiplexed clock device, the SEL pin is used to
determine which CLKn input will have an active effect on
Truth Tables
’2525
e
0, the CLK0 input is selected.
the outputs of the circuit. When SEL
e
1, the CLK1 input is
Inputs
CLK
Outputs
selected and when SEL
O –O
0
7
The non-selected CLKn input will not have any effect on the
logical output level of the circuit. The output pins act as a
single entity and will follow the state of the CLK or
CLK1/CLK0 pins when either the multiplexed (’2526) or the
straight (’2525) clock distribution chip is selected.
L
L
H
H
’2526
Inputs
CLK1
Outputs
O –O
Pin Description
CLK0
SEL
Pin Names
Description
0
7
L
H
X
X
X
X
L
L
L
L
H
L
CLK
Clock Input (’2525)
Clock Inputs (’2526)
Outputs
CLK0, CLK1
H
H
O –O
0
7
H
H
SEL
Clock Select (’2526)
e
e
e
L
Low Voltage Level
High Voltage Level
Immaterial
H
X
’2525
’2526
TL/F/10684–7
TL/F/10684–8
http://www.national.com
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage (V
‘C’
‘CT’
)
CC
2.0V to 6.0V
4.5V to 5.5V
b
a
0.5V to 7.0V
Supply Voltage (V
)
CC
DC Input Diode Current (I
)
IK
Input Voltage (V )
I
0V to V
0V to V
CC
e b
b
20 mA
V
I
V
I
0.5V
a
Output Voltage (V
)
O
CC
e
a
V
CC
0.5V
0.2 mA
Operating Temperature (T )
A
CGS74C/CT
54AC/ACT
b
b
a
0.5V)
DC Input Voltage (V )
I
0.5V to (V
0.5V to (V
CC
b
b
a
40 C to 85 C
§
55 C to 125 C
§
§
DC Output Diode Current (I
)
a
OK
§
e
e
b
V
V
0.5V
V
20 mA
a
20 mA
O
O
Input Rise and Fall Times Devices
)
a
0.5V
CC
(30% to 70% of V
CC
a
DC Output Voltage (V
DC Output Source
)
O
0.5V)
50 mA
50 MA
e
CC
V
3.3V
4.5V
5.5V
10.5 ns max
14.4 ns max
17.6 ns max
CC
g
g
or Sink Current (I
)
O
DC V
or Ground Current
Input Rise and Fall Times Devices
(0.8V to 2.0V)
CC
per Output Pin (I or I
CC
)
9.6 ns max
GND
)
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, without
exception, to ensure that the system design is reliable over its power supply,
temperature, and output/input loading variables. National does not recom-
mend operation of CGS circuits outside databook specifications.
b
a
65 C to 150 C
Storage Temperature (T
§
§
STG
Junction Temperature (i
Plastic (N) 14-Lead
Plastic (M) 14-Lead
Plastic (N) 16-Lead
Plastic (M) 16-Lead
)
JA
102 C/W
§
128 C/W
§
97 C/W
§
124 C/W
§
DC Electrical Characteristics for CGS74C and 54AC Family Devices
Over recommended operating conditions unless specified otherwise.
CGS74C 54AC
CGS74C
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
A
25 C
§
Units
Conditions
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
3.0
4.5
5.5
1.5
2.1
2.1
2.1
V
IH
OUT
b
2.25
2.75
3.15
3.85
3.15
3.85
3.15
3.85
V
V
V
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
3.0
4.5
5.5
1.5
0.9
0.9
0.9
V
OUT
0.1V
IL
b
0.1V
2.25
2.75
1.35
1.65
1.35
1.65
1.35
1.65
or V
CC
e b
50 mA
Minimum High Level
Output Voltage
(Note 2)
3.0
4.5
5.5
2.99
4.49
5.49
2.9
4.4
5.4
2.9
4.4
5.4
2.9
4.4
5.4
I
OH
OUT
e
V
IN
V or V
IL IH
b
b
b
3.0
4.5
5.5
2.56
3.86
4.86
2.4
3.7
4.7
2.46
3.76
4.76
12 mA
24 mA
24 mA
V
V
I
OH
e
50 mA
V
OL
Maximum Low Level
Output Voltage
(Note 2)
3.0
4.5
5.5
0.002
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
I
OUT
e
V
IN
V or V
IL IH
3.0
4.5
5.5
0.36
0.36
0.36
0.40
0.50
0.50
0.44
0.44
0.44
12 mA
24 mA
24 mA
V
I
OL
3
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DC Electrical Characteristics for CGS74C and 54AC Family Devices (Continued)
Over recommended operating conditions unless specified otherwise.
CGS74C 54AC
e a
CGS74C
e
e
T
A
V
T
CC
A
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
b a
40 C to 85 C
(V)
55 C to 125 C
§
§
§
§
Typ
Guaranteed Limits
I
Maximum Input
Leakage Current
(Note 3)
IN
g
g
g
e
V
I
5.5
0.1
1.0
1.0
mA
V
, GND
CC
e
I
I
Minimum Dynamic
Output Current
(Note 4)
5.5
5.5
50
75
mA
mA
V
V
1.65V Max
e
3.85V Min
OLD
OHD
OLD
b
b
50
75
OHD
I
Maximum Quiescent
Supply Current
(Note 3)
CC
e
or GND
mA
V
V
CC
IN
5.5
8.0
80.0
80.0
DC Electrical Characteristics for CGS74CT and 54ACT Family Devices
Over recommended operating conditions unless specified otherwise.
CGS74CT 54ACT
CGS74CT
e
e
T
A
V
T
CC
A
e a
Symbol
Parameter
T
25 C
§
Units
Conditions
A
b
a
55 C to 125 C
b a
40 C to 85 C
(V)
§
§
§
§
Typ
Guaranteed Limits
e
0.1V
V
V
V
Minimum High Level
Input Voltage
4.5
5.5
1.5
1.5
2.0
2.0
2.0
2.0
2.0
2.0
V
IH
OUT
V
V
V
b
or V
CC
0.1V
e
Maximum Low Level
Input Voltage
4.5
5.5
1.5
1.5
0.8
0.8
0.8
0.8
0.8
0.8
V
OUT
0.1V
IL
b
or V
CC
0.1V
Minimum High Level
Output Voltage
(Note 2)
4.5
5.5
4.49
5.49
4.4
5.4
4.4
5.4
4.4
5.4
OH
e b
I
50 mA
OUT
e
V
IN
V or V
IL IH
b
b
4.5
5.5
3.86
4.86
3.70
4.70
3.76
4.76
V
V
24 mA
I
OH
24 mA
V
OL
Maximum Low Level
Output Voltage
(Note 2)
4.5
5.5
0.001
0.001
0.1
0.1
0.1
0.1
0.1
0.1
e
I
50 mA
OUT
e
V
IN
V or V
IL IH
4.5
5.5
0.36
0.36
0.50
0.50
0.44
0.44
V
24 mA
24 mA
I
OL
I
Maximum Input
Leakage Current
IN
e
e
g
g
g
1.0
5.5
0.1
1.0
mA
V
V
V
, GND
I
CC
b
I
I
I
Maximum I /Input
CC
5.5
5.5
0.6
1.6
50
1.5
75
mA
mA
V
V
2.1V
CCT
OLD
OHD
I
CC
e
Minimum Dynamic
Output Current
(Note 4)
1.65V Max
e
3.85V Min
OLD
OHD
b
b
5.5
5.5
50
75
mA
V
I
Maximum Quiescent
Supply Current
(Note 5)
CC
e
or GND
V
V
IN
CC
8.0
160.0
80.0
mA
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4
AC Electrical Characteristics Over recommended operating conditions unless specified otherwise.
CGS74C
54AC
CGS74C
e b
40 C
V
CC
e b
T
55 C
T
§
to 125 C
§
A
A
e a
Range
(V)
T
25 C
§
50 pF
A
a
a
Symbol
Parameter
to 85 C
§
Units
§
50 pF
e
C
L
e
e
50 pF
C
C
L
L
(Note 6)
Min
Typ
Max
Min
Max
Min
Typ
Max
t
t
,
Propagation Delay
3.3
5.0
3.0
3.2
6.5
5.0
11.0
7.8
3.0
2.5
11.0
8.2
3.0
2.9
12.5
8.1
PLH
ns
ns
ns
CLK to O (’2525)
n
PHL
t
t
Propagation Delay
3.3
5.0
3.0
3.6
7.0
5.5
13.0
7.8
3.0
3.3
14.0
8.6
PLH,
CLKn to O (’2526)
n
PHL
t
t
,
Propagation Delay
3.3
5.0
3.0
4.0
8.0
6.5
14.0
8.5
3.0
3.5
15.0
9.5
PLH
SEL to O (’2526)
n
PHL
t
t
t
t
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
OSHL
OSLH
OST
PV
3.3
5.0
0.3
0.2
1.5
1.0
600
500
ps
ps
ns
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
3.3
5.0
0.3
0.2
1.5
1.0
600
500
Maximum Skew
Opposite Edge
Output-to-Output (Note 7)
Variation
1.5
1.0
5.0
0.4
1.0
1.0
Maximum Skew
Part-to-Part
’C2525
’CT2525
’C2526
5.0
5.0
5.0
3.5
5.0
3.0
4.0
4.0
ns
ns
ns
Variation (Note 8)
’CT2526
t
t
,
,
Maximum
rise
Rise/Fall Time
3.75
fall
(20% to 80% V
)
CC
t
t
Maximum
rise
Rise/Fall Time
0.9
1.1
ns
fall
(0.8V/2.0V and 2.0V/0.8V)
AC Electrical Characteristics Over recommended operating conditions unless specified otherwise.
CGS74CT
54ACT
CGS74CT
e b
40 C
V
CC
e b
T
55 C
T
§
to 125 C
§
A
A
e a
Range
(V)
T
25 C
§
50 pF
A
a
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
e
C
L
e
C
C
L
L
(Note 6)
Min
Typ
Max
Min
Max
Min
Max
t
,
Propagation Delay
PLH
5.0
5.0
4.6
6.5
8.5
9.0
4.0
10.1
12.4
ns
ns
t
CLK to O (’2525)
n
PHL
t
t
Propagation Delay
PLH,
5.8
11.1
5.1
CLKn to O (’2526)
n
PHL
5
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AC Electrical Characteristics
Over recommended operating conditions unless specified otherwise. (Continued)
CGS74CT
54ACT
e b
CGS74CT
e b
40 C
V
CC
T
55 C
T
A
§
to 125 C
§
A
e a
e
Range
(V)
T
25 C
§
A
a
e
a
e
Symbol
Parameter
to 85 C
Units
§
50 pF
§
50 pF
C
50 pF
L
C
C
L
L
(Note 6)
Min
Typ
Max
Min
Max
Min Typ Max
t
t
,
Propagation Delay
PLH
5.0
5.0
5.1
8.5
12.4
4.4
14.1
550
ns
ps
SEL to O (’2526)
n
PHL
t
t
t
t
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
OSHL
OSLH
OST
PV
0.2
Maximum Skew
Common Edge
Output-to-Output (Note 7)
Variation
5.0
5.0
0.2
0.4
550
1.0
ps
ns
Maximum Skew
Opposite Edge
Output-to-Output (Note 7)
Variation
Maximum Skew
Part-to-Part
AC2525
ACT2525
Variation (Note 8) AC2526
5.0
5.0
3.5
5.0
ns
ns
ACT2526
t
t
,
,
Maximum
rise
Rise/Fall Time
5.0
3.0
3.75
ns
ns
fall
(20% to 80% V
)
CC
t
t
Maximum
rise
Rise/Fall Time
0.9
1.1
fall
(0.8V/2.0V and 2.0V/0.8V)
Note 2: All outputs loaded; thresholds on input associated with output under test.
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V
Note 3: I and I
IN
.
CC
CC
@ @
for 54AC 25 C is identical to CGS74C 25 C.
§ §
I
CC
Note 4: Maximum test duration 2.0 ms, one output loaded at a time.
@ @
for 54ACT 25 C is identical to CGS74CT 25 C.
§ §
Note 5: I
CC
g
g
Note 6: Voltage Range 5.0 is 5.0V 0.5V, voltage range 3.3 is 3.3V 0.3V.
Note 7: Output-to-Output Skew is defined as the absolute value of the difference between the actual propagation delay for any outputs within the same packaged
device. The specifications apply to any outputs switching in the same direction either HIGH to LOW (t
@
are characterized and guaranteed by design 1 MHz.
) or LOW to HIGH (t
) or in opposite directions both
OSLH
OSHL
HL and LH (t
). t
OST OSHL
and t
OSLH
Note 8: Part-to-part skew is defined as the absolute value of the difference between the propagation delay for any outputs from device to device. The parameter is
Ý
specified for a given set of conditions (i.e., capacitive load, V , temperature,
CC
of outputs switching, etc.). Parameter guaranteed by design.
Note 9: Load capacitance includes the test jig.
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6
Capacitance
Symbol
Parameter
Input Capacitance
Typ
Units Conditions
e
e
e
C
C
C
4.5
pF
pF
pF
V
CC
V
CC
V
CC
5.0V
5.0V
5.0V
IN
Power Dissipation Capacitance (’2525) 820 pF–1.2 x 10b (f)*
18
PD
PD
Power Dissipation Capacitance (’2526) 820 pF–1.2 x 10b (f)*
18
e
*f
frequency
Recommended Maximum Power Dissipation (W)
e
e
T
A
T
25 C
§
85 C
§
A
LFPM
PDIP
1.105
1.493
1.71
SOIC
0.858
1.055
1.210
PDIP
0.528
0.714
0.820
SOIC
0.41
0
225
500
0.504
0.578
Timing Diagrams
TL/F/10684–27
TL/F/10684–28
Test Circuit
R
is 500X
is 50 pF for all prop delays and skew measurements.
L
C
L
TL/F/10684–29
7
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Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/10684–26
Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (M)
NS Package Number M14A
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Integrated Circuit (M)
NS Package Number M16A
14-Lead Plastic Dual-In-Line Package (N)
NS Package Number N14A
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (N)
NS Package Number N16E
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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Corporation
National Semiconductor
Europe
National Semiconductor
Hong Kong Ltd.
National Semiconductor
Japan Ltd.
a
1111 West Bardin Road
Arlington, TX 76017
Tel: 1(800) 272-9959
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@
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a
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a
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a
Fran3ais Tel: 49 (0) 180-532 93 58
a
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National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications.
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