CD4514BM [NSC]
4-Bit Latched/4-to-16 Line Decoders; 4位锁存/ 4至16线路解码器
| 型号： | CD4514BM |
| 厂家： | 
National Semiconductor |
| 描述： | 4-Bit Latched/4-to-16 Line Decoders |
| 文件： | 总7页 (文件大小：122K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1988
CD4514BM/CD4514BC, CD4515BM/CD4515BC
4-Bit Latched/4-to-16 Line Decoders
General Description
Features
Y
Wide supply voltage range
3.0V to 15V
0.45 V (typ.)
The CD4514B and CD4515B are 4-to-16 line decoders with
latched inputs implemented with complementary MOS
(CMOS) circuits constructed with N- and P-channel en-
hancement mode transistors. These circuits are primarily
used in decoding applications where low power dissipation
and/or high noise immunity is required.
Y
High noise immunity
DD
Y
Low power TTL
compatibility
fan out of 2
driving 74L
Y
Low quiescent power dissipation
0.025 mW/package
@
5.0 V
DC
Y
The CD4514B (output active high option) presents a logical
‘‘1’’ at the selected output, whereas the CD4515B presents
a logical ‘‘0’’ at the selected output. The input latches are
R–S type flip-flops, which hold the last input data presented
prior to the strobe transition from ‘‘1’’ to ‘‘0’’. This input data
is decoded and the corresponding output is activated. An
output inhibit line is also available.
Single supply operation
12
10 X typically
Y
Y
e
Plug-in replacement for MC14514, MC14515
Input impedance
Logic and Connection Diagrams
TL/F/5994–1
Dual-In-Line Package
Order Number CD4514B or CD4515B
TL/F/5994–2
Top View
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/5994
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions (Note 2)
DC Supply Voltage (V
)
DD
3V to 15V
0V to V
Input Voltage (V
)
IN
DD
b
a
0.5V to 18V
DC Supply Voltage (V
)
DD
Operating Temperature Range (T )
A
b
a
0.5V
Input Voltage (V
IN
)
0.5V to V
DD
b
b
a
55 C to 125 C
CD4514BM, CD4515BM
CD4514BC, CD4515BC
§
40 C to 85 C
§
§
b
a
65 C to 150 C
Storage Temperature Range (T )
S
§
§
a
§
Power Dissipation (P )
D
Dual-In-Line
Small Outline
700 mW
500 mW
Lead Temperature (T )
L
(Soldering, 10 seconds)
260 C
§
DC Electrical Characteristics CD4514BM, CD4515BM (Note 2)
b
a
a
55 C
25 C
125 C
§
§
§
Typ
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
Min
Max
e
e
e
e
V
I
Quiescent Device
Current
V
DD
V
DD
V
DD
5V, V
IN
10V, V
15V, V
or V
DD SS
5
10
20
0.005
0.010
0.015
5
10
20
150
300
600
mA
mA
mA
DD
e
V
or V
or V
IN
IN
DD
DD
SS
SS
e
V
k
e
e
V
V
V
V
Low Level
Output Voltage
V
V
V
V
V
5V, V
10V
, I
l
1 mA
0V
OL
OH
IL
IH
DD
O
l
e
e
e
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
DD
DD
DD
IL
15V
k
e
e
High Level
Output Voltage
V
V
V
V
V
DD
, I
1 mA
0V
IH
l
O
IL
l
e
e
e
5V, V
10V
15V
4.95
9.95
14.95
4.95
9.95
14.95
5
10
15
4.95
9.95
14.95
V
V
V
DD
DD
DD
e
0.5V or 4.5V
Low Level
Input Voltage
V
V
V
V
O
k
e
e
e
5V, I
10V, V
15V, V
1 mA
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
l
O
l
e
e
1.0V or 9.0V
1.5V or 13.5V
O
O
e
0.5V or 4.5V
High Level
Input Voltage
V
V
V
V
IH
O
k
e
e
e
5V, I
10V, V
15V, V
1 mA
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
DD
DD
DD
l
O
l
e
e
1.0V or 9.0V
1.5V or 13.5V
O
O
e
e
e
e
0.4V
I
I
I
Low Level Output
Current (Note 3)
V
V
V
5V, V
O
10V, V
15V, V
0.64
1.6
4.2
0.51
1.3
3.4
0.88
2.25
8.80
0.36
0.90
2.40
mA
mA
mA
OL
DD
DD
DD
e
e
0.5V
1.5V
O
O
e
e
e
e
5V, V
O
b
b
b
b
b
b
b
b
High Level Output
Current (Note 3)
V
DD
V
DD
V
DD
4.6V
0.64
0.51
0.88
2.25
8.80
0.36
0.90
2.40
mA
mA
mA
OH
IN
e
e
b
b
10V, V
15V, V
9.5V
13.5V
1.6
4.2
1.3
3.4
O
O
b
b
b
5
e
e
e
e
b
0.1
0.1
b
b
0.1
0.1
b
1.0
1.0
Input Current
V
DD
V
DD
15V, V
15V, V
0V
15V
10
mA
mA
IN
IN
10b
5
DC Electrical Characteristics CD4514BC, CD4515BC (Note 2)
b
a
a
85 C
40 C
25 C
§
§
Typ
§
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
Min
Max
e
e
e
e
V
I
Quiescent Device
Current
V
V
V
5V, V
IN
10V, V
15V, V
or V
DD SS
20
40
80
0.005
0.010
0.015
20
40
80
150
300
600
mA
mA
mA
DD
DD
DD
DD
e
V
or V
or V
IN
IN
e
DD
DD
SS
SS
e
V
e
k
V
Low Level
Output Voltage
V
I
0V, V
1 mA
V
DD
,
OL
IL
IH
l
O
l
e
e
e
V
DD
V
DD
V
DD
5V
10V
15V
0.05
0.05
0.05
0
0
0
0.05
0.05
0.05
0.05
0.05
0.05
V
V
V
e
IL
e
V
OH
High Level
Output Voltage
V
I
0V, V
1 mA
5V
10V
15V
V
DD
,
IH
k
l
O
l
e
V
V
V
4.95
9.95
14.95
4.95
9.95
14.95
5.0
10.0
15.0
4.95
9.95
14.95
V
V
V
DD
DD
DD
e
e
2
DC Electrical Characteristics CD4514BC, CD4515BC (Note 2) (Continued)
b
a
a
85 C
40 C
§
25 C
§
Typ
§
Symbol
Parameter
Conditions
Units
Min
Max
Min
Max
Min
Max
k
V
IL
Low Level
Input Voltage
I
O
1 mA
5V, V
10V, V
15V, V
l
l
e
e
e
e
0.5V or 4.5V
V
V
V
1.5
3.0
4.0
2.25
4.50
6.75
1.5
3.0
4.0
1.5
3.0
4.0
V
V
V
DD
DD
DD
O
e
1.0V or 9.0V
1.5V or 13.5V
O
e
O
k
1 mA
V
IH
High Level
Input Voltage
I
V
V
V
l
O
l
e
e
0.5V or 4.5V
5V, V
3.5
7.0
11.0
3.5
7.0
11.0
2.75
5.50
8.25
3.5
7.0
11.0
V
V
V
DD
DD
DD
O
e
e
e
1.0V or 9.0V
10V, V
15V, V
O
O
e
1.5V or 13.5V
e
e
e
e
0.4V
I
I
I
Low Level Output
Current (Note 3)
V
V
V
5V, V
O
10V, V
15V, V
0.52
1.3
3.6
0.44
1.1
3.0
0.88
2.25
8.8
0.36
0.90
2.4
mA
mA
mA
OL
OH
IN
DD
DD
DD
e
e
0.5V
1.5V
O
O
e
e
e
e
O
b
b
b
b
High Level Output
Current (Note 3)
V
DD
V
DD
V
DD
5V, V
10V, V
15V, V
4.6V
0.52
0.44
0.88
2.25
8.8
0.36
0.90
mA
mA
mA
e
e
b
b
b
b
b
b
9.5V
13.5V
1.3
3.6
1.1
3.0
O
O
b
b
2.4
b
10b
5
5
e
e
e
e
b
0.3
0.3
b
b
0.3
0.3
b
1.0
1.0
Input Current
V
DD
V
DD
15V, V
15V, V
0V
15V
10
mA
mA
IN
IN
AC Electrical Characteristics*
e
e
e
e
t 20 ns unless otherwise specified
f
All types C
50 pF, T
25 C, t
§
L
A
r
Symbol
Parameter
Transition Times
Conditions
Min
Typ
Max
Units
e
e
e
t
t
t
t
t
, t
THL TLH
V
DD
V
DD
V
DD
5V
10V
15V
100
50
40
200
100
80
ns
ns
ns
e
e
e
, t
PLH PHL
Propagation Delay Times
V
V
V
5V
10V
15V
550
225
150
1100
450
300
ns
ns
ns
DD
DD
DD
e
e
e
, t
PLH PHL
Inhibit Propagation
Delay Times
V
DD
V
DD
V
DD
5V
10V
15V
400
150
100
800
300
200
ns
ns
ns
e
e
e
Setup Time
V
DD
V
DD
V
DD
5V
10V
15V
125
50
38
250
100
75
ns
ns
ns
SU
e
e
e
Strobe Pulse Width
V
DD
V
DD
V
DD
5V
10V
15V
175
50
38
350
100
75
ns
ns
ns
WH
C
C
Power Dissipation Capacitance
Input Capacitance
Per Package (Note 5)
Any Input (Note 4)
150
5
pF
pF
PD
7.5
IN
*AC Parameters are guaranteed by DC correlated testing.
Note 1: ‘‘Absolute Maximum Ratings’’ are those values beyond which the safety of the device cannot be guaranteed. Except for ‘‘Operating Temperature Range’’
they are not meant to imply that the devices should be operated at these limits. The tables of ‘‘Recommended Operating Conditions’’ and ‘‘Electrical Characteris-
tics’’ provide conditions for actual device operation.
e
Note 2: V
0V unless otherwise specified.
and I are tested one output at a time.
SS
Note 3: I
OH
OL
Note 4: Capacitance is guaranteed by periodic testing.
Note 5: C determines the no load AC power consumption of any CMOS device. For complete explanation, see 54C and 74C Family Characteristics application
PD
note, AN-90.
3
Truth Table
e
Decode Truth Table (Strobe
Data Inputs
1)
Selected Output
e
e
Inhibit
CD4514
CD4515
Logic ‘‘1’’
Logic ‘‘0’’
D
C
B
A
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
1
S0
S1
S2
S3
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
S4
S5
S6
S7
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
S8
S9
S10
S11
0
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
S12
S13
S14
S15
e
e
1
X
X
X
X
All Outputs
All Outputs
0, CD4514
1, CD4515
e
X
Don’t Care
AC Test Circuit and Switching Time Waveforms
TL/F/5994–4
TL/F/5994–3
FIGURE 1
4
Applications
Two CD4512 8-channel data selectors are used here with
the CD4514B 4-bit latch/decoder to effect a complex data
routing system. A total of 16 inputs from data registers are
8 times faster than the shift frequency of the input registers,
the most significant bit (MSB) from each register could be
selected for transfer to the data bus. Therefore, all of the
most significant bits from all of the registers can be trans-
ferred to the data bus before the next most significant bit is
presented for transfer by the input registers.
selected and transferred via a TRI-STATE data bus to a
É
data distributor for rearrangement and entry into 16 output
registers. In this way sequential data can be re-routed or
intermixed according to patterns determined by data select
and distribution inputs.
Information from the TRI-STATE bus is redistributed by the
CD4514B 4-bit latch/decoder. Using the 4-bit address,
INA–IND, the information on the inhibit line can be trans-
ferred to the addressed output line to the desired output
registers, A–P. This distribution of data bits to the output
registers can be made in many complex patterns. For exam-
ple, all of the most significant bits from the input registers
can be routed into output register A, all of the next most
significant bits into register B, etc. In this way horizontal,
vertical, or other methods of data slicing can be implement-
ed.
Data is placed into the routing scheme via the 8 inputs on
both CD4512 data selectors. One register is assigned to
each input. The signals on A0, A1 and A2 choose 1-of-8
inputs for transfer out to the TRI-STATE data bus. A fourth
signal, labelled Dis, disables one of the CD4512 selectors,
assuring transfer of data from only one register.
In addition to a choice of input registers, 1–16, the rate of
transfer of the sequential information can also be varied.
That is, if the CD4512 were addressed at a rate that is
TL/F/5994–5
5
Physical Dimensions inches (millimeters)
Ceramic Dual-In-Line Package (J)
Order Number CD4514BMJ, CD4514BCJ, CD4515BMJ or CD4515BCJ
NS Package Number J24A
Molded Dual-In-Line Package (N)
Order Number CD4514BMN, CD4514BCN, CD4515BMN or CD4515BCN
NS Package Number N24A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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National Semiconductor
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相关型号：
CD4514BMJ/883
4000/14000/40000 SERIES, OTHER DECODER/DRIVER, TRUE OUTPUT, CDIP24, CERAMIC, DIP-24
TI
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