ADC12DC105CISQ_技术文档

ADVANCE INFORMATION

September 2007

ADC12DC080/ADC12DC105

Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS

Outputs

General Description

NOTE: This is Advance Information for products current-

ly in development. ALL specifications are design targets

and are subject to change.

Features

1 GHz Full Power Bandwidth

■

Internal sample-and-hold circuit and precision reference

Low power consumption

The ADC12DC080 and ADC12DC105 are high-performance

CMOS analog-to-digital converters capable of converting two

analog input signals into 12-bit digital words at rates up to

80/105 Mega Samples Per Second (MSPS) respectively.

These converters use a differential, pipelined architecture

with digital error correction and an on-chip sample-and-hold

circuit to minimize power consumption and the external com-

ponent count, while providing excellent dynamic perfor-

mance. A unique sample-and-hold stage yields a full-power

bandwidth of 1 GHz. The ADC12DC080/105 may be operated

from a single +3.3V power supply. A power-down feature re-

duces the power consumption to very low levels while still

allowing fast wake-up time to full operation. The differential

inputs provide a 2V full scale differential input swing. A stable

1.2V internal voltage reference is provided, or the AD-

C12DC080/105 can be operated with an external 1.2V refer-

ence. Output data format (offset binary versus 2's comple-

ment) and duty cycle stabilizer are pin-selectable. The duty

cycle stabilizer maintains performance over a wide range of

clock duty cycles.

Clock Duty Cycle Stabilizer

Single +3.3V supply operation

Power-down mode

Offset binary or 2's complement output data format

60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)

Key Specifications

For ADC12DC105

Resolution

Conversion Rate

SNR (f_IN= 240 MHz)

SFDR (f_IN= 240 MHz)

Full Power Bandwidth

Power Consumption

■

12 Bits

105 MSPS

67 dBFS (typ)

83 dBFS (typ)

1 GHz (typ)

■

800 mW (typ)

Applications

High IF Sampling Receivers

■

The ADC12DC080/105 is available in a 60-lead LLP package

and operates over the industrial temperature range of −40°C

to +85°C.

Wireless Base Station Receivers

Test and Measurement Equipment

Communications Instrumentation

Portable Instrumentation

■

Connection Diagram

30015401

300154

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Block Diagram

30015402

Ordering Information

Package

Industrial (−40°C ≤ T_A≤ +85°C)

ADC12DC080CISQ

60 Pin LLP

ADC12DC105CISQ

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2

Pin Descriptions and Equivalent Circuits

Pin No.

Symbol

Equivalent Circuit

Description

ANALOG I/O

V_INA+

V_INB+

3

13

Differential analog input pins. The differential full-scale input signal

level is 2V_P-Pwith each input pin signal centered on a common

V_INA-

V_INB-

2

14

mode voltage, V_CM

.

V_RP

A

B

5

11

These pins should each be bypassed to AGND with a low ESL

(equivalent series inductance) 0.1 µF capacitor placed very close

to the pin to minimize stray inductance. An 0201 size 0.1 µF

capacitor should be placed between V_RPand V_RNas close to the

pins as possible, and a 1 µF capacitor should be placed in parallel.

V_RPand V_RNshould not be loaded. V_CMOmay be loaded to 1mA

for use as a temperature stable 1.5V reference.

V_CMO

A

B

7

9

V_RN

A

6

10

B

It is recommended to use V_CMOto provide the common mode

voltage, V_CM, for the differential analog inputs.

Reference Voltage. This device provides an internally developed

1.2V reference. When using the internal reference, V_REFshould be

decoupled to AGND with a 0.1 µF and a 1µF, low equivalent series

inductance (ESL) capacitor.

V_REF

59

This pin may be driven with an external 1.2V reference voltage.

This pin should not be used to source or sink current.

DIGITAL I/O

This is a four-state pin controlling the input clock mode and output

data format.

OF/DCS = V_A, output data format is 2's complement without duty

cycle stabilization applied to the input clock

OF/DCS = AGND, output data format is offset binary, without duty

cycle stabilization applied to the input clock.

OF/DCS = (2/3)*V_A, output data is 2's complement with duty cycle

stabilization applied to the input clock

OF/DCS = (1/3)*V_A, output data is offset binary with duty cycle

stabilization applied to the input clock.

19

18

OF/DCS

The clock input pin.

The analog inputs are sampled on the rising edge of the clock input.

CLK

This is a two-state input controlling Power Down.

PD = V_A, Power Down is enabled and power dissipation is reduced.

PD = AGND, Normal operation.

57

20

PD_A

PD_B

3

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Pin No.

Symbol

Equivalent Circuit

Description

Digital data output pins that make up the 12-bit conversion result

for Channel A. DA0 (pin 42) is the LSB, while DA11 (pin 55) is the

MSB of the output word. Output levels are CMOS compatible.

42-49,

52-55

DA0-DA7,

DA8-DA11

Digital data output pins that make up the 12-bit conversion result

for Channel B. DB0 (pin 23) is the LSB, while DB11 (pin 36) is the

MSB of the output word. Output levels are CMOS compatible.

23-24,

27-36

DB0-DB1,

DB3-DB11

Data Ready Strobe. The data output transition is synchronized with

the falling edge of this signal. This signal switches at the same

frequency as the CLK input.

39

DRDY

ANALOG POWER

Positive analog supply pins. These pins should be connected to a

quiet source and be bypassed to AGND with 0.1 µF capacitors

located close to the power pins.

8, 16, 17, 58,

60

V_A

1, 4, 12, 15,

Exposed Pad

AGND

The ground return for the analog supply.

DIGITAL POWER

Positive driver supply pin for the output drivers. This pin should be

connected to a quiet voltage source and be bypassed to DRGND

with a 0.1 µF capacitor located close to the power pin.

V_DR

26, 38,50

The ground return for the digital output driver supply. This pins

should be connected to the system digital ground, but not be

connected in close proximity to the ADC's AGND pins.

25, 37, 51

DRGND

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Absolute Maximum Ratings (Notes 1, 3)

Operating Ratings (Notes 1, 3)

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Operating Temperature

−40°C ≤ T_A≤ +85°C

Supply Voltage (V_A)

Output Driver Supply (V_DR

Clock Duty Cycle

(DCS Enabled)

(DCS disabled)

V_CM

+2.7V to +3.6V

)

+2.4V to V_A

Supply Voltage (V_A, V_DR

)

−0.3V to 4.2V

Voltage on Any Pin

(Not to exceed 4.2V)

−0.3V to (V_A+0.3V)

30/70 %

45/55 %

1.4V to 1.6V

Input Current at Any Pin other

than Supply Pins (Note 4)

±5 mA

|AGND-DRGND|

Package Input Current (Note 4)

Max Junction Temp (T_J)

±50 mA

+150°C

30°C/W

≤100mV

Thermal Resistance (θ_JA

)

ESD Rating

Human Body Model (Note 6)

Machine Model (Note 6)

Storage Temperature

2500V

250V

−65°C to +150°C

Soldering process must comply with National

Semiconductor's Reflow Temperature Profile

specifications. Refer to www.national.com/packaging.

(Note 7)

ADC12DC080 Converter Electrical Characteristics

This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica-

tions cannot be guaranteed until device characterization has taken place.

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.0V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 80 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Limits

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12

Bits (min)

LSB (max)

LSB (min)

LSB (max)

LSB (min)

INL

Integral Non Linearity (Note 11)

Differential Non Linearity

±0.5

±0.4

DNL

Under Range Output Code

Over Range Output Code

0

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

1.45

1.55

V (min)

V (max)

V_CMO

V_CM

C_IN

Common Mode Output Voltage

1.5

1.4

1.6

V (min)

V (max)

Analog Input Common Mode Voltage

(CLK LOW)

(CLK HIGH)

8.5

3.5

pF

V_INInput Capacitance (each pin to

GND) (Note 12)

V_IN= 1.5 Vdc

± 0.5 V

1.176

1.224

V (min)

V (max)

V_REF

External Reference Voltage

1.20

5

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ADC12DC080 Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.0V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 80 MHz, V_CM= V_CMO, C_L= 5 pF/pin, . Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Units

(Limits)

(Note 2)

Typical

(Note 10)

Symbol

Parameter

Conditions

Limits

DYNAMIC CONVERTER CHARACTERISTICS, A_IN= -1dBFS

FPBW

SNR

Full Power Bandwidth

Signal-to-Noise Ratio

-1 dBFS Input, −3 dB Corner

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 170 MHz

1.0

71.2

70

GHz

dBFS

Bits

68

90

SFDR

ENOB

THD

H2

Spurious Free Dynamic Range

Effective Number of Bits

88

83

11.5

11.3

11

Bits

−88

−85

−80

−100

−95

−85

−90

−88

−83

71.1

69.8

67.7

dBFS

Total Harmonic Disortion

Second Harmonic Distortion

Third Harmonic Distortion

H3

SINAD

Signal-to-Noise and Distortion Ratio

ADC12DC080 Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.0V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 80 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Limits

DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B)

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

V_D= 3.6V

V_D= 3.0V

V_IN= 3.3V

V_IN= 0V

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

2.0

0.8

V (min)

V (max)

µA

10

−10

5

µA

pF

DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY)

V_OUT(1)

V_OUT(0)

+I_SC

I_OUT= −0.5 mA , V_DR= 2.4V

I_OUT= 1.6 mA, V_DR= 2.4V

V_OUT= 0V

Logical “1” Output Voltage

1.2

0.4

V (min)

V (max)

mA

Logical “0” Output Voltage

Output Short Circuit Source Current

Output Short Circuit Sink Current

Digital Output Capacitance

−10

10

5

−I_SC

V_OUT= V_DR

mA

C_OUT

pF

POWER SUPPLY CHARACTERISTICS

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Typical

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Limits

I_A

I_DR

Full Operation

200

26

mA (max)

mA

Analog Supply Current

Full Operation (Note 13)

Excludes I_DR(Note 13)

PD_A=PD_B=V_A

Digital Output Supply Current

Power Consumption

600

30

mW (max)

mW

Power Down Power Consumption

ADC12DC080 Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.0V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 80 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Timing measurements are taken at 50% of

the signal amplitude. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symb

Parameter

Conditions

Limits

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

80

20

MHz (max)

MHz (min)

ns

t_CH

6

t_CL

Clock Low Time

ns

t_CONV

Conversion Latency

7

Clock Cycles

2

6

ns (min)

ns (max)

t_OD

Output Delay of CLK to DATA

Relative to rising edge of CLK

4

t_SU

t_H

t_AD

t_AJ

Data Output Setup Time

Data Output Hold Time

Aperture Delay

Relative to DRDY

5

ns (min)

ns

5

0.6

0.1

Aperture Jitter

ps rms

7

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ADC12DC105 Converter Electrical Characteristics

This product is currently under development. As such, the parameters specified are DESIGN TARGETS. The specifica-

tions cannot be guaranteed until device characterization has taken place.

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.3V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 105 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Limits

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes

12

Bits (min)

LSB (max)

LSB (min)

LSB (max)

LSB (min)

INL

Integral Non Linearity (Note 11)

Differential Non Linearity

±0.5

±0.4

DNL

Under Range Output Code

Over Range Output Code

0

4095

REFERENCE AND ANALOG INPUT CHARACTERISTICS

1.45

1.55

V (min)

V (max)

V_CMO

V_CM

C_IN

Common Mode Output Voltage

1.5

1.4

1.6

V (min)

V (max)

Analog Input Common Mode Voltage

(CLK LOW)

(CLK HIGH)

8.5

3.5

pF

V_INInput Capacitance (each pin to GND) V_IN= 1.5 Vdc

(Note 12)

± 0.5 V

1.176

1.224

V (min)

V (max)

V_REF

External Reference Voltage

1.20

ADC12DC105 Dynamic Converter Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.3V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 105 MHz, V_CM= V_CMO, C_L= 5 pF/pin, . Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Units

(Limits)

(Note 2)

Typical

(Note 10)

Symbol

Parameter

Conditions

Limits

DYNAMIC CONVERTER CHARACTERISTICS, A_IN= -1dBFS

FPBW

SNR

Full Power Bandwidth

Signal-to-Noise Ratio

-1 dBFS Input, −3 dB Corner

f_IN= 10 MHz

1.0

70.1

69.1

67

GHz

dBFS

Bits

f_IN= 70 MHz

f_IN= 240 MHz

f_IN= 10 MHz

88

f_IN= 70 MHz

SFDR

ENOB

THD

H2

Spurious Free Dynamic Range

Effective Number of Bits

85

f_IN= 240 MHz

f_IN= 10 MHz

83

11.3

11.2

10.8

−86

−85

−80

−95

−90

−85

f_IN= 70 MHz

Bits

f_IN= 240 MHz

f_IN= 10 MHz

Bits

dBFS

f_IN= 70 MHz

Total Harmonic Disortion

Second Harmonic Distortion

f_IN= 240 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 240 MHz

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Units

(Limits)

(Note 2)

Typical

(Note 10)

Symbol

Parameter

Conditions

Limits

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 240 MHz

f_IN= 10 MHz

f_IN= 70 MHz

f_IN= 240 MHz

−88

−85

−83

70

dBFS

H3

Third Harmonic Distortion

SINAD

Signal-to-Noise and Distortion Ratio

69

66.8

ADC12DC105 Logic and Power Supply Electrical Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.3V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 105 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Boldface limits apply for T_MIN≤ T_A≤

T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symbol

Parameter

Conditions

Limits

DIGITAL INPUT CHARACTERISTICS (CLK, PD_A,PD_B)

V_IN(1)

V_IN(0)

I_IN(1)

I_IN(0)

C_IN

V_D= 3.6V

V_D= 3.0V

V_IN= 3.3V

V_IN= 0V

Logical “1” Input Voltage

Logical “0” Input Voltage

Logical “1” Input Current

Logical “0” Input Current

Digital Input Capacitance

2.0

0.8

V (min)

V (max)

µA

10

−10

5

µA

pF

DIGITAL OUTPUT CHARACTERISTICS (DA0-DA11,DB0-DB11,DRDY)

V_OUT(1)

V_OUT(0)

+I_SC

I_OUT= −0.5 mA , V_DR= 2.4V

I_OUT= 1.6 mA, V_DR= 2.4V

V_OUT= 0V

Logical “1” Output Voltage

1.2

0.4

V (min)

V (max)

mA

Logical “0” Output Voltage

Output Short Circuit Source Current

Output Short Circuit Sink Current

Digital Output Capacitance

−10

10

5

−I_SC

V_OUT= V_DR

mA

C_OUT

pF

POWER SUPPLY CHARACTERISTICS

I_A

Full Operation

242

32

mA (max)

mA

Analog Supply Current

I_DR

Full Operation (Note 13)

Excludes I_DR(Note 13)

PD_A=PD_B=V_A

Digital Output Supply Current

Power Consumption

800

33

mW (max)

mW

Power Down Power Consumption

ADC12DC105 Timing and AC Characteristics

Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, V_A= +3.3V, V_DR= +2.5V, Internal V_REF

=

+1.2V, f_CLK= 105 MHz, V_CM= V_CMO, C_L= 5 pF/pin. Typical values are for T_A= 25°C. Timing measurements are taken at 50% of

the signal amplitude. Boldface limits apply for T_MIN≤ T_A≤ T_MAX. All other limits apply for T_A= 25°C (Notes 8, 9)

Typical

(Note 10)

Units

(Limits)

Symb

Parameter

Conditions

Limits

Maximum Clock Frequency

Minimum Clock Frequency

Clock High Time

105

20

MHz (max)

MHz (min)

ns

t_CH

4

t_CL

Clock Low Time

ns

t_CONV

Conversion Latency

7

Clock Cycles

2

6

ns (min)

ns (max)

t_OD

Output Delay of CLK to DATA

Relative to rising edge of CLK

4

t_SU

t_H

t_AD

t_AJ

Data Output Setup Time

Data Output Hold Time

Aperture Delay

Relative to DRDY

3

ns (min)

ns

3

0.6

0.1

Aperture Jitter

ps rms

9

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Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is

guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.

The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under

the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.

Note 2: This parameter is specified in units of dBFS - indicating the value that would be attained with a full-scale input signal.

Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.

Note 4: When the input voltage at any pin exceeds the power supplies (that is, V_IN< AGND, or V_IN> V_A), the current at that pin should be limited to ±5 mA. The

±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.

Note 5: The maximum allowable power dissipation is dictated by T_J,max, the junction-to-ambient thermal resistance, (θ_JA), and the ambient temperature, (T_A), and

can be calculated using the formula P_D,max= (T_J,max- T_A)/θ_JA. The values for maximum power dissipation listed above will be reached only when the device is

operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such

conditions should always be avoided.

Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0 Ω

Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.

Note 8: The inputs are protected as shown below. Input voltage magnitudes above V_Aor below GND will not damage this device, provided current is limited per

(Note 4). However, errors in the A/D conversion can occur if the input goes above 2.6V or below GND as described in the Operating Ratings section.

30015411

Note 9: With a full scale differential input of 2V_P-P, the 12-bit LSB is 488 µV.

Note 10: Typical figures are at T_A= 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not

guaranteed.

Note 11: Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through positive and negative

full-scale.

Note 12: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.

Note 13: I_DRis the current consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins, the supply voltage,

V_DR, and the rate at which the outputs are switching (which is signal dependent). I_DR=V_DR(C₀x f₀+ C₁x f₁+....C₁₁x f₁₁) where V_DRis the output driver power

supply voltage, C_nis total capacitance on the output pin, and f_nis the average frequency at which that pin is toggling.

Note 14: This parameter is guaranteed by design and/or characterization and is not tested in production.

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MSB (MOST SIGNIFICANT BIT) is the bit that has the largest

value or weight. Its value is one half of full scale.

Specification Definitions

APERTURE DELAY is the time after the falling edge of the

clock to when the input signal is acquired or held for conver-

sion.

NEGATIVE FULL SCALE ERROR is the difference between

the actual first code transition and its ideal value of ½ LSB

above negative full scale.

APERTURE JITTER (APERTURE UNCERTAINTY) is the

variation in aperture delay from sample to sample. Aperture

jitter manifests itself as noise in the output.

OFFSET ERROR is the difference between the two input

voltages [(V_IN+) – (V_IN-)] required to cause a transition from

code 2047 to 2048.

CLOCK DUTY CYCLE is the ratio of the time during one cycle

that a repetitive digital waveform is high to the total time of

one period. The specification here refers to the ADC clock

input signal.

OUTPUT DELAY is the time delay after the falling edge of the

clock before the data update is presented at the output pins.

PIPELINE DELAY (LATENCY) See CONVERSION LATEN-

CY.

COMMON MODE VOLTAGE (V_CM) is the common DC volt-

age applied to both input terminals of the ADC.

POSITIVE FULL SCALE ERROR is the difference between

the actual last code transition and its ideal value of 1½ LSB

below positive full scale.

CONVERSION LATENCY is the number of clock cycles be-

tween initiation of conversion and when that data is presented

to the output driver stage. Data for any given sample is avail-

able at the output pins the Pipeline Delay plus the Output

Delay after the sample is taken. New data is available at every

clock cycle, but the data lags the conversion by the pipeline

delay.

POWER SUPPLY REJECTION RATIO (PSRR) is a measure

of how well the ADC rejects a change in the power supply

voltage. PSRR is the ratio of the Full-Scale output of the ADC

with the supply at the minimum DC supply limit to the Full-

Scale output of the ADC with the supply at the maximum DC

supply limit, expressed in dB.

CROSSTALK is coupling of energy from one channel into the

other channel.

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in

dB, of the rms value of the input signal to the rms value of the

sum of all other spectral components below one-half the sam-

pling frequency, not including harmonics or DC.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of

the maximum deviation from the ideal step size of 1 LSB.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE

BITS) is another method of specifying Signal-to-Noise and

Distortion Ratio or SINAD. ENOB is defined as (SINAD -

1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or

SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral com-

ponents below half the clock frequency, including harmonics

but excluding d.c.

FULL POWER BANDWIDTH is a measure of the frequency

at which the reconstructed output fundamental drops 3 dB

below its low frequency value for a full scale input.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-

ence, expressed in dB, between the rms values of the input

signal and the peak spurious signal, where a spurious signal

is any signal present in the output spectrum that is not present

at the input.

GAIN ERROR is the deviation from the ideal slope of the

transfer function. It can be calculated as:

TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-

pressed in dB, of the rms total of the first nine harmonic levels

at the output to the level of the fundamental at the output. THD

is calculated as

Gain Error = Positive Full Scale Error − Negative Full Scale

Error

It can also be expressed as Positive Gain Error and Negative

Gain Error, which are calculated as:

PGE = Positive Full Scale Error - Offset Error

NGE = Offset Error - Negative Full Scale Error

INTEGRAL NON LINEARITY (INL) is a measure of the de-

viation of each individual code from a best fit straight line. The

deviation of any given code from this straight line is measured

from the center of that code value.

where f₁is the RMS power of the fundamental (output) fre-

quency and f₂through f₁₀are the RMS power of the first 9

harmonic frequencies in the output spectrum.

INTERMODULATION DISTORTION (IMD) is the creation of

additional spectral components as a result of two sinusoidal

frequencies being applied to the ADC input at the same time.

It is defined as the ratio of the power in the intermodulation

products to the total power in the original frequencies. IMD is

usually expressed in dBFS.

SECOND HARMONIC DISTORTION (2ND HARM) is the dif-

ference expressed in dB, between the RMS power in the input

frequency at the output and the power in its 2nd harmonic

level at the output.

THIRD HARMONIC DISTORTION (3RD HARM) is the dif-

ference, expressed in dB, between the RMS power in the

input frequency at the output and the power in its 3rd harmonic

level at the output.

LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-

est value or weight of all bits. This value is V_FS/2ⁿ, where

“V_FS” is the full scale input voltage and “n” is the ADC reso-

lution in bits.

MISSING CODES are those output codes that will never ap-

pear at the ADC outputs. The ADC is guaranteed not to have

any missing codes.

11

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Timing Diagrams

30015409

FIGURE 1. Output Timing

Transfer Characteristic

30015410

FIGURE 2. Transfer Characteristic

www.national.com

12

Physical Dimensions inches (millimeters) unless otherwise noted

TOP View...............................SIDE View...............................BOTTOM View

60-Lead LLP Package

Ordering Numbers:

ADC12DC080CISQ / ADC12DC105CISQ

NS Package Number SQA60A

13

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Notes

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型号：	ADC12DC105CISQ
厂家：	National Semiconductor
描述：	Dual 12-Bit, 80/105 MSPS A/D Converter with CMOS Outputs 双12位，一百〇五分之八十零MSPS A / D转换器，CMOS输出转换器
文件：	总14页 (文件大小：343K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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