ADC10DV200CISQE [NSC]
Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs; 双路10位， 200 MSPS低功耗A / D转换器，并行LVDS / CMOS输出
| 型号： | ADC10DV200CISQE |
| 厂家： | 
National Semiconductor |
| 描述： | Dual 10-bit, 200 MSPS Low-Power A/D Converter with Parallel LVDS/CMOS Outputs |
| 文件： | 总24页 (文件大小：518K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 5, 2009
ADC10DV200
Dual 10-bit, 200 MSPS Low-Power A/D Converter with
Parallel LVDS/CMOS Outputs
General Description
Features
The ADC10DV200 is a monolithic analog-to-digital converter
capable of converting two analog input signals into 10-bit dig-
ital words at rates up to 200 Mega Samples Per Second
(MSPS). The digital output mode is selectable and can be ei-
ther differential LVDS or CMOS signals. This converter uses
a differential, pipelined architecture with digital error correc-
tion and an on-chip sample-and-hold circuit to minimize die
size and power consumption while providing excellent dy-
namic performance. A unique sample-and-hold stage yields
a full-power bandwidth of 900MHz. Fabricated in core CMOS
process, the ADC10DV200 may be operated from a single
1.8V power supply. The ADC10DV200 achieves approxi-
mately 9.6 effective bits at Nyquist and consumes just 280mW
at 170MSPS in CMOS mode and 450mW at 200MSPS in
LVDS mode. The power consumption can be scaled down
further by reducing sampling rates.
Single 1.8V power supply operation.
■
■
■
■
■
■
■
■
Power scaling with clock frequency.
Internal sample-and-hold.
Internal or external reference.
Power down mode.
Offset binary or 2's complement output data format.
LVDS or CMOS output signals.
60-pin LLP package, (9x9x0.8mm, 0.5mm pin-pitch)
Clock Duty Cycle Stabilizer.
■
■
IF Sampling Bandwidth > 900MHz.
Key Specifications
Resolution
Conversion Rate
ENOB
SNR
SINAD
10 Bits
■
■
■
■
■
■
■
■
■
200 MSPS
9.6 bits (typ) @Fin=70MHz
59.9 dBFS (typ) @Fin=70MHz
59.9 dBFS (typ) @Fin=70MHz
82 dBFS (typ) @Fin=70MHz
450mW (typ) @Fs=200MSPS
280mW (typ) @Fs=170MSPS
−40°C to +85°C.
Applications
Communications
■
■
■
■
Medical Imaging
SFDR
Portable Instrumentation
LVDS Power
CMOS Power
Operating Temp. Range
Digital Video
Block Diagram
30082002
© 2009 National Semiconductor Corporation
300820
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Connection Diagram
30082001
Ordering Information
Package
Industrial (−40°C ≤ TA ≤ +85°C)
ADC10DV200CISQ
60 Pin LLP
ADC10DV200CISQE
60 Pin LLP,
250 pc. Tape and Reel
ADC10DV200EB
Evaluation Board
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2
Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
VINA+
VINB+
13
3
Differential analog input pins. The differential full-scale input
signal level is 1.5VP-P with each input pin signal centered on
VINA-
VINB-
14
2
a common mode voltage, VCM
.
VRP
VRP
A
B
10
6
These pins should each be bypassed to AGND with a low ESL
(equivalent series inductance) 0.1 µF capacitor placed very
close to the pin to minimize stray inductance. An 0201 size 0.1
µF capacitor should be placed between VRP and VRN as close
to the pins as possible.
VRM
VRM
A
B
11
5
VRP and VRN should not be loaded. VRM may be loaded to 1mA
for use as a temperature stable 0.9V reference.
It is recommended to use VRM to provide the common mode
voltage, VCM for the differential analog inputs.
VRN
VRN
A
B
9
7
Reference Voltage select pin and external reference input.
The relationship between the voltage on the pin and the
reference voltage is as follows:
The internal 0.75V reference is
used.
1.4V ≤ VREF ≤ VA
The external reference voltage is
used.
0.2V ≤ VREF ≤ 1.4V
VREF
17
Note: When using an external
reference, be sure to bypass with
a 0.1µF capacitor to AGND as
close to the pin as possible.
The internal 0.5V reference is
used.
AGND ≤ VREF ≤ 0.2V
Programming resistor for analog bias current. Nominally a
3.3kΩ to AGND for 200MSPS, or tie to VA to use the internal
frequency scaling current.
REXT
19
Data Format/Duty Cycle Correction selection pin.
(see Table 1)
20
DF/DCS
3
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Pin No.
Symbol
Equivalent Circuit
Description
DIGITAL I/O
Clock input pins signal. The analog inputs are sampled on the
rising edge of this signal. The clock can be configured for
single-ended mode by shorting the CLK- pin to AGND. When
in differential mode, the common mode voltage for the clock
is internally set to 1.2V.
57
56
CLK +
CLK -
Two-state input controlling Power Down.
PD = VA, Power Down is enabled and power dissipation is
reduced.
36
53
PD_A
PD_B
PD = AGND, Normal operation.
Two-state input controlling Output Mode.
OUTSEL = VD, LVDS Output Mode.
OUTSEL = AGND, CMOS Output Mode.
23
OUTSEL
LVDS Output Mode
24, 25
26, 27
28, 29
32, 33
34, 35
39, 40
41, 42
43, 44
47, 48
49, 50
D0+,D0-
D1+, D1-
D2+, D2-
D3+, D3-
D4+, D4-
D5+, D5-
D6+, D6-
D7+, D7-
D8+, D8-
D9+, D9-
LVDS Output pairs for bits 0 through 9. A-channel and B-
channel digital LVDS outputs are interleaved. A channel is
ready at rising edge of DRDY and B channel is ready at the
falling edge of DRDY.
Data Ready Strobe. This signal is a LVDS DDR clock used to
capture the output data. A-channel data is valid on the rising
edge of this signal and B-channel data is valid on the falling
edge.
37
38
DRDY+
DRDY-
ADC over-range Signal. This signals timing is formatted
similarly to the data output signals. A channel is valid on DRDY
rising and B channel is valid on DRDY falling. This signal will
go high when the respective channel exceeds the allowable
range of the ADC. Nominally this signal will be low.
51
52
OR+
OR-
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4
Pin No.
Symbol
Equivalent Circuit
Description
CMOS Output Mode
Digital data output pins that make up the 10-bit conversion
result for Channel A. DA0 (pin 24) is the LSB, while DA9 (pin
35) is the MSB of the output word. Output levels are CMOS
compatible.
24-29,
32-35
DA0-DA9
Digital data output pins that make up the 10-bit conversion
result for Channel B. DB0 (pin 39) is the LSB, while DB9 (pin
50) is the MSB of the output word. Output levels are CMOS
compatible.
39-44,
47-50
DB0-DB9
Data Ready Strobe for channel A. This signal is used to clock
the A-Channel output data. DRDYA is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
37
DRDYA
DRDYB
Data Ready Strobe for channel B. This signal is used to clock
the B-Channel output data. DRDYB is a SDR clock with same
frequency as CLK rate and data is valid on the rising edges.
38
51
Overrange indicator for channel A. A high on this pin indicates
that the input exceeded the allowable range for the converter.
ORA
ORB
Overrange indicator for channel B. A high on this pin indicates
that the input exceeded the allowable range for the converter.
52
ANALOG POWER
Positive analog supply pins. These pins should be connected
to a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
8, 16, 18, 59,
60
VA
The ground return for the analog supply.
Exposed pad must be soldered to AGND to ensure rated
performance.
1, 4, 12, 15,
22, 55, 58, EP
AGND
DIGITAL POWER
Positive digital supply pins. These pins should be connected
to a quiet source and be bypassed to AGND with 0.1 µF
capacitors located close to the power pins.
VD
21, 54
Positive driver supply pin for the output drivers. This pin should
be connected to a quiet voltage source and be bypassed to
DRGND with a 0.1 µF capacitor located close to the power
pin.
VDR
31, 45
30, 46
The ground return for the digital output driver supply. This pin
should be connected to the system digital ground.
DRGND
TABLE 1. Voltage on DF/DCS Pin and Corresponding Chip Response
Voltage on DF/DCS
Results
Suggestions
Min
0 mV
Max
DF
1
DCS
200mV
600 mV
1
0
0
1
2's complement data, duty cycle correction on
Offset binary data, duty cycle correction off
2's complement data, duty cycle correction off
Offset binary data, duty cycle correction on
Tie to AGND
250 mV
0
Leave floating
Tie to VA
750 mV 1250 mV
1400mV VA
1
0
5
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Absolute Maximum Ratings (Notes 3, 1)
Operating Ratings (Notes 1, 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Operating Temperature
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA, VD, VDR
Clock Duty Cycle
(DCS Enabled)
(DCS disabled)
VCM
)
+1.7V to +1.9V
Supply Voltage (VA, VD VDR
)
−0.3V to 2.2V
30/70 %
48/52 %
0.8V to 1.0V
Voltage on Any Pin
(Not to exceed 2.2V)
−0.3V to (VA +0.3V)
Input Current at Any Pin other
than Supply Pins (Note 4)
±25 mA
Package Input Current (Note 4)
Max Junction Temp (TJ)
±50 mA
+150°C
30°C/W
Thermal Resistance (θJA
ESD Rating (Note 6)
Human Body Model
Machine Model
)
2500V
250V
Human Body Model
Storage Temperature
750V
−65°C to +150°C
Soldering process must comply with National
Semiconductor's Reflow Temperature Profile
specifications. Refer to www.national.com/packaging.
(Note 7)
Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,
CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits
apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)
Typical
(Note 10)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
STATIC CONVERTER CHARACTERISTICS
Resolution with No Missing Codes
10
Bits (min)
mLSB (max)
mLSB (max)
%FS (max)
%FS (max)
ppm/°C
INL
Integral Non Linearity
Differential Non Linearity
Positive Gain Error
±300
±170
0.57
0.60
13
±920
±430
3.11
2.72
DNL
PGE
NGE
TC PGE
Negative Gain Error
Positive Gain Error Tempco
−40°C ≤ TA ≤ +85°C
Negative Gain Error Tempco
Offset Error
TC NGE
VOFF
15
ppm/°C
%FS (max)
ppm/°C
−40°C ≤ TA ≤ +85°C
+0.75
-0.75
0.1
Offset Error Tempco
TC VOFF
4
0
−40°C ≤ TA ≤ +85°C
Under Range Output Code
Over Range Output Code
0
1023
1023
REFERENCE AND ANALOG INPUT CHARACTERISTICS
1
0.85
V (min)
V (max)
VRM
VCM
CIN
Common Mode Output Voltage
0.9
Analog Input Common Mode Voltage
0.9
1
V
pF
pF
V
(CLK LOW)
(CLK HIGH)
VIN Input Capacitance (each pin to
AGND) (Note 11)
VIN = 0.75 Vdc
± 0.5 V
2.5
VRP
VRN
Internal Reference Top
1.33
0.55
0.78
Internal Reference Bottom
Internal Reference Accuracy
V
(VRP-VRN
)
V
EXT
VREF
0.5
1.0
V (Min)
V (max)
External Reference Voltage
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6
Dynamic Converter Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,
CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits
apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = +25°C (Notes 8, 9)
Units
(Limits)
(Note 2)
Typical
(Note 10)
Symbol
Parameter
Conditions
Limits
DYNAMIC CONVERTER CHARACTERISTICS, AIN = -1dBFS
FPBW
SNR
Full Power Bandwidth (Note 16)
Signal-to-Noise Ratio (Note 13)
-1 dBFS Input, −3 dB Corner
fIN = 10 MHz
900
59.9
59.9
82
MHz
dBFS
fIN = 70 MHz
59
70
dBFS (min)
dBFS
fIN = 10 MHz
Spurious Free Dynamic Range (Note
14)
SFDR
ENOB
H2
fIN = 70 MHz
82
dBFS (min)
Bits
fIN = 10 MHz
9.65
9.65
-94
Effective Number of Bits
Second Harmonic Distortion
Third Harmonic Distortion
fIN = 70 MHz
9.48
-70
-70
58.9
Bits (min)
dBFS
fIN = 10 MHz
fIN = 70 MHz
-94
dBFS (min)
dBFS
fIN = 10 MHz
-85
H3
fIN = 70 MHz
-84
dBFS (min)
dBFS
fIN = 10 MHz
59.8
59.8
Signal-to-Noise and Distortion Ratio
(Note 15)
SINAD
IMD
fIN = 70 MHz
dBFS (min)
fIN1 = 69 MHz AIN1 = -7 dBFS
fIN2 = 70 MHz AIN2 = -7 dBFS
fIN1 = 69 MHz AIN1 = -1 dBFS
fIN2 = 70MHz AIN2 = -1 dBFS
Intermodulation Distortion (Note 16)
Cross Talk (Note 16)
93
97
dBFS
dBFS
Power Supply Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,
CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference, LVDS Output. Typical values are for TA = 25°C. Boldface limits
apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Typical
(Note 10)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
LVDS OUTPUT MODE
Full Operation, Internal Bias
Full Operation, External 3.3kΩ Bias
Full Operation
160
148
36
mA
IA
Analog Supply Current
184
43
mA (max)
mA (max)
mA (max)
mW
ID
Digital Supply Current
IDR
64
80
Output Driver Supply Current
Internal Bias
473
450
57
Power Consumption
524
mW (max)
mW
External 3.3kΩ Bias
PDA=PDB=VA
Power Down Power Consumption
CMOS OUTPUT MODE (Note 12)
Full Operation, Internal Bias
Full Operation, External 3.3kΩ Bias
Full Operation
138
124
31
IA
ID
Analog Supply Current
Digital Supply Current
mA
mA
Internal Bias
310
280
60
Power Consumption
mW
mW
External 3.3kΩ Bias
PDA=PDB=VA
Power Down Power Consumption
7
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Input/Output Logic Electrical Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,
CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Boldface limits apply for TMIN
≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Typical
(Note 10)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
DIGITAL INPUT CHARACTERISTICS (PD_A,PD_B,OUTSEL)
VIN(1)
VIN(0)
IIN(1)
IIN(0)
CIN
VA = 1.9V
VA = 1.7V
VIN = 1.8V
VIN = 0V
Logical “1” Input Voltage (Note 16)
Logical “0” Input Voltage (Note 16)
Logical “1” Input Current
0.89
0.67
V (min)
V (max)
µA
10.6
-7.6
2
Logical “0” Input Current
µA
Digital Input Capacitance
pF
LVDS OUTPUT CHARACTERISTICS (D0-D9,DRDY,OR)
VOD
mVP-P
mV
LVDS differential output voltage
(Note 16)
330
0
Output Differential Voltage
Unbalance
±VOD
50
50
VOS
±VOS
RL
LVDS common-mode output voltage (Note 16)
Offset Voltage Unbalance
1.25
V
mV
Ω
Intended Load Resistance
100
CMOS OUTPUT CHARACTERISTICS (DA0-DA9,DB0-DB9,DRDY,OR) (Note 12)
VOH
VDR = 1.8V (Unloaded)
VDR = 1.8V (Unloaded)
VOUT = 0V
Logical "1" Output Voltage
1.8
0
V
V
VOL
Logical "0" Output Voltage
+IOSC
-IOSC
COUT
Output Short Circuit Source Current
Output Short Circuit Sink Current
Digital Output Capacitance
-20
20
2
mA
mA
pF
VOUT = VDR
Timing and AC Characteristics
Unless otherwise specified, the following specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz,
CLK duty cycle = 50%, DCS = ON, Internal 0.75V Reference. Typical values are for TA = 25°C. Timing measurements are taken
at 50% of the signal amplitude. Boldface limits apply for TMIN ≤ TA ≤ TMAX. All other limits apply for TA = 25°C (Notes 8, 9)
Typical
(Note 10)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
LVDS OUTPUT MODE
Maximum Clock Frequency
200
MHz (max)
MHz (min)
DCS On
DCS Off
65
45
Minimum Clock Frequency
DCS On
DCS Off
1.5
2.4
tCH
Clock High Time
Clock Low Time
Conversion Latency
ns (min)
ns (min)
DCS On
DCS Off
1.5
2.4
tCL
5/5.5
(A/B)
tCONV
Clock Cycles
tODA
tODB
tSU
Output Delay of CLK to A-Channel Data Relative to rising edge of CLK
Output Delay of CLK to B-Channel Data Relative to falling edge of CLK
2.7
2.7
1.2
1.2
0.7
0.3
20
1.46
1.46
0.7
ns (min)
ns (min)
ns (min)
ns (min)
ns
Data Output Setup Time
Data Output Hold Time
Aperture Delay
Relative to DRDY
Relative to DRDY
tH
0.7
tAD
tAJ
Aperture Jitter
ps rms
ps
tSKEW
Data-Data Skew
470
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8
Typical
(Note 10)
Units
(Limits)
Symbol
Parameter
Conditions
Limits
CMOS OUTPUT MODE (Notes 12, 16)
Maximum Clock Frequency
170
MHz
MHz
DCS On
DCS Off
65
25
Minimum Clock Frequency
DCS On
DCS Off
1.76
2.82
tCH
Clock High Time
ns
DCS On
DCS Off
1.76
2.82
tCL
ns
tCONV
tOD
Conversion Latency
Clock Cycles
5.5
3.15
5.81
ns (min)
ns (max)
Output Delay of CLK to DATA
Relative to falling edge of CLK
4.5
tSU
tH
tAD
tAJ
Data Output Setup Time(Note 16)
Data Output Hold Time(Note 16)
Aperture Delay
Relative to DRDY
Relative to DRDY
2.5
3.4
0.7
0.3
1.79
2.69
ns (min)
ns (min)
ns
Aperture Jitter
ps rms
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is
guaranteed to be functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see the Electrical Characteristics.
The guaranteed specifications apply only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions. Operation of the device beyond the maximum Operating Ratings is not recommended.
Note 2: Units of dBFS indicates the value that would be attained with a full-scale input signal.
Note 3: All voltages are measured with respect to GND = AGND = DRGND = 0V, unless otherwise specified.
Note 4: When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be limited to ±5 mA. The
±50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of ±5 mA to 10.
Note 5: The maximum allowable power dissipation is dictated by TJ,max, the junction-to-ambient thermal resistance, (θJA), and the ambient temperature, (TA), and
can be calculated using the formula PD,max = (TJ,max - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is
operated in a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed). Such
conditions should always be avoided.
Note 6: Human Body Model is 100 pF discharged through a 1.5 kΩ resistor. Machine Model is 220 pF discharged through 0Ω resistor. Charged device model
simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an automated assembler) then rapidly being discharged.
Note 7: Reflow temperature profiles are different for lead-free and non-lead-free packages.
Note 8: The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided current is limited per
(Note 4). However, errors in the A/D conversion can occur if the input goes above VA or below AGND.
30082011
Note 9: With a full scale differential input of 1.5VP-P , the 10-bit LSB is 1.465mV.
Note 10: Typical figures are at TA = 25°C and represent most likely parametric norms at the time of product characterization. The typical specifications are not
guaranteed.
Note 11: The input capacitance is the sum of the package/pin capacitance and the sample and hold circuit capacitance.
Note 12: CMOS Specifications are for FCLK = 170 MHz.
Note 13: SNR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.2dBFS lower.
Note 14: SFDR minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 2dBFS lower.
Note 15: SINAD minimum and typical values are for LVDS mode. Typical values for CMOS mode are typically 0.1dBFS lower.
Note 16: This parameter is guaranteed by design and/or characterization and is not tested in production.
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MISSING CODES are those output codes that will never ap-
pear at the ADC outputs. The ADC is guaranteed not to have
any missing codes.
Specification Definitions
APERTURE DELAY is the time after the falling edge of the
clock to when the input signal is acquired or held for conver-
sion.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
APERTURE JITTER (APERTURE UNCERTAINTY) is the
variation in aperture delay from sample to sample. Aperture
jitter manifests itself as noise in the output. The amount of
SNR reduction can be calculated as
NEGATIVE FULL SCALE ERROR is the difference between
the actual first code transition and its ideal value of ½ LSB
above negative full scale.
OFFSET ERROR is the difference between the two input
voltages [(VIN+) – (VIN-)] required to cause a transition from
code 511 to 512.
SNR Reduction = 20 x log10[½ x π x ƒA x tj]
CLOCK DUTY CYCLE is the ratio of the time during one cycle
that a repetitive digital waveform is high to the total time of
one period. The specification here refers to the ADC clock
input signal.
OUTPUT DELAY is the time delay after the falling edge of the
clock before the data update is presented at the output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATEN-
CY.
COMMON MODE VOLTAGE (VCM) is the common DC volt-
POSITIVE FULL SCALE ERROR is the difference between
the actual last code transition and its ideal value of 1½ LSB
below positive full scale.
age applied to both input terminals of the ADC.
CONVERSION LATENCY is the number of clock cycles be-
tween initiation of conversion and when that data is presented
to the output driver stage. Data for any given sample is avail-
able at the output pins the Pipeline Delay plus the Output
Delay after the sample is taken. New data is available at every
clock cycle, but the data lags the conversion by the pipeline
delay.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure
of how well the ADC rejects a change in the power supply
voltage. PSRR is the ratio of the Full-Scale output of the ADC
with the supply at the minimum DC supply limit to the Full-
Scale output of the ADC with the supply at the maximum DC
supply limit, expressed in dB.
CROSSTALK is coupling of energy from one channel into the
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal to the rms value of the
sum of all other spectral components below one-half the sam-
pling frequency, not including harmonics or DC.
other channel.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio or SINAD. ENOB is defined as (SINAD -
1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or
SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral com-
ponents below half the clock frequency, including harmonics
but excluding d.c.
FULL POWER BANDWIDTH is a measure of the frequency
at which the reconstructed output fundamental drops 3 dB
below its low frequency value for a full scale input.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal and the peak spurious signal, where a spurious signal
is any signal present in the output spectrum that is not present
at the input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated as:
Gain Error = Positive Full Scale Error − Negative Full Scale
Error
TOTAL HARMONIC DISTORTION (THD) is the ratio, ex-
pressed in dB, of the rms total of the first six harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
It can also be expressed as Positive Gain Error and Negative
Gain Error, which are calculated as:
PGE = Positive Full Scale Error - Offset Error
NGE = Offset Error - Negative Full Scale Error
INTEGRAL NON LINEARITY (INL) is a measure of the de-
viation of each individual code from a best fit straight line. The
deviation of any given code from this straight line is measured
from the center of that code value.
where f1 is the RMS power of the fundamental (output) fre-
quency and f2 through f7 are the RMS power of the first six
harmonic frequencies in the output spectrum.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the intermodulation
products to the total power in the original frequencies. IMD is
usually expressed in dBFS.
SECOND HARMONIC DISTORTION (2ND HARM) is the dif-
ference expressed in dB, between the RMS power in the input
frequency at the output and the power in its 2nd harmonic
level at the output.
THIRD HARMONIC DISTORTION (3RD HARM) is the dif-
ference, expressed in dB, between the RMS power in the
input frequency at the output and the power in its 3rd harmonic
level at the output.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is VFS/2n, where
“VFS” is the full scale input voltage and “n” is the ADC reso-
lution in bits.
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Timing Diagrams
30082009
FIGURE 1. LVDS Output Timing
30082016
FIGURE 2. CMOS Output Timing
11
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Transfer Characteristic
30082010
FIGURE 3. Transfer Characteristic
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Typical Performance Characteristics DNL, INL Unless otherwise specified, the following
specifications apply: AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS Enabled, LVDS Output,
VCM = VRM, TA = 25°C.
DNL
INL
30082041
30082042
13
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Typical Performance Characteristics Unless otherwise specified, the following specifications apply:
AGND = DRGND = 0V, VA = VD = VDR = +1.8V, fCLK = 200 MHz, 50% Duty Cycle, DCS disabled, LVDS Output, VCM = VRM, fIN
70 MHz, TA = 25°C.
=
SNR, SINAD, SFDR vs. VA
Distortion vs. VA
30082051
30082052
SNR, SINAD, SFDR vs. Temperature
Distortion vs. Temperature
30082053
30082054
SNR, SINAD, SFDR vs. Clock Duty Cycle, fIN = 10MHz
Distortion vs. Clock Duty Cycle, fIN = 10MHz
30082055
30082056
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SNR, SINAD, SFDR vs. Ext. Reference Voltage
Distortion vs. Ext. Reference Voltage
30082057
30082058
SNR, SINAD, SFDR vs. Clock Frequency
Distortion vs. Clock Frequency
30082059
30082060
SNR, SINAD, SFDR vs. Ext. VCM
Distortion vs. Ext. VCM
30082061
30082062
15
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Spectral Response @ 10 MHz Input
Spectral Response @ 70 MHz Input
30082063
30082064
Spectral Response @ 170 MHz Input
IMD, fIN1 = 69 MHz, fIN2 = 70 MHz
30082065
30082066
Total Power vs. Clock Frequency, fIN = 10 MHz
30082067
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For single frequency sine waves the full scale error in LSB
can be described as approximately
Functional Description
Operating on a single +1.8V supply, the ADC10DV200 digi-
tizes two differential analog input signals to 10 bits, using a
differential pipelined architecture with error correction circuitry
and an on-chip sample-and-hold circuit to ensure maximum
performance. The user has the choice of using an internal
0.75V stable reference, or using an external 0.75V reference.
Any external reference is buffered on-chip to ease the task of
driving that pin. Duty cycle stabilization and output data format
are selectable using the quad state function DF/DCS pin (pin
20). The output data can be set for offset binary or two's com-
plement.
EFS = 1024 ( 1 - sin (90° + dev))
Where dev is the angular difference in degrees between the
two signals having a 180° relative phase relationship to each
other (see Figure 5). For single frequency inputs, angular er-
rors result in a reduction of the effective full scale input. For
complex waveforms, however, angular errors will result in
distortion.
Applications Information
1.0 OPERATING CONDITIONS
We recommend that the following conditions be observed for
operation of the ADC10DV200:
30082081
1.7V ≤ VA ≤ 1.9V
1.7V ≤ VDR ≤ VA
FIGURE 5. Angular Errors Between the Two Input Signals
Will Reduce the Output Level or Cause Distortion
45 MHz ≤ fCLK ≤ 200 MHz, with DCS off
65 MHz ≤ fCLK ≤ 200 MHz, with DCS on
0.75V internal reference
It is recommended to drive the analog inputs with a source
impedance less than 100Ω. Matching the source impedance
for the differential inputs will improve even ordered harmonic
performance (particularly second harmonic).
VREF = 0.75V (for an external reference)
VCM = 0.9V (from VRM
2.0 ANALOG INPUTS
2.1 Signal Inputs
)
Table 2 indicates the input to output relationship of the AD-
C10DV200.
2.1.1 Differential Analog Input Pins
The ADC10DV200 has a pair of analog signal input pins for
each of two channels. VIN+ and VIN− form a differential input
pair. The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
Figure 4shows the expected input signal range. Note that the
common mode input voltage, VCM, should be 0.9V. Using
VRM (pins 5,11) for VCM will ensure the proper input common
mode level for the analog input signal. The positive peaks of
the individual input signals should each never exceed 2.2V.
Each analog input pin of the differential pair should have a
maximum peak-to-peak voltage of 1.5V, be 180° out of phase
with each other and be centered around VCM.The peak-to-
peak voltage swing at each analog input pin should not ex-
ceed the 1V or the output data will be clipped.
30082080
FIGURE 4. Expected Input Signal Range
17
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TABLE 2. Input to Output Relationship
VIN+
VIN−
Binary Output
00 0000 0000
01 0000 0000
10 0000 0000
11 0000 0000
11 1111 1111
2’s Complement Output
VCM − VREF/2
VCM − VREF/4
VCM
VCM + VREF/2
VCM + VREF/4
VCM
10 0000 0000
11 0000 0000
00 0000 0000
01 0000 0000
01 1111 1111
Negative Full-Scale
Mid-Scale
VCM + VREF/4
VCM + VREF/2
VCM − VREF/4
VCM − VREF/2
Positive Full-Scale
2.1.2 Driving the Analog Inputs
Figure 6 and Figure 7 show examples of single-ended to dif-
ferential conversion circuits. The circuit in Figure 6 works well
for input frequencies up to approximately 70MHz, while the
circuit in Figure 7 works well above 70MHz.
The VIN+ and the VIN− inputs of the ADC10DV200 have an
internal sample-and-hold circuit which consists of an analog
switch followed by a switched-capacitor amplifier.
30082082
FIGURE 6. Low Input Frequency Transformer Drive Circuit
30082083
FIGURE 7. High Input Frequency Transformer Drive Circuit
One short-coming of using a transformer to achieve the sin-
gle-ended to differential conversion is that most RF trans-
formers have poor low frequency performance. A differential
amplifier can be used to drive the analog inputs for low fre-
quency applications. The amplifier must be fast enough to
settle from the charging glitches on the analog input resulting
from the sample-and-hold operation before the clock goes
high and the sample is passed to the ADC core.
2.2 Reference Pins
The ADC10DV200 is designed to operate with an internal or
external voltage reference. The voltage on the VREF pin se-
lects the source and level of the reference voltage. An internal
0.75 Volt reference is used when a voltage between 1.4 V to
VA is applied to the VREF pin. An internal 0.5 Volt reference is
used when a voltage between 0.2V and AGND is applied to
the VREF pin. If a voltage between 0.2V and 1.4V is applied to
the VREF pin, then that voltage is used for the reference. SNR
will improve without a significant degradation in SFDR for
VREF=1.0V. SNR will decrease if VREF=0.5V, yet linearity will
be maintained. If using an external reference the VREF pin
should be bypassed to ground with a 0.1 µF capacitor close
to the reference input pin.
2.1.3 Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range
of 0.8V to 1.0V and be a value such that the peak excursions
of the analog signal do not go more negative than ground or
more positive than the VA supply. It is recommended to use
VRM (pins 5,11) as the input common mode voltage.
It is important that all grounds associated with the reference
voltage and the analog input signal make connection to the
ground plane at a single, quiet point to minimize the effects of
noise currents in the ground path.
If the ADC10DV200 is operated with VA=1.8V, a resistor of
approximately 1KΩ should be used from the VRM pin to AG-
ND. This will help maintain stability over the entire tempera-
ture range when using a high supply voltage.
The Reference Bypass Pins (VRP, VRM, and VRN) for channels
A and B are made available for bypass purposes. These pins
should each be bypassed to AGND with a low ESL (equivalent
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18
series inductance) 0.1 µF capacitor placed very close to the
pin to minimize stray inductance. A 0.1 µF capacitor should
be placed between VRP and VRN as close to the pins as pos-
sible. This configuration is shown in Figure 8. It is necessary
to avoid reference oscillation, which could result in reduced
SFDR and/or SNR. VRM may be loaded to 1mA for use as a
temperature stable 0.9V reference. The remaining pins
should not be loaded.
through a high speed buffer gate. The trace carrying the clock
signal should be as short as possible and should not cross
any other signal line, analog or digital, not even at 90°.
If the clock is interrupted, or its frequency is too low, the
charge on the internal capacitors can dissipate to the point
where the accuracy of the output data will degrade. This is
what limits the minimum sample rate.
The clock line should be terminated at its source in the char-
acteristic impedance of that line. Take care to maintain a
constant clock line impedance throughout the length of the
line. Refer to Application Note AN-905 for information on set-
ting characteristic impedance. It is highly desirable that the
the source driving the ADC clock pins only drive that pin.
Smaller capacitor values than those specified will allow faster
recovery from the power down mode, but may result in de-
graded noise performance. Loading any of these pins, other
than VRM may result in performance degradation.
The nominal voltages for the reference bypass pins are as
follows:
The duty cycle of the clock signal can affect the performance
of the A/D Converter. Because achieving a precise duty cycle
is difficult, the ADC10DV200 has a Duty Cycle Stabilizer.
VRM = 0.9 V
VRP = 1.33 V
VRN = 0.55 V
4.0 DIGITAL OUTPUTS
Digital outputs consist of the LVDS signals D0-D9, OR, and
DRDY.
2.3 DF/DCS Pin
Duty cycle stabilization and output data format are selectable
using this quad state function pin. When enabled, duty cycle
stabilization can compensate for clock inputs with duty cycles
ranging from 30% to 70% and generate a stable internal clock,
improving the performance of the part. See Table 1 for DF/
DCS voltage vs output format description. DCS mode of op-
eration is limited to 65 MHz ≤ fCLK ≤ 200 MHz.
The ADC10DV200 has 12 LVDS compatible data output pins:
10 data output pins corresponding to the converted input val-
ue, a data ready (DRDY) signal that should be used to capture
the output data and an over-range indicator (OR) which is set
high when the sample amplitude exceeds the 10-Bit conver-
sion range. Valid data is present at these outputs while the
PD pin is low. A-Channel data should be captured and latched
with the rising edge of the DRDY signal and B-Channel data
should be captured and latched with the falling edge of DRDY.
3.0 DIGITAL INPUTS
Digital CMOS compatible inputs consist of CLK, PD_A,
PD_B, and OUTSEL.
To minimize noise due to output switching, the load currents
at the digital outputs should be minimized. This can be
achieved by keeping the PCB traces less than 2 inches long;
longer traces are more susceptible to noise. The character-
istic impedance of the LVDS traces should be 100Ω, and the
effective capacitance < 10pF. Try to place the 100Ω termina-
tion resistor as close to the receiving circuit as possible. (See
Figure 8)
3.1 Clock Input
The CLK controls the timing of the sampling process. To
achieve the optimum noise performance, the clock input
should be driven with a stable, low jitter clock signal in the
range indicated in the Electrical Table. The clock input signal
should also have a short transition region. This can be
achieved by passing a low-jitter sinusoidal clock source
19
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20
5.0 POWER SUPPLY CONSIDERATIONS
the noise on the analog supply pin should be kept below 100
mVP-P
.
The power supply pins should be bypassed with a 0.1 µF ca-
pacitor and with a 100 pF ceramic chip capacitor close to each
power pin. Leadless chip capacitors are preferred because
they have low series inductance.
No pin should ever have a voltage on it that is in excess of the
supply voltages, not even on a transient basis. Be especially
careful of this during power turn on and turn off.
As is the case with all high-speed converters, the AD-
C10DV200 is sensitive to power supply noise. Accordingly,
21
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Physical Dimensions inches (millimeters) unless otherwise noted
TOP View...............................SIDE View...............................BOTTOM View
60-Lead LLP Package
Ordering Numbers:
ADC10DV200CISQ
NS Package Number SQA60A
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Notes
23
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