ADC08D1010DIYB [NSC]
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter; 高性能，低功耗，双路，8位， 1 GSPS A / D转换器
| 型号： | ADC08D1010DIYB |
| 厂家： | 
National Semiconductor |
| 描述： | High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D Converter |
| 文件： | 总38页 (文件大小：1237K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 20, 2009
ADC08D1010
High Performance, Low Power, Dual 8-Bit, 1 GSPS A/D
Converter
General Description
Features
The ADC08D1010 is a dual, low power, high performance
CMOS analog-to-digital converter that digitizes signals to 8
bits resolution at sampling rates up to 1.0 GSPS. Consuming
a typical 1.6 Watts at 1 GSPS from a single 1.9 Volt supply,
this device is guaranteed to have no missing codes over the
full operating temperature range. The unique folding and in-
terpolating architecture, the fully differential comparator de-
sign, the innovative design of the internal sample-and-hold
amplifier and the self-calibration scheme enable a very flat
response of all dynamic parameters beyond Nyquist, produc-
ing 6.9 ENOB with a 500 MHz input signal and a 1 GHz
sample rate while providing a 10-15 B.E.R. Output formatting
is offset binary and the LVDS digital outputs are compliant
with IEEE 1596.3-1996, with the exception of an adjustable
common mode voltage between 0.8V and 1.2V.
Internal Sample-and-Hold
■
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■
■
■
■
■
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Single +1.9V ±0.1V Operation
Choice of SDR or DDR output clocking
Interleave Mode for 2x Sampling Rate
Multiple ADC Synchronization Capability
Guaranteed No Missing Codes
Serial Interface for Extended Control
Fine Adjustment of Input Full-Scale Range and Offset
Duty Cycle Corrected Sample Clock
■
Key Specifications
Resolution
Max Conversion Rate
Bit Error Rate
ENOB @ 500 MHz Input
DNL
Power Consumption
8 Bits
1 GSPS (min)
10-15 (typ)
6.9 Bits (typ)
±0.15 LSB (typ)
■
■
■
■
■
■
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Each converter has a 1:2 demultiplexer that feeds two LVDS
buses and reduces the output data rate on each bus to half
the sampling rate. The two converters can be interleaved and
used as a single 2 GSPS ADC.
The converter typically consumes less than 3.5 mW in the
Power Down Mode and is available in a 128-lead, thermally
enhanced exposed pad LQFP and operates over the Indus-
trial (-40°C ≤ TA ≤ +85°C) temperature range.
Operating
Power Down Mode
1.6 W (typ)
3.5 mW (typ)
—
—
Applications
Direct RF Down Conversion
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■
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Digital Oscilloscopes
Satellite Set-top boxes
Communications Systems
Test Instrumentation
■
Block Diagram
20146753
© 2009 National Semiconductor Corporation
201467
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Ordering Information
Industrial Temperature Range (-40°C <
NS Package
TA < +85°C)
ADC08D1010DIYB
128-Pin Exposed Pad LQFP
Pin Configuration
20146701
* Exposed pad on back of package must be soldered to ground plane to ensure rated performance.
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2
Pin Descriptions and Equivalent Circuits
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Output Voltage Amplitude and Serial Interface Clock. Tie this pin
high for normal differential DCLK and data amplitude. Ground this
pin for a reduced differential output amplitude and reduced power
consumption. See Section 1.1.6. When the extended control mode
is enabled, this pin functions as the SCLK input which clocks in the
serial data. See Section 1.2 for details on the extended control
mode. See Section 1.3 for description of the serial interface.
3
OutV / SCLK
DCLK Edge Select, Double Data Rate Enable and Serial Data
Input. This input sets the output edge of DCLK+ at which the output
data transitions. (See Section 1.1.5.2). When this pin is floating or
connected to 1/2 the supply voltage, DDR clocking is enabled.
When the extended control mode is enabled, this pin functions as
the SDATA input. See Section 1.2 for details on the extended
control mode. See Section 1.3 for description of the serial
interface.
OutEdge / DDR /
SDATA
4
DCLK Reset. A positive pulse on this pin is used to reset and
synchronize the DCLK outs of multiple converters. See Section 1.5
for detailed description.
15
26
DCLK_RST
PD
Power Down. A logic high on the PD pin puts the entire device into
the Power Down Mode.
Calibration Cycle Initiate. A minimum 80 input clock cycles logic
low followed by a minimum of 80 input clock cycles high on this
pin initiates the self calibration sequence. See Section 2.4.2 for an
overview of self-calibration and Section 2.4.2.2 for a description of
on-command calibration.
30
CAL
Power Down Q. A logic high on the PDQ pin puts only the "Q" ADC
into the Power Down mode.
29
PDQ
Full Scale Range Select and Extended Control Enable. In non-
extended control mode, a logic low on this pin sets the full-scale
differential input range to 650 mVP-P. A logic high on this pin sets
the full-scale differential input range to 870 mVP-P. See Section
1.1.4. To enable the extended control mode, whereby the serial
interface and control registers are employed, allow this pin to float
or connect it to a voltage equal to VA/2. See Section 1.2 for
information on the extended control mode.
14
FSR/ECE
3
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
Calibration Delay, Dual Edge Sampling and Serial Interface Chip
Select. With a logic high or low on pin 14, this pin functions as
Calibration Delay and sets the number of input clock cycles after
power up before calibration begins (See Section 1.1.1). With pin
14 floating, this pin acts as the enable pin for the serial interface
input and the CalDly value becomes "0" (short delay with no
provision for a long power-up calibration delay). When this pin is
floating or connected to a voltage equal to VA/2, DES (Dual Edge
Sampling) mode is selected where the "I" input is sampled at twice
the input clock rate and the "Q" input is ignored. See Section
1.1.5.1.
CalDly / DES /
SCS
127
LVDS Clock input pins for the ADC. The differential clock signal
must be a.c. coupled to these pins. The input signal is sampled on
the falling edge of CLK+. See Section 1.1.2 for a description of
acquiring the input and Section 2.3 for an overview of the clock
inputs.
18
19
CLK+
CLK-
VINI+
VINI−
.
VINQ+
VINQ−
11
10
.
22
23
Analog signal inputs to the ADC. The differential full-scale input
range is 650 mVP-P when the FSR pin is low, or 870 mVP-P when
the FSR pin is high.
Common Mode Voltage. The voltage output at this pin is required
to be the common mode input voltage at VIN+ and VIN− when d.c.
coupling is used. This pin should be grounded when a.c. coupling
is used at the analog inputs. This pin is capable of sourcing or
sinking 100μA. See Section 2.2.
VCMO
7
VBG
31
Bandgap output voltage capable of 100 μA source/sink.
Calibration Running indication. This pin is at a logic high when
calibration is running.
126
CalRun
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4
Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
External bias resistor connection. Nominal value is 3.3k-Ohms
(±0.1%) to ground. See Section 1.1.1.
REXT
32
Temperature Diode Positive (Anode) and Negative (Cathode).
These pins may be used for die temperature measurements,
however no specified accuracy is implied or guaranteed. Noise
coupling from adjacent output data signals has been shown to
affect temperature measurements using this feature. See Section
2.6.2.
34
35
Tdiode_P
Tdiode_N
83 / 78
84 / 77
85 / 76
86 / 75
89 / 72
90 / 71
91 / 70
92 / 69
93 / 68
94 / 67
95 / 66
96 / 65
100 / 61
101 / 60
102 / 59
103 / 58
DI7− / DQ7−
DI7+ / DQ7+
DI6− / DQ6−
DI6+ / DQ6+
DI5− / DQ5−
DI5+ / DQ5+
DI4− / DQ4−
DI4+ / DQ4+
DI3− / DQ3−
DI3+ / DQ3+
DI2− / DQ2−
DI2+ / DQ2+
DI1− / DQ1−
DI1+ / DQ1+
DI0− / DQ0−
DI0+ / DQ0+
I and Q channel LVDS Data Outputs that are not delayed in the
output demultiplexer. Compared with the DId and DQd outputs,
these outputs represent the later time samples. These outputs
should always be terminated with a 100Ω differential resistor.
104 / 57 DId7− / DQd7−
105 / 56 DId7+ / DQd7+
106 / 55 DId6− / DQd6−
107 / 54 DId6+ / DQd6+
111 / 50 DId5− / DQd5−
112 / 49 DId5+ / DQd5+
113 / 48 DId4− / DQd4−
114 / 47 DId4+ / DQd4+
115 / 46 DId3− / DQd3−
116 / 45 DId3+ / DQd3+
117 / 44 DId2− / DQd2−
118 / 43 DId2+ / DQd2+
122 / 39 DId1− / DQd1−
123 / 38 DId1+ / DQd1+
124 / 37 DId0− / DQd0−
125 / 36 DId0+ / DQd0+
I and Q channel LVDS Data Outputs that are delayed by one CLK
cycle in the output demultiplexer. Compared with the DI/DQ
outputs, these outputs represent the earlier time sample. These
outputs should always be terminated with a 100Ω differential
resistor.
Out Of Range output. A differential high at these pins indicates that
the differential input is out of range (outside the range as defined
by the FSR pin).
79
80
OR+
OR-
Differential Clock outputs used to latch the output data. Delayed
and non-delayed data outputs are supplied synchronous to this
signal. This signal is at 1/2 the input clock rate in SDR mode and
at 1/4 the input clock rate in the DDR mode.
82
81
DCLK+
DCLK-
5
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Pin Functions
Pin No.
Symbol
Equivalent Circuit
Description
2, 5, 8, 13,
16, 17, 20,
25, 28, 33,
128
VA
Analog power supply pins. Bypass these pins to ground.
40, 51 ,62,
73, 88, 99,
110, 121
VDR
Output Driver power supply pins. Bypass these pins to DR GND.
Ground return for VA.
1, 6, 9, 12,
21, 24, 27,
41
GND
42, 53, 64,
74, 87, 97,
108, 119
Ground return for VDR
.
DR GND
NC
52, 63, 98,
109, 120
No Connection. Make no connection to these pins.
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6
Absolute Maximum Ratings
(Notes 1, 2)
Operating Ratings (Notes 1, 2)
Ambient Temperature Range
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA)
+1.8V to +2.0V
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
Driver Supply Voltage (VDR
)
+1.8V to VA
Analog Input Common Mode Voltage
VCMO ±50mV
Supply Voltage (VA, VDR
)
2.2V
VIN+, VIN- Voltage Range
(Maintaining Common Mode)
0V to 2.15V
(100% duty cycle)
0V to 2.5V
Supply Difference
VDR - VA
0V to 100 mV
(10% duty cycle)
Voltage on Any Input Pin
(Except VIN+, VIN-)
Ground Difference
(|GND - DR GND|)
CLK Pins Voltage Range
Differential CLK Amplitude
−0.15V to (VA +0.15V)
0V
0V to VA
Voltage on VIN+, VIN-
(Maintaining Common Mode)
Ground Difference
|GND - DR GND|
Input Current at Any Pin (Note 3)
Package Input Current (Note 3)
-0.15V to 2.5V
0.4VP-P to 2.0VP-P
0V to 100 mV
±25 mA
Package Thermal Resistance
Package
θJA
θJC (Top of
θJ-PAD
±50 mA
Package)
(Thermal Pad)
Power Dissipation at TA ≤ 85°C
ESD Susceptibility (Note 4)
Human Body Model
Machine Model
2.0 W
128-Lead
Exposed Pad
LQFP
25°C / W 10°C / W
2.8°C / W
ꢀ
2500V
250V
Soldering Temperature, Infrared,
10 seconds, (Note 5), (Applies
to standard plated package only)
235°C
Storage Temperature
−65°C to +150°C
Converter Electrical Characteristics
The following specifications apply after calibration for VA = VDR = +1.9VDC, OutV = 1.9V, VIN FSR (a.c. coupled) = differential
870mVP-P, CL = 10 pF, Differential, a.c. coupled Sinewave Input Clock, fCLK = 1 GHz at 0.5VP-P with 50% duty cycle, VBG = Floating,
Non-Extended Control Mode, SDR Mode, REXT = 3300Ω ±0.1%, Analog Signal Source Impedance = 100Ω Differential. Boldface
limits apply for TA = TMIN to TMAX. All other limits TA = 25°C, unless otherwise noted. (Notes 6, 7)
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
STATIC CONVERTER CHARACTERISTICS
DC Coupled, 1MHz Sine Wave Over
ranged
INL
Integral Non-Linearity (Best fit)
Differential Non-Linearity
±0.3
±0.9
±0.6
8
LSB (max)
LSB (max)
Bits
DC Coupled, 1MHz Sine Wave Over
ranged
DNL
±0.15
Resolution with No Missing
Codes
−1.5
0.5
LSB (min)
LSB (max)
VOFF
Offset Error
-0.45
VOFF_ADJ
PFSE
Input Offset Adjustment Range
Positive Full-Scale Error (Note 9)
Extended Control Mode
Extended Control Mode
±45
mV
−0.6
±25
±25
±15
mV (max)
Negative Full-Scale Error (Note
9)
NFSE
−1.31
±20
mV (max)
%FS
FS_ADJ
Full-Scale Adjustment Range
NORMAL MODE (Non DES) DYNAMIC CONVERTER CHARACTERISTICS
FPBW
B.E.R.
Full Power Bandwidth
Bit Error Rate
Normal Mode (non DES)
1.5
10-15
±0.6
±1.2
7.3
GHz
Error/Sample
dBFS
d.c. to 500 MHz
Gain Flatness
d.c. to 1 GHz
dBFS
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
Bits
ENOB
Effective Number of Bits
7.0
6.7
6.6
Bits (min)
Bits (min)
6.9
7
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Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 100 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
45.7
43.9
43.3
45.8
44.0
43.4
-53
dB
dB (min)
dB (min)
dB
Signal-to-Noise Plus Distortion
Ratio
SINAD
42.1
41.5
SNR
Signal-to-Noise Ratio
42.2
41.6
dB (min)
dB (min)
dB
THD
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
-53
-47.5
-47.5
dB (max)
dB (max)
dB
-53
−57
−57
−57
−62
−62
−62
53
2nd Harm
3rd Harm
dB
dB
dB
dB
dB
dB
SFDR
IMD
Spurious-Free dynamic Range
Intermodulation Distortion
53
47.5
47.5
dB (min)
dB (min)
53
fIN1 = 321 MHz, VIN = FSR − 7 dB
fIN2 = 326 MHz, VIN = FSR − 7 dB
-50
dB
(VIN+) − (VIN−) > + Full Scale
(VIN+) − (VIN−) < − Full Scale
255
0
Out of Range Output Code
(In addition to OR Output high)
INTERLEAVE MODE (DES Pin 127=Float) - DYNAMIC CONVERTER CHARACTERISTICS
FPBW
(DES)
Full Power Bandwidth
Dual Edge Sampling Mode
900
MHz
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
fIN = 248 MHz, VIN = FSR − 0.5 dB
fIN = 498 MHz, VIN = FSR − 0.5 dB
6.9
6.8
6.5
6.5
40.9
40.9
41
Bits (min)
Bits (min)
dB (min)
dB (min)
dB (min)
dB (min)
dB (min)
dB (min)
dB
ENOB
Effective Number of Bits
43.3
42.7
43.4
42.8
-54
-54
-61
-61
-66
-66
54
Signal to Noise Plus Distortion
Ratio
SINAD
SNR
Signal to Noise Ratio
41
-48
-48
THD
Total Harmonic Distortion
Second Harmonic Distortion
Third Harmonic Distortion
Spurious Free Dynamic Range
2nd Harm
3rd Harm
SFDR
dB
dB
dB
47
47
dB (min)
dB (min)
54
ANALOG INPUT AND REFERENCE CHARACTERISTICS
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
570
730
790
950
FSR pin 14 Low
650
Full Scale Analog Differential
Input Range
VIN
FSR pin 14 High
870
VCMO − 50
VCMO + 50
Analog Input Common Mode
Voltage
mV (min)
mV (max)
VCMI
VCMO
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8
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
Differential
0.02
1.6
pF
pF
Analog Input Capacitance,
normal operation (Notes 10, 11)
Each input pin to ground
Differential
CIN
0.08
2.2
pF
Analog Input Capacitance, DES
Mode (Notes 10, 11)
Each input pin to ground
pF
94
Ω (min)
Ω (max)
RIN
Differential Input Resistance
100
106
ANALOG OUTPUT CHARACTERISTICS
0.95
1.45
V (min)
V (max)
VCMO
ICMO = ±100 µA
Common Mode Output Voltage
1.26
VA = 1.8V
VA = 2.0V
0.60
0.66
V
V
VCMO input threshold to set DC
Coupling mode
VCMO_LVL
TC VCMO
CLOAD VCMO
VBG
Common Mode Output Voltage
Temperature Coefficient
TA = −40°C to +85°C
118
ppm/°C
pF
Maximum VCMO load
Capacitance
80
Bandgap Reference Output
Voltage
1.20
1.33
V (min)
V (max)
IBG = ±100 µA
1.26
28
TA = −40°C to +85°C,
IBG = ±100 µA
Bandgap Reference Voltage
Temperature Coefficient
TC VBG
CLOAD VBG
ppm/°C
pF
Maximum Bandgap Reference
load Capacitance
80
TEMPERATURE DIODE CHARACTERISTICS
192 µA vs. 12 µA,
TJ = 25°C
71.23
85.54
mV
mV
ΔVBE
Temperature Diode Voltage
192 µA vs. 12 µA,
TJ = 85°C
CHANNEL-TO-CHANNEL CHARACTERISTICS
Offset Match
1
1
LSB
LSB
Positive Full-Scale Match
Negative Full-Scale Match
Phase Matching (I, Q)
Zero offset selected in Control Register
Zero offset selected in Control Register
FIN = 1GHz
1
LSB
< 1
Degree
Crosstalk from I (Aggressor) to Q Aggressor = 867 MHz F.S.
X-TALK
X-TALK
-71
-71
dB
dB
(Victim) Channel
Victim = 100 MHz F.S.
Crosstalk from Q (Aggressor) to I Aggressor = 867 MHz F.S.
(Victim) Channel
Victim = 100 MHz F.S.
CLOCK INPUT CHARACTERISTICS
VP-P (min)
VP-P (max)
0.4
2.0
Sine Wave Clock
0.6
0.6
VID
Differential Clock Input Level
VP-P (min)
VP-P (max)
0.4
2.0
Square Wave Clock
II
VIN = 0 or VIN = VA
Differential
Input Current
±1
0.02
1.5
µA
pF
pF
CIN
Input Capacitance (Notes 10, 11)
Each input to ground
DIGITAL CONTROL PIN CHARACTERISTICS
VIH
VIL
CIN
0.85 x VA
0.15 x VA
Logic High Input Voltage
Logic Low Input Voltage
(Note 12)
(Note 12)
V (min)
V (max)
pF
Input Capacitance (Notes 11, 13) Each input to ground
1.2
DIGITAL OUTPUT CHARACTERISTICS
9
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Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
Parameter
Conditions
mVP-P (min)
mVP-P (max)
mVP-P (min)
mVP-P (max)
400
920
280
720
Measured differentially, OutV = VA, VBG
= Floating, (Note 15)
710
510
VOD
LVDS Differential Output Voltage
Measured differentially, OutV = GND,
VBG = Floating, (Note 15)
Change in LVDS Output Swing
Between Logic Levels
Δ VO DIFF
VOS
±1
800
1200
±1
mV
mV
mV
mV
Output Offset Voltage, see Figure
1
VBG = Floating
Output Offset Voltage, see Figure
1
VOS
VBG = VA (Note 15)
Output Offset Voltage Change
Between Logic Levels
Δ VOS
IOS
Output Short Circuit Current
Differential Output Impedance
CalRun High Level Output
CalRun Low Level Output
Output+ & Output- connected to 0.8V
±4
mA
Ohms
V
ZO
100
1.65
0.15
VOH
VOL
IOH = -400uA(Note 12)
IOH = 400uA(Note 12)
1.5
0.3
V
POWER SUPPLY CHARACTERISTICS
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
660
430
1.8
765
508
mA (max)
mA (max)
mA
IA
Analog Supply Current
Output Driver Supply Current
Power Consumption
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
200
112
0.012
275
157
mA (max)
mA (max)
mA
IDR
PD = PDQ = Low
PD = Low, PDQ = High
PD = PDQ = High
1.6
1.0
3.5
1.97
1.27
W (max)
W (max)
mW
PD
Change in Full Scale Error with change
in VA from 1.8V to 2.0V
D.C. Power Supply Rejection
Ratio
PSRR1
PSRR2
30
51
dB
dB
A.C. Power Supply Rejection
Ratio
248 MHz, 50mVP-P riding on VA
AC ELECTRICAL CHARACTERISTICS
fCLK1
fCLK2
fCLK2
Maximum Input Clock Frequency Normal Mode (non DES) or DES Mode
Minimum Input Clock Frequency Normal Mode (non DES)
Minimum Input Clock Frequency DES Mode
1.3
200
500
1.0
GHz (min)
MHz
MHz
20
80
% (min)
% (max)
200 MHz ≤ Input clock frequency ≤ 1
Input Clock Duty Cycle
50
50
GHz (Normal Mode) (Note 12)
20
80
% (min)
% (max)
500MHz ≤ Input clock frequency ≤ 1
GHz (DES Mode) (Note 12)
Input Clock Duty Cycle
tCL
tCH
Input Clock Low Time
Input Clock High Time
(Note 11)
(Note 11)
500
500
200
200
ps (min)
ps (min)
45
55
% (min)
% (max)
DCLK Duty Cycle
(Note 11)
50
tRS
tRH
Reset Setup Time
Reset Hold Time
(Note 11)
(Note 11)
150
250
ps
ps
Synchronizing Edge to DCLK
Output Delay
tSD
tOD + tOSK
ns
Clock Cycles
(min)
tRPW
tLHT
Reset Pulse Width
(Note 11)
4
Differential Low to High Transition
Time
10% to 90%, CL = 2.5 pF
250
ps
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10
Typical
(Note 8)
Limits
(Note 8)
Units
(Limits)
Symbol
tHLT
Parameter
Conditions
Differential High to Low Transition
Time
10% to 90%, CL = 2.5 pF
250
±50
ps
50% of DCLK transition to 50% of Data
transition, SDR Mode
tOSK
DCLK to Data Output Skew
ps (max)
and DDR Mode, 0° DCLK (Note 11)
tSU
tH
tAD
tAJ
Data to DCLK Set-Up Time
DCLK to Data Hold Time
Sampling (Aperture) Delay
Aperture Jitter
DDR Mode, 90° DCLK (Note 11)
DDR Mode, 90° DCLK (Note 11)
Input CLK+ Fall to Acquisition of Data
750
890
1.3
0.4
ps
ps
ns
ps rms
Input Clock to Data Output Delay 50% of Input Clock transition to 50% of
tOD
3.1
ns
(in addition to Pipeline Delay)
Data transition
DI Outputs
13
14
DId Outputs
Normal Mode
DES Mode
13
Pipeline Delay (Latency)
(Notes 11, 14)
Input Clock
Cycles
DQ Outputs
13.5
14
Normal Mode
DES Mode
DQd Outputs
14.5
Differential VIN step from ±1.2V to 0V to
get accurate conversion
Input Clock
Cycle
Over Range Recovery Time
1
PD low to Rated Accuracy
Conversion (Wake-Up Time)
tWU
500
ns
DCS
(Note 11)
(Note 11)
1
100
2.5
1
µs
MHz
fSCLK
tSSU
tSH
Serial Clock Frequency
Data to Serial Clock Setup Time (Note 11)
ns (min)
ns (min)
ns (min)
ns (min)
Clock Cycles
Data to Serial Clock Hold Time
Serial Clock Low Time
(Note 11)
4
4
Serial Clock High Time
Calibration Cycle Time
tCAL
1.4 x 105
Clock Cycles
(min)
tCAL_L
CAL Pin Low Time
CAL Pin High Time
See Figure 9(Note 11)
See Figure 9(Note 11)
80
80
Clock Cycles
(min)
tCAL_H
CalDly = Low
See 1.1.1 Self Calibration, Figure 9,
(Note 11)
Clock Cycles
(min)
225
Calibration delay determined by
pin 127 state.
tCalDly
CalDly = High
See 1.1.1, Self Calibration, Figure 9,
(Note 11)
Clock Cycles
(max)
231
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. There is no guarantee of operation at the Absolute Maximum
Ratings. Operating Ratings indicate conditions for which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications
and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions.
Note 2: All voltages are measured with respect to GND = DR GND = 0V, unless otherwise specified.
Note 3: When the input voltage at any pin exceeds the power supply limits (that is, less than GND or greater than VA), the current at that pin should be limited to
25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 25 mA to
two. This limit is not placed upon the power, ground and digital output pins.
Note 4: Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO Ohms.
Note 5: See AN-450, “Surface Mounting Methods and Their Effect on Product Reliability”.
Note 6: The analog inputs are protected as shown below. Input voltage magnitudes beyond the Absolute Maximum Ratings may damage this device.
11
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20146704
Note 7: To guarantee accuracy, it is required that VA and VDR be well bypassed. Each supply pin must be decoupled with separate bypass capacitors. Additionally,
achieving rated performance requires that the backside exposed pad be well grounded.
Note 8: Typical figures are at TA = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average Outgoing Quality
Level).
Note 9: Calculation of Full-Scale Error for this device assumes that the actual reference voltage is exactly its nominal value. Full-Scale Error for this device,
therefore, is a combination of Full-Scale Error and Reference Voltage Error. See Figure 2. For relationship between Gain Error and Full-Scale Error, see
Specification Definitions for Gain Error.
Note 10: The analog and clock input capacitances are die capacitances only. Additional package capacitances of 0.65 pF differential and 0.95 pF each pin to
ground are isolated from the die capacitances by lead and bond wire inductances.
Note 11: This parameter is guaranteed by design and is not tested in production.
Note 12: This parameter is guaranteed by design and/or characterization and is not tested in production.
Note 13: The digital control pin capacitances are die capacitances only. Additional package capacitance of 1.6 pF each pin to ground are isolated from the die
capacitances by lead and bond wire inductances.
Note 14: Each of the two converters of the ADC08D1010 has two LVDS output buses, which each clock data out at one half the sample rate. The data at each
bus is clocked out at one half the sample rate. The second bus (D0 through D7) has a pipeline latency that is one Input Clock cycle less than the latency of the
first bus (Dd0 through Dd7).
Note 15: Tying VBG to the supply rail will increase the output offset voltage (VOS) by 400mV (typical), as shown in the VOS specification above. Tying VBG to the
supply rail will also affect the differential LVDS output voltage (VOD), causing it to increase by 40mV (typical).
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12
Specification Definitions
APERTURE (SAMPLING) DELAY is that time required after
the fall of the clock input for the sampling switch to open. The
Sample/Hold circuit effectively stops capturing the input sig-
nal and goes into the “hold” mode the aperture delay time
(tAD) after the input clock goes low.
APERTURE JITTER (tAJ) is the variation in aperture delay
from sample to sample. Aperture jitter shows up as input
noise.
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Bit Error Rate (B.E.R.) is the probability of error and is de-
fined as the probable number of errors per unit of time divided
by the number of bits seen in that amount of time. A B.E.R. of
10-18 corresponds to a statistical error in one bit about every
four (4) years.
FIGURE 1.
LVDS OUTPUT OFFSET VOLTAGE (VOS) is the midpoint
between the D+ and D- pins output voltage; i.e., [(VD+) +
( VD-)]/2.
CLOCK DUTY CYCLE is the ratio of the time that the clock
wave form is at a logic high to the total time of one clock pe-
riod.
MISSING CODES are those output codes that are skipped
and will never appear at the ADC outputs. These codes can-
not be reached with any input value.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of
the maximum deviation from the ideal step size of 1 LSB.
Measured at 1 GSPS with a ramp input.
MSB (MOST SIGNIFICANT BIT) is the bit that has the largest
value or weight. Its value is one half of full scale.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE
BITS) is another method of specifying Signal-to-Noise and
Distortion Ratio, or SINAD. ENOB is defined as (SINAD −
1.76) / 6.02 and says that the converter is equivalent to a per-
fect ADC of this (ENOB) number of bits.
NEGATIVE FULL-SCALE ERROR (NFSE) is a measure of
how far the last code transition is from the ideal 1/2 LSB above
a differential −435 mV with the FSR pin high, or 1/2 LSB above
a differential −325 mV with the FSR pin low. For the AD-
C08D1010 the reference voltage is assumed to be ideal, so
this error is a combination of full-scale error and reference
voltage error.
FULL POWER BANDWIDTH (FPBW) is a measure of the
frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
OFFSET ERROR (VOFF) is a measure of how far the mid-
scale point is from the ideal zero voltage differential input.
GAIN ERROR is the deviation from the ideal slope of the
transfer function. It can be calculated from Offset and Full-
Scale Errors:
Offset Error = Actual Input causing average of 8k sam-
ples to result in an average code of 127.5.
Positive Gain Error = Offset Error − Positive Full-Scale
Error
OUTPUT DELAY (tOD) is the time delay after the falling edge
of DCLK before the data update is present at the output pins.
Negative Gain Error = −(Offset Error − Negative Full-
Scale Error)
OVER-RANGE RECOVERY TIME is the time required after
the differential input voltages goes from ±1.2V to 0V for the
converter to recover and make a conversion with its rated ac-
curacy.
Gain Error = Negative Full-Scale Error − Positive Full-
Scale Error = Positive Gain Error + Negative Gain Error
INTEGRAL NON-LINEARITY (INL) is a measure of the de-
viation of each individual code from a straight line through the
input to output transfer function. The deviation of any given
code from this straight line is measured from the center of that
code value. The best fit method is used.
PIPELINE DELAY (LATENCY) is the number of input clock
cycles between initiation of conversion and when that data is
presented to the output driver stage. New data is available at
every clock cycle, but the data lags the conversion by the
Pipeline Delay plus the tOD
.
INTERMODULATION DISTORTION (IMD) is the creation of
additional spectral components as a result of two sinusoidal
frequencies being applied to the ADC input at the same time.
It is defined as the ratio of the power in the second and third
order intermodulation products to the power in one of the
original frequencies. IMD is usually expressed in dBFS.
POSITIVE FULL-SCALE ERROR (PFSE) is a measure of
how far the last code transition is from the ideal 1-1/2 LSB
below a differential +435 mV with the FSR pin high, or 1-1/2
LSB below a differential +325 mV with the FSR pin low. For
the ADC08D1010 the reference voltage is assumed to be
ideal, so this error is a combination of full-scale error and ref-
erence voltage error.
LSB (LEAST SIGNIFICANT BIT) is the bit that has the small-
est value or weight of all bits. This value is
POWER SUPPLY REJECTION RATIO (PSRR) can be one
of two specifications. PSRR1 (DC PSRR) is the ratio of the
change in full-scale error that results from a power supply
voltage change from 1.8V to 2.0V. PSRR2 (AC PSRR) is a
measure of how well an a.c. signal riding upon the power
supply is rejected from the output and is measured with a 248
MHz, 50 mVP-P signal riding upon the power supply. It is the
ratio of the output amplitude of that signal at the output to its
amplitude on the power supply pin. PSRR is expressed in dB.
VFS / 2n
where VFS is the differential full-scale amplitude of 650 mV or
870 mV as set by the FSR input and "n" is the ADC resolution
in bits, which is 8 for the ADC08D1010.
LVDS DIFFERENTIAL OUTPUT VOLTAGE (VOD) is the ab-
solute value of the difference between the VD+ & VD- outputs;
each measured with respect to Ground.
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SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in
dB, of the rms value of the input signal at the output to the rms
value of the sum of all other spectral components below one-
half the sampling frequency, not including harmonics or d.c.
where Af1 is the RMS power of the fundamental (output) fre-
quency and Af2 through Af10 are the RMS power of the first 9
harmonic frequencies in the output spectrum.
– Second Harmonic Distortion (2nd Harm) is the differ-
ence, expressed in dB, between the RMS power in the input
frequency seen at the output and the power in its 2nd har-
monic level at the output.
SIGNAL TO NOISE PLUS DISTORTION (S/(N+D) or
SINAD) is the ratio, expressed in dB, of the rms value of the
input signal at the output to the rms value of all of the other
spectral components below half the input clock frequency, in-
cluding harmonics but excluding d.c.
– Third Harmonic Distortion (3rd Harm) is the difference
expressed in dB between the RMS power in the input fre-
quency seen at the output and the power in its 3rd harmonic
level at the output.
SPURIOUS-FREE DYNAMIC RANGE (SFDR) is the differ-
ence, expressed in dB, between the rms values of the input
signal at the output and the peak spurious signal, where a
spurious signal is any signal present in the output spectrum
that is not present at the input, excluding d.c.
TOTAL HARMONIC DISTORTION (THD) is the ratio ex-
pressed in dB, of the rms total of the first nine harmonic levels
at the output to the level of the fundamental at the output. THD
is calculated as
Transfer Characteristic
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FIGURE 2. Input / Output Transfer Characteristic
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14
Timing Diagrams
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FIGURE 3. ADC08D1010 Timing — SDR Clocking
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FIGURE 4. ADC08D1010 Timing — DDR Clocking
15
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20146719
FIGURE 5. Serial Interface Timing
20146720
FIGURE 6. Clock Reset Timing in DDR Mode
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FIGURE 7. Clock Reset Timing in SDR Mode with OUTEDGE Low
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20146724
FIGURE 8. Clock Reset Timing in SDR Mode with OUTEDGE High
20146725
FIGURE 9. Self Calibration and On-Command Calibration Timing
17
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Typical Performance Characteristics VA=VDR=1.9V, FCLK=1000MHz, TA=25°C unless otherwise stated.
INL vs. CODE
INL vs. TEMPERATURE
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DNL vs. CODE
DNL vs. TEMPERATURE
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POWER DISSIPATION vs. SAMPLE RATE
ENOB vs. CLOCK DUTY CYCLE
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ENOB vs. TEMPERATURE
ENOB vs. SAMPLE RATE
SNR vs. TEMPERATURE
ENOB vs. SUPPLY VOLTAGE
ENOB vs. INPUT FREQUENCY
SNR vs. SUPPLY VOLTAGE
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20146768
20146777
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19
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SNR vs. SAMPLE RATE
THD vs. TEMPERATURE
THD vs. SAMPLE RATE
SNR vs. INPUT FREQUENCY
THD vs. SUPPLY VOLTAGE
THD vs. INPUT FREQUENCY
20146770
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20146774
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20146773
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SFDR vs. TEMPERATURE
SFDR vs. SUPPLY VOLTAGE
SFDR vs. INPUT FREQUENCY
FULL POWER BANDWIDTH
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SFDR vs. SAMPLE RATE
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CROSSTALK vs. SOURCE FREQUENCY
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During the calibration process, the input termination resistor
is trimmed to a value that is equal to REXT / 33. This external
resistor is located between pin 32 and ground. REXT must be
3300 Ω ±0.1%. With this value, the input termination resistor
is trimmed to be 100 Ω. Because REXT is also used to set the
proper current for the Track and Hold amplifier, for the pream-
plifiers and for the comparators, other values of REXT should
not be used.
1.0 Functional Description
The ADC08D1010 is a versatile A/D Converter with an inno-
vative architecture permitting very high speed operation. The
controls available ease the application of the device to circuit
solutions. Optimum performance requires adherence to the
provisions discussed here and in the Applications Information
Section.
While it is generally poor practice to allow an active pin to float,
pins 4, 14 and 127 of the ADC08D1010 are designed to be
left floating without jeopardy. In all discussions throughout this
data sheet, whenever a function is called by allowing a control
pin to float, connecting that pin to a potential of one half the
VA supply voltage will have the same effect as allowing it to
float.
In normal operation, calibration is performed just after appli-
cation of power and whenever a valid calibration command is
given, which is holding the CAL pin low for at least 80 input
clock cycles, then hold it high for at least another 80 input
clock cycles. The time taken by the calibration procedure is
specified in the A.C. Characteristics Table. Holding the CAL
pin high upon power up will prevent the calibration process
from running until the CAL pin experiences the above-men-
tioned 80 input clock cycles low followed by 80 cycles high.
1.1 OVERVIEW
The ADC08D1010 uses a calibrated folding and interpolating
architecture that achieves over 6.9 effective bits. The use of
folding amplifiers greatly reduces the number of comparators
and power consumption. Interpolation reduces the number of
front-end amplifiers required, minimizing the load on the input
signal and further reducing power requirements. In addition
to other things, on-chip calibration reduces the INL bow often
seen with folding architectures. The result is an extremely
fast, high performance, low power converter.
CalDly (pin 127) is used to select one of two delay times after
the application of power to the start of calibration. This cali-
bration delay is 225 input clock cycles (about 33.6 ms at 1
GSPS) with CalDly low, or 231 input clock cycles (about 2.15
seconds at 1 GSPS) with CalDly high. These delay values
allow the power supply to come up and stabilize before cali-
bration takes place. If the PD pin is high upon power-up, the
calibration delay counter will be disabled until the PD pin is
brought low. Therefore, holding the PD pin high during power
up will further delay the start of the power-up calibration cycle.
The best setting of the CalDly pin depends upon the power-
on settling time of the power supply.
The analog input signal that is within the converter's input
voltage range is digitized to eight bits at speeds of 200 MSPS
to 1.0 GSPS, typical. Differential input voltages below nega-
tive full-scale will cause the output word to consist of all
zeroes. Differential input voltages above positive full-scale
will cause the output word to consist of all ones. Either of
these conditions at either the "I" or "Q" input will cause the OR
(Out of Range) output to be activated. This single OR output
indicates when the output code from one or both of the chan-
nels is below negative full scale or above positive full scale.
The CalRun output is high whenever the calibration proce-
dure is running. This is true whether the calibration is done at
power-up or on-command.
1.1.2 Acquiring the Input
Data is acquired at the falling edge of CLK+ (pin 18) and the
digital equivalent of that data is available at the digital outputs
13 input clock cycles later for the DI and DQ output buses and
14 input clock cycles later for the DId and DQd output buses.
There is an additional internal delay called tOD before the data
is available at the outputs. See the Timing Diagram. The AD-
C08D1010 will convert as long as the input clock signal is
present. The fully differential comparator design and the in-
novative design of the sample-and-hold amplifier, together
with self calibration, enables a very flat SINAD/ENOB re-
sponse beyond 1.0 GHz. The ADC08D1010 output data sig-
naling is LVDS and the output format is offset binary.
Each of the two converters has a 1:2 demultiplexer that feeds
two LVDS output buses. The data on these buses provide an
output word rate on each bus at half the ADC sampling rate
and must be interleaved by the user to provide output words
at the full conversion rate.
The output levels may be selected to be normal or reduced.
Using reduced levels saves power but could result in erro-
neous data capture of some or all of the bits, especially at
higher sample rates and in marginally designed systems.
1.1.1 Self-Calibration
1.1.3 Control Modes
A self-calibration is performed upon power-up and can also
be invoked by the user upon command. Calibration trims the
100Ω analog input differential termination resistor and mini-
mizes full-scale error, offset error, DNL and INL, resulting in
maximizing SNR, THD, SINAD (SNDR) and ENOB. Internal
bias currents are also set with the calibration process. All of
this is true whether the calibration is performed upon power
up or is performed upon command. Running the self calibra-
tion is an important part of this chip's functionality and is
required in order to obtain adequate performance. In addition
to the requirement to be run at power-up, self calibration must
be re-run whenever the sense of the FSR pin is changed. For
best performance, we recommend that self calibration be run
20 seconds or more after application of power and whenever
the operating temperature changes significantly, according to
the system design performance specifications. See Section
2.4.2.2 for more information. Calibration can not be initiated
or run while the device is in the power-down mode. See Sec-
tion 1.1.7 for information on the interaction between Power
Down and Calibration.
Much of the user control can be accomplished with several
control pins that are provided. Examples include initiation of
the calibration cycle, power down mode and full scale range
setting. However, the ADC08D1010 also provides an Extend-
ed Control mode whereby a serial interface is used to access
register-based control of several advanced features. The Ex-
tended Control mode is not intended to be enabled and
disabled dynamically. Rather, the user is expected to employ
either the normal control mode or the Extended Control mode
at all times. When the device is in the Extended Control mode,
pin-based control of several features is replaced with register-
based control and those pin-based controls are disabled.
These pins are OutV (pin 3), OutEdge/DDR (pin 4), FSR (pin
14) and CalDly/DES (pin 127). See Section 1.2 for details on
the Extended Control mode.
1.1.4 The Analog Inputs
The ADC08D1010 must be driven with a differential input sig-
nal. Operation with a single-ended signal is not recommend-
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22
ed. It is important that the input signals are either a.c. coupled
to the inputs with the VCMO pin grounded, or d.c. coupled with
the VCMO pin left floating. An input common mode voltage
equal to the VCMO output must be provided when d.c. coupling
is used.
1.1.5.1 Dual-Edge Sampling
The DES mode allows one of the ADC08D1010's inputs (I or
Q Channel) to be sampled by both ADCs. One ADC samples
the input on the positive edge of the input clock and the other
ADC samples the same input on the other edge of the input
clock. A single input is thus sampled twice per input clock cy-
cle, resulting in an overall sample rate of twice the input clock
frequency, or 2 GSPS with a 1 GHz input clock.
Two full-scale range settings are provided with pin 14 (FSR).
A high on pin 14 causes an input full-scale range setting of
870 mVP-P, while grounding pin 14 causes an input full-scale
range setting of 650 mVP-P. The full-scale range setting op-
erates equally on both ADCs.
In this mode the outputs are interleaved such that the data is
effectively demultiplexed 1:4. Since the sample rate is dou-
bled, each of the 4 output buses have a 500 MSPS output rate
with a 1 GHz input clock. All data is available in parallel. The
four bytes of parallel data that are output with each clock is in
the following sampling order, from the earliest to the latest:
DQd, DId, DQ, DI. Table 1 indicates what the outputs repre-
sent for the various sampling possibilities.
In the Extended Control mode, the full-scale input range can
be set to values between 560 mVP-P and 840 mVP-P through
a serial interface. See Section 2.2
1.1.5 Clocking
The ADC08D1010 must be driven with an a.c. coupled, dif-
ferential clock signal. Section 2.3 describes the use of the
clock input pins. A differential LVDS output clock is available
for use in latching the ADC output data into whatever device
is used to receive the data.
In the non-extended mode of operation only the "I" input can
be sampled in the DES mode. In the extended mode of op-
eration the user can select which input is sampled.
The ADC08D1010 also includes an automatic clock phase
background calibration feature which can be used in DES
mode to automatically and continuously adjust the clock
phase of the I and Q channel. This feature removes the need
to adjust the clock phase setting manually and provides opti-
mal Dual-Edge Sampling ENOB performance.
The ADC08D1010 offers options for input and output clock-
ing. These options include a choice of Dual Edge Sampling
(DES) or "interleaved mode" where the ADC08D1010 per-
forms as a single device converting at twice the input clock
rate, a choice of which DCLK edge the output data transitions
on, and a choice of Single Data Rate (SDR) or Double Data
Rate (DDR) outputs.
IMPORTANT NOTE: The background calibration feature in
DES mode does not replace the requirement for On-Com-
mand Calibration which should be run before entering DES
mode, or if a large swing in ambient temperature is experi-
enced by the device.
The ADC08D1010 also has the option to use a duty cycle
corrected clock receiver as part of the input clock circuit. This
feature is enabled by default and provides improved ADC
clocking especially in the Dual-Edge Sampling mode (DES).
This circuitry allows the ADC to be clocked with a signal
source having a duty cycle ratio of 80 / 20 % (worst case) for
both the normal and the Dual Edge Sampling modes.
TABLE 1. Input Channel Samples Produced at Data Outputs
Data Outputs (Always
sourced with respect to fall
of DCLK)
Dual-Edge Sampling Mode (DES)
Normal Sampling Mode
I-Channel Selected
Q-Channel Selected *
"I" Input Sampled with Fall of "I" Input Sampled with Fall of "Q" Input Sampled with Fall of
DI
CLK 13 cycles earlier. CLK 13 cycles earlier. CLK 13 cycles earlier.
"I" Input Sampled with Fall of "I" Input Sampled with Fall of "Q" Input Sampled with Fall of
CLK 14 cycles earlier. CLK 14 cycles earlier. CLK 14 cycles earlier.
"Q" Input Sampled with Fall of "I" Input Sampled with Rise of "Q" Input Sampled with Rise
DId
DQ
CLK 13 cycles earlier.
CLK 13.5 cycles earlier.
of CLK 13.5 cycles earlier.
"Q" Input Sampled with Fall of
CLK 14 cycles after being
sampled.
"I" Input Sampled with Rise of "Q" Input Sampled with Rise
CLK 14.5 cycles earlier. of CLK 14.5 cycles earlier.
DQd
* Note that, in the DES mode, the "Q" channel input can only be selected for sampling in the Extended Control Mode.
1.1.5.2 OutEdge Setting
(DCLK) frequency is the same as the data rate of the two out-
put buses. With double data rate the DCLK frequency is half
the data rate and data is sent to the outputs on both DCLK
clock edges. DDR clocking is enabled in non-Extended Con-
trol mode by allowing pin 4 to float.
To help ease data capture in the SDR mode, the output data
may be caused to transition on either the positive or the neg-
ative edge of the output data clock (DCLK). This is chosen
with the OutEdge input (pin 4). A high on the OutEdge input
pin causes the output data to transition on the rising edge of
DCLK, while grounding this input causes the output to transi-
tion on the falling edge of DCLK. See Section 2.4.3.
1.1.6 The LVDS Outputs
The data outputs, the Out Of Range (OR) and DCLK, are
LVDS. Output current sources provide 3 mA of output current
to a differential 100 Ohm load when the OutV input (pin 14) is
high or 2.2 mA when the OutV input is low. For short LVDS
lines and low noise systems, satisfactory performance may
be realized with the OutV input low, which results in lower
1.1.5.3 Double Data Rate
A choice of single data rate (SDR) or double data rate (DDR)
output is offered. With single data rate the output clock
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power consumption. If the LVDS lines are long and/or the
system in which the ADC08D1010 is used is noisy, it may be
necessary to tie the OutV pin high.
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state. Calibration will
function with the "Q" channel powered down, but that channel
will not be calibrated if PDQ is high. If the "Q" channel is sub-
sequently to be used, it is necessary to perform a calibration
after PDQ is brought low.
The LVDS data output have a typical common mode voltage
of 800mV when the VBG pin is unconnected and floating. This
common mode voltage can be increased to 1.2V by tying the
VBG pin to VA if a higher common mode is required.
IMPORTANT NOTE: Tying the VBG pin to VA will also in-
crease the differential LVDS output voltage by up to 40mV.
1.1.7 Power Down
1.2 NORMAL/EXTENDED CONTROL
The ADC08D1010 is in the active state when the Power Down
pin (PD) is low. When the PD pin is high, the device is in the
power down mode. In this power down mode the data output
pins (positive and negative) are put into a high impedance
state and the devices power consumption is reduced to a
minimal level. The DCLK+/- and OR +/- are not tri-stated, they
are weakly pulled down to ground internally. Therefore when
both I and Q are powered down the DCLK +/- and OR +/-
should not be terminated to a DC voltage.
The ADC08D1010 may be operated in one of two modes. In
the simpler "normal" control mode, the user affects available
configuration and control of the device through several control
pins. The "extended control mode" provides additional con-
figuration and control options through a serial interface and a
set of 8 registers. The two control modes are selected with
pin 14 (FSR/ECE: Extended Control Enable). The choice of
control modes is required to be a fixed selection and is not
intended to be switched dynamically while the device is op-
erational.
A high on the PDQ pin will power down the "Q" channel and
leave the "I" channel active. There is no provision to power
down the "I" channel independently of the "Q" channel. Upon
return to normal operation, the pipeline will contain meaning-
less information.
Table 2 shows how several of the device features are affected
by the control mode chosen.
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
TABLE 2. Features and Modes
Normal Control Mode
Feature
Extended Control Mode
Selected with DE bit in the Configuration
Register
SDR or DDR Clocking
Selected with pin 4
Selected with DCP bit in the
Configuration Register. See 1.4
REGISTER DESCRIPTION
DDR Clock Phase
Not Selectable (0° Phase Only)
Selected with pin 4
SDR Data transitions with rising or falling
DCLK edge
Selected with the OE bit in the
Configuration Register
Selected with the OV bit (9)in the
Configuration Register
LVDS output level
Selected with pin 3
Power-On Calibration Delay
Delay Selected with pin 127
Short delay only.
Up to 512 step adjustments over a
nominal range of 560 mV to 840 mV.
Separate range selected for I- and Q-
Channels. Selected using registers 3H
and Bh
Options (650 mVP-P or 870 mVP-P
)
Full-Scale Range
selected with pin 14. Selected range
applies to both channels.
Separate 45 mV adjustments in 512
steps for each channel using registers 2h
and Ah
Input Offset Adjust
Not possible
Dual Edge Sampling Selection
Enabled with pin 127
Enabled through DES Enable Register
Dual Edge Sampling Input Channel
Selection
Either I- or Q-Channel input may be
sampled by both ADCs
Only I-Channel Input can be used
Automatic Clock Phase control can be
selected by setting bit 14 in the DES
Enable register (Dh). The clock phase
can also be adjusted manually through
the Coarse & Fine registers (Eh and Fh)
The Clock Phase is adjusted
automatically
DES Sampling Clock Adjustment
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24
The default state of the Extended Control Mode is set upon
power-on reset (internally performed by the device) and is
shown in Table 3.
quence is such that a "0" is loaded first. These 12 bits form
the header. The next 4 bits are the address of the register that
is to be written to and the last 16 bits are the data written to
the addressed register. The addresses of the various regis-
ters are indicated in Table 4.
TABLE 3. Extended Control Mode Operation (Pin 14
Floating)
Refer to the Register Description (Section 1.4) for information
on the data to be written to the registers.
Extended Control Mode
Feature
Default State
Subsequent register accesses may be performed immediate-
ly, starting with the 33rd SCLK. This means that the SCS input
does not have to be de-asserted and asserted again between
register addresses. It is possible, although not recommended,
to keep the SCS input permanently enabled (at a logic low)
when using extended control.
SDR or DDR Clocking
DDR Clock Phase
DDR Clocking
Data changes with DCLK
edge (0° phase)
Normal amplitude
LVDS Output Amplitude
Calibration Delay
(710 mVP-P
)
IMPORTANT NOTE: The Serial Interface should not be used
when calibrating the ADC. Doing so will impair the perfor-
mance of the device until it is re-calibrated correctly. Pro-
gramming the serial registers will also reduce dynamic
performance of the ADC for the duration of the register access
time.
Short Delay
700 mV nominal for both
channels
Full-Scale Range
No adjustment for either
channel
Input Offset Adjust
TABLE 4. Register Addresses
4-Bit Address
Dual Edge Sampling (DES)
Not enabled
Loading Sequence:
A3 loaded after Fixed Header Pattern, A0 loaded last
1.3 THE SERIAL INTERFACE
IMPORTANT NOTE: During the initial write using the serial
interface, all 8 user registers must be written with desired or
default values. In addition, the first write to the DES Enable
register (Dh) must load the default value (0x3FFFh). Once all
registers have been written once, other desired settings, in-
cluding enabling DES can be loaded.
A3
0
A2
0
A1
0
A0
0
Hex Register Addressed
0h
1h
2h
3h
Reserved
Configuration
"I" Ch Offset
0
0
0
1
0
0
1
0
The 3-pin serial interface is enabled only when the device is
in the Extended Control mode. The pins of this interface are
Serial Clock (SCLK), Serial Data (SDATA) and Serial Inter-
face Chip Select (SCS) Eight write only registers are acces-
sible through this serial interface.
0
0
1
1
"I" Ch Full-Scale
Voltage Adjust
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
4h
5h
6h
7h
8h
9h
Ah
Bh
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
"Q" Ch Offset
SCS: This signal should be asserted low while accessing a
register through the serial interface. Setup and hold times with
respect to the SCLK must be observed.
SCLK: Serial data input is accepted with the rising edge of
this signal. There is no minimum frequency requirement for
SCLK.
SDATA: Each register access requires a specific 32-bit pat-
tern at this input. This pattern consists of a header, register
address and register value. The data is shifted in MSB first.
Setup and hold times with respect to the SCLK must be ob-
served. See the Timing Diagram.
"Q" Ch Full-Scale
Voltage Adjust
1
1
1
1
1
1
1
1
0
0
1
1
0
1
0
1
Ch
Dh
Reserved
DES Enable
Eh DES Coarse Adjust
Fh DES Fine Adjust
Each Register access consists of 32 bits, as shown in Figure
5 of the Timing Diagrams. The fixed header pattern is 0000
0000 0001 (eleven zeros followed by a 1). The loading se-
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1.4 REGISTER DESCRIPTION
Bit 8
OE: Output Edge. This bit selects the DCLK
edge with which the data words transition in
the SDR mode and has the same effect as the
OutEdge pin in the normal control mode.
When this bit is 1, the data outputs change with
the rising edge of DCLK+. When this bit is 0,
the data output change with the falling edge of
DCLK+.
Eight write-only registers provide several control and config-
uration options in the Extended Control Mode. These regis-
ters have no effect when the device is in the Normal Control
Mode. Each register description below also shows the Power-
On Reset (POR) state of each control bit.
Configuration Register
Addr: 1h (0001b)
W only (0xB2FF)
POR State: 0b
D15 D14 D13 D12 D11 D10
D9
DCS DCP nDE OV
D8
Bits 7:0
Must be set to 1b.
1
0
1
OE
I-Channel Offset
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Addr: 2h (0010b)
W only (0x007F)
D15 D14 D13 D12 D11 D10
D9
D8
IMPORTANT: The Configuration Register should not be
written if the DES Enable bit = 1. The DES Enable bit
should first be changed to 0, then the Configuration
Register can be written. Failure to follow this procedure
can cause the internal DES clock generation circuitry to
stop.
(MSB)
Offset Value
(LSB)
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Sign
Bits 15:8 Offset Value. The input offset of the I-Channel
ADC is adjusted linearly and monotonically by
the value in this field. 0000 0000 0b provides
a nominal zero offset, while FFh provides a
nominal 45 mV of offset. Thus, each code step
provides 0.176 mV of offset.
Bit 15
Bit 14
Bit 13
Bit 12
Must be set to 1b
Must be set to 0b
Must be set to 1b
DCS: Duty Cycle Stabilizer. When this bit is set
to 1b , a duty cycle stabilization circuit is
applied to the clock input. When this bit is set
to 0b the stabilization circuit is disabled.
POR State: 1b
POR State: 0000 0000 0b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
POR State: 0b
Bit 11
DCP: DDR Clock Phase. This bit only has an
effect in the DDR mode. When this bit is set to
0b, the DCLK edges are time-aligned with the
data bus edges ("0° Phase"). When this bit is
set to 1b, the DCLK edges are placed in the
middle of the data bit-cells ("90° Phase"),
using the one-half speed DCLK shown in
Figure 4 as the phase reference.
Bit 6:0
Must be set to 1b
POR State: 0b
Bit 10
nDE: DDR Enable. When this bit is set to 0b,
data bus clocking follows the DDR (Dual Data
Rate) mode whereby a data word is output
with each rising and falling edge of DCLK.
When this bit is set to a 1b, data bus clocking
follows the SDR (single data rate) mode
whereby each data word is output with either
the rising or falling edge of DCLK , as
determined by the OutEdge bit.
POR State: 0b
Bit 9
OV: Output Voltage. This bit determines the
LVDS outputs' voltage amplitude and has the
same function as the OutV pin that is used in
the normal control mode. When this bit is set
to 1b, the standard output amplitude of 710
mVP-P is used. When this bit is set to 0b, the
reduced output amplitude of 510 mVP-P is
used.
POR State: 1b
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I-Channel Full-Scale Voltage Adjust
Addr: 3h (0011b) W only (0x807F)
Q-Channel Offset
Addr: Ah (1010b)
D15 D14 D13 D12 D11 D10
W only (0x007F)
D9
D8
D15 D14 D13 D12 D11 D10
D9
D8
(MSB)
Offset Value
(LSB)
(MSB
)
Adjust Value
D7
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
Sign
D7
D6
1
D5
1
D4
D3
1
D2
D1
1
D0
1
Bit 15:8
Offset Value. The input offset of the Q-
Channel ADC is adjusted linearly and
monotonically by the value in this field. 00h
provides a nominal zero offset, while FFh
provides a nominal ±45 mV of offset. Thus,
each code step provides about 0.176 mV of
offset.
(LSB
)
1
1
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mVP-P differential value.
POR State: 0000 0000 b
Bit 7
Sign bit. 0b gives positive offset, 1b gives
negative offset.
0000 0000 0
560mVP-P
700mVP-P
1000 0000 0
Default Value
1111 1111 1
POR State: 0b
Bit 6:0
Must be set to 1b
840mVP-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 1000 0000 0b (no adjustment)
Bits 6:0 Must be set to 1b
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Q-Channel Full-Scale Voltage Adjust
Addr: Bh (1011b) W only (0x807F)
D15 D14 D13 D12 D11 D10
Bit 15
DES Enable. Setting this bit to 1b enables the
Dual Edge Sampling mode. In this mode the
ADCs in this device are used to sample and
convert the same analog input in a time-
interleaved manner, accomplishing a
sampling rate of twice the input clock rate.
When this bit is set to 0b, the device operates
in the normal dual channel mode.
D9
D8
(MSB
)
Adjust Value
D7
D6
1
D5
1
D4
D3
1
D2
D1
1
D0
1
(LSB
)
1
1
POR State: 0b
Bit 14
Automatic Clock Phase (ACP) Control. Setting
this bit to 1b enables the Automatic Clock
Phase Control. In this mode the DES Coarse
and Fine manual controls are disabled. A
phase detection circuit continually adjusts the
I and Q sampling edges to be 180 degrees out
of phase. When this bit is set to 0b, the sample
(input) clock delay between the I and Q
channels is set manually using the DES
Coarse and Fine Adjust registers. (See
Section 2.4.5 for important application
information) Using the ACP Control option
is recommended over the manual DES
settings.
Bit 15:7
Full Scale Voltage Adjust Value. The input full-
scale voltage or gain of the I-Channel ADC is
adjusted linearly and monotonically with a 9 bit
data value. The adjustment range is ±20% of
the nominal 700 mVP-P differential value.
0000 0000 0
1000 0000 0
1111 1111 1
560mVP-P
700mVP-P
840mVP-P
For best performance, it is recommended that
the value in this field be limited to the range of
0110 0000 0b to 1110 0000 0b. i.e., limit the
amount of adjustment to ±15%. The remaining
±5% headroom allows for the ADC's own full
scale variation. A gain adjustment does not
require ADC re-calibration.
POR State: 0b
Bits 13:0 Must be set to 1b
DES Coarse Adjust
Addr: Eh (1110b) W only (0x07FF)
D15 D14 D13 D12 D11 D10
POR State: 1000 0000 0b (no adjustment)
Must be set to 1b
Bits 6:0
DES Enable
D9
1
D8
1
Addr: Dh (1101b)
W only (0x3FFF)
IS
ADS
CAM
1
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
D15 D14 D13 D12 D11 D10
D9
1
D8
1
DEN ACP
1
1
1
1
Bit 15
Input Select. When this bit is set to 0b the "I"
input is operated upon by both ADCs. When
this bit is set to 1b the "Q" input is operated on
by both ADCs.
D7
1
D6
1
D5
1
D4
1
D3
1
D2
1
D1
1
D0
1
POR State: 0b
Bit 14
Adjust Direction Select. When this bit is set to
0b, the programmed delays are applied to the
"I" channel sample clock while the "Q" channel
sample clock remains fixed. When this bit is
set to 1b, the programmed delays are applied
to the "Q" channel sample clock while the "I"
channel sample clock remains fixed.
POR State: 0b
Bits 13:11 Coarse Adjust Magnitude. Each code value in
this field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit) by approximately 20 picoseconds. A
value of 000b in this field causes zero
adjustment.
POR State: 000b
Bits 10:0 Must be set to 1b
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DES Fine Adjust
the reset period is determined by the mode of operation (SDR/
DDR) and the setting of the Output Edge configuration pin or
bit. (Refer to Figure 6, Figure 7 and Figure 8 for the DCLK
reset state conditions). Therefore, depending upon when the
DCLK_RST signal is asserted, there may be a narrow pulse
on the DCLK line during this reset event. When the
DCLK_RST signal is de-asserted in synchronization with the
CLK rising edge, the next CLK falling edge synchronizes the
DCLK output with those of other ADC08D1010s in the sys-
tem. The DCLK output is enabled again after a constant delay
(relative to the input clock frequency) which is equal to the
CLK input to DCLK output delay (tSD). The device always ex-
hibits this delay characteristic in normal operation.
Addr: Fh (1111b)
W only (0x007F)
D15 D14 D13 D12 D11 D10
D9
D8
(MSB)
D7
FAM
D3
D6
1
D5
1
D4
1
D2
1
D1
1
D0
1
(LSB
)
1
Bits 15:7 Fine Adjust Magnitude. Each code value in this
field delays either the "I" channel or the "Q"
channel sample clock (as determined by the
ADS bit of the DES Coarse Adjust Register) by
approximately 0.1 ps. A value of 00h in this
field causes zero adjustment. Note that the
amount of adjustment achieved with each
code will vary with the device conditions as
well as with the Coarse Adjustment value
chosen.
The DCLK-RST pin should NOT be brought high while the
calibration process is running (while CalRun is high). Doing
so could cause a digital glitch in the digital circuitry, resulting
in corruption and invalidation of the calibration.
2.0 Applications Information
2.1 THE REFERENCE VOLTAGE
The voltage reference for the ADC08D1010 is derived from a
1.254V bandgap reference, a buffered version of which is
made available at pin 31, VBG for user convenience and has
an output current capability of ±100 μA. This reference volt-
age should be buffered if more current is required.
POR State: 0000 0000 b
Bit 6:0 Must be set to 1b
1.4.1 Note Regarding Extended Mode Offset Correction
When using the I or Q channel Offset Adjust registers, the
following information should be noted.
The internal bandgap-derived reference voltage has a nomi-
nal value of 650 mV or 870 mV, as determined by the FSR
pin and described in Section 1.1.4.
For offset values of +0000 0000 and -0000 0000, the actual
offset is not the same. By changing only the sign bit in this
case, an offset step in the digital output code of about 1/10th
of an LSB is experienced. This is shown more clearly in the
Figure below.
There is no provision for the use of an external reference volt-
age, but the full-scale input voltage can be adjusted through
a Configuration Register in the Extended Control mode, as
explained in Section 1.2.
Differential input signals up to the chosen full-scale level will
be digitized to 8 bits. Signal excursions beyond the full-scale
range will be clipped at the output. These large signal excur-
sions will also activate the OR output for the time that the
signal is out of range. See Section 2.2.2.
One extra feature of the VBG pin is that it can be used to raise
the common mode voltage level of the LVDS outputs. The
output offset voltage (VOS) is typically 800mV when the VBG
pin is used as an output or left unconnected. To raise the
LVDS offset voltage to a typical value of 1200mV the VBG pin
can be connected directly to the supply rails.
2.2 THE ANALOG INPUT
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The analog input is a differential one to which the signal
source may be a.c. coupled or d.c. coupled. The full-scale
input range is selected with the FSR pin to be 650 mVP-P or
870 mVP-P, or can be adjusted to values between 560 mVP-
P and 840 mVP-P in the Extended Control mode through the
Serial Interface. For best performance, it is recommended
that the full-scale range be kept between 595 mVP-P and 805
mVP-P in the Extended Control mode.
FIGURE 10. Extended Mode Offset Behavior
1.5 MULTIPLE ADC SYNCHRONIZATION
The ADC08D1010 has the capability to precisely reset its
sampling clock input to DCLK output relationship as deter-
mined by the user-supplied DCLK_RST pulse. This allows
multiple ADCs in a system to have their DCLK (and data) out-
puts transition at the same time with respect to the shared
CLK input that they all use for sampling.
Table 5 gives the input to output relationship with the FSR pin
high and the normal (non-extended) mode is used. With the
FSR pin grounded, the millivolt values in Table 5 are reduced
to 75% of the values indicated. In the Enhanced Control
Mode, these values will be determined by the full scale range
and offset settings in the Control Registers.
The DCLK_RST signal must observe some timing require-
ments that are shown in Figure 6, Figure 7 and Figure 8 of the
Timing Diagrams. The DCLK_RST pulse must be of a mini-
mum width and its deassertion edge must observe setup and
hold times with respect to the CLK input rising edge. These
times are specified in the AC Electrical Characteristics Table.
The DCLK_RST signal can be asserted asynchronous to the
input clock. If DCLK_RST is asserted, the DCLK output is held
in a designated state. The state in which DCLK is held during
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TABLE 5. DIFFERENTIAL INPUT TO OUTPUT
RELATIONSHIP (Non-Extended Control Mode, FSR High)
Full-scale distortion performance falls off rapidly as the
input common mode voltage deviates from VCMO. This is
a direct result of using a very low supply voltage to min-
imize power. Keep the input common voltage within 50
VIN+
VIN−
Output Code
0000 0000
0100 0000
VCM − 217.5mV
VCM − 109 mV
VCM + 217.5mV
VCM + 109 mV
mV of VCMO
.
Performance is as good in the d.c. coupled mode as it is
in the a.c. coupled mode, provided the input common
mode voltage at both analog inputs remain within 50 mV
0111 1111 /
1000 0000
VCM
VCM
of VCMO
.
VCM + 109 mV
VCM + 217.5mV
VCM −109 mV
1100 0000
1111 1111
If d.c. coupling is used, it is best to servo the input common
mode voltage, using the VCMO pin, to maintain optimum per-
formance. An example of this type of circuit is shown in Figure
12.
VCM − 217.5mV
The buffered analog inputs simplify the task of driving these
inputs and the RC pole that is generally used at sampling ADC
inputs is not required. If it is desired to use an amplifier circuit
before the ADC, use care in choosing an amplifier with ade-
quate noise and distortion performance and adequate gain at
the frequencies used for the application.
Note that a precise d.c. common mode voltage must be
present at the ADC inputs. This common mode voltage,
VCMO, is provided on-chip when a.c. input coupling is used
and the input signal is a.c. coupled to the ADC.
When the inputs are a.c. coupled, the VCMO output must be
grounded, as shown in Figure 11. This causes the on-chip
VCMO voltage to be connected to the inputs through on-chip
50k-Ohm resistors.
IMPORTANT NOTE: An Analog input channel that is not used
(e.g. in DES Mode) should be left floating when the inputs are
a.c. coupled. Do not connect an unused analog input to
ground.
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FIGURE 12. Example of Servoing the Analog Input with
VCMO
One such circuit should be used in front of the VIN+ input and
another in front of the VIN− input. In that figure, RD1, RD2 and
RD3 are used to divide the VCMO potential so that, after being
gained up by the amplifier, the input common mode voltage
is equal to VCMO from the ADC. RD1 and RD2 are split to allow
the bypass capacitor to isolate the input signal from VCMO
.
RIN, RD2 and RD3 will divide the input signal, if necessary. Ca-
pacitor "C" in Figure 12 should be chosen to keep any com-
ponent of the input signal from affecting VCMO
.
Be sure that the current drawn from the VCMO output does not
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exceed 100 μA.
FIGURE 11. Differential Input Drive
The Input impedance in the d.c. coupled mode (VCMO pin not
grounded) consists of a precision 100Ω resistor between VIN
+ and VIN− and a capacitance from each of these inputs to
ground. In the a.c. coupled mode the input appears the same
except there is also a resistor of 50K between each analog
input pin and the VCMO potential.
When the d.c. coupled mode is used, a common mode volt-
age must be provided at the differential inputs. This common
mode voltage should track the VCMO output pin. Note that the
VCMO output potential will change with temperature. The com-
mon mode output of the driving device should track this
change.
Driving the inputs beyond full scale will result in a saturation
or clipping of the reconstructed output.
IMPORTANT NOTE: An analog input channel that is not used
(e.g. in DES Mode) should be tied to the VCMO voltage when
the inputs are d.c. coupled. Do not connect unused analog
inputs to ground.
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30
2.2.1 Handling Single-Ended Input Signals
lifetime. This is because of the higher power consumption and
die temperatures at high sample rates. Important also for re-
liability is proper thermal management . See Section 2.6.2.
There is no provision for the ADC08D1010 to adequately pro-
cess single-ended input signals. The best way to handle
single-ended signals is to convert them to differential signals
before presenting them to the ADC. The easiest way to ac-
complish single-ended to differential signal conversion is with
an appropriate balun-connected transformer, as shown in
Figure 13.
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FIGURE 14. Differential (LVDS) Input Clock Connection
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The differential input clock line pair should have a character-
istic impedance of 100Ω and (when using a balun), be termi-
nated at the clock source in that (100Ω) characteristic
impedance. The input clock line should be as short and as
direct as possible. The ADC08D1010 clock input is internally
terminated with an untrimmed 100Ω resistor.
Insufficient input clock levels will result in poor dynamic per-
formance. Excessively high input clock levels could cause a
change in the analog input offset voltage. To avoid these
problems, keep the input clock level within the range specified
in the Electrical Characteristics Table.
FIGURE 13. Single-Ended to Differential signal
conversion with a balun-connected transformer
The 100 Ohm external resistor placed across the output ter-
minals of the balun in parallel with the ADC08D1010's on-chip
100 Ohm resistor makes a 50 Ohms differential impedance
at the balun output. Or, 25 Ohms to virtual ground at each of
the balun output terminals.
Looking into the balun, the source sees the impedance of the
first coil in series with the impedance at the output of that coil.
Since the transformer has a 1:1 turns ratio, the impedance
across the first coil is exactly the same as that at the output
of the second coil, namely 25 Ohms to virtual ground. So, the
25 Ohms across the first coil in series with the 25 Ohms at its
output gives 50 Ohms total impedance to match the source.
The low and high times of the input clock signal can affect the
performance of any A/D Converter. The ADC08D1010 fea-
tures a duty cycle clock correction circuit which can maintain
performance over temperature even in DES mode. The ADC
will meet its performance specification if the input clock high
and low times are maintained within the range (20/80% ratio)
as specified in the Electrical Characteristics Table.
2.2.2 Out Of Range (OR) Indication
When the conversion result is clipped the Out of Range output
is activated such that OR+ goes high and OR- goes low. This
output is active as long as accurate data on either or both of
the buses would be outside the range of 00h to FFh.
High speed, high performance ADCs such as the AD-
C08D1010 require a very stable input clock signal with mini-
mum phase noise or jitter. ADC jitter requirements are defined
by the ADC resolution (number of bits), maximum ADC input
frequency and the input signal amplitude relative to the ADC
input full scale range. The maximum jitter (the sum of the jitter
from all sources) allowed to prevent a jitter-induced reduction
in SNR is found to be
2.2.3 Full-Scale Input Range
As with all A/D Converters, the input range is determined by
the value of the ADC's reference voltage. The reference volt-
age of the ADC08D1010 is derived from an internal band-gap
reference. The FSR pin controls the effective reference volt-
age of the ADC08D1010 such that the differential full-scale
input range at the analog inputs is 870 mVP-P with the FSR
pin high, or is 650 mVP-P with FSR pin low. Best SNR is ob-
tained with FSR high, but better distortion and SFDR are
obtained with the FSR pin low.
tJ(MAX) = (VIN(P-P) / VINFSR) x (1/(2(N+1) x π x fIN))
where tJ(MAX) is the rms total of all jitter sources in seconds,
VIN(P-P) is the peak-to-peak analog input signal, VINFSR is the
full-scale range of the ADC, "N" is the ADC resolution in bits
and fIN is the maximum input frequency, in Hertz, to the ADC
analog input.
2.3 THE CLOCK INPUTS
Note that the maximum jitter described above is the arithmetic
sum of the jitter from all sources, including that in the ADC
input clock, that added by the system to the ADC input clock
and input signals and that added by the ADC itself. Since the
effective jitter added by the ADC is beyond user control, the
best the user can do is to keep the sum of the externally added
input clock jitter and the jitter added by the analog circuitry to
the analog signal to a minimum.
The ADC08D1010 has differential LVDS clock inputs, CLK+
and CLK-, which must be driven with an a.c. coupled, differ-
ential clock signal. Although the ADC08D1010 is tested and
its performance is guaranteed with a differential 1.0 GHz
clock, it typically will function well with input clock frequencies
indicated in the Electrical Characteristics Table. The clock in-
puts are internally terminated and biased. The input clock
signal must be capacitively coupled to the clock pins as indi-
cated in Figure 14.
Input clock amplitudes above those specified in the Electrical
Characteristics Table may result in increased input offset volt-
age. This would cause the converter to produce an output
code other than the expected 127/128 when both input pins
are at the same potential.
Operation up to the sample rates indicated in the Electrical
Characteristics Table is typically possible if the maximum am-
bient temperatures indicated are not exceeded. Operating at
higher sample rates than indicated for the given ambient tem-
perature may result in reduced device reliability and product
31
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2.4 CONTROL PINS
gin when it is not desired. As mentioned in section 1.1.1 for
best performance, a self calibration should be performed 20
seconds or more after power up and repeated when the op-
erating temperature changes significantly according to the
particular system performance requirements. ENOB drops
slightly as junction temperature increases and executing a
new self calibration cycle will essentially eliminate the
change.
Six control pins (without the use of the serial interface) provide
a wide range of possibilities in the operation of the AD-
C08D1010 and facilitate its use. These control pins provide
Full-Scale Input Range setting, Self Calibration, Calibration
Delay, Output Edge Synchronization choice, LVDS Output
Level choice and a Power Down feature.
2.4.1 Full-Scale Input Range Setting
2.4.2.3 Calibration Delay
The input full-scale range can be selected to be either 650
mVP-P or 870 mVP-P, as selected with the FSR control input
(pin 14) in the Normal Mode of operation. In the Extended
Control Mode, the input full-scale range may be set to be
anywhere from 560 mVP-P to 840 mVP-P. See Section 2.2 for
more information.
The CalDly input (pin 127) is used to select one of two delay
times after the application of power to the start of calibration,
as described in Section 1.1.1. The calibration delay values
allow the power supply to come up and stabilize before cali-
bration takes place. With no delay or insufficient delay, cali-
bration would begin before the power supply is stabilized at
its operating value and result in non-optimal calibration coef-
ficients. If the PD pin is high upon power-up, the calibration
delay counter will be disabled until the PD pin is brought low.
Therefore, holding the PD pin high during power up will further
delay the start of the power-up calibration cycle. The best
setting of the CalDly pin depends upon the power-on settling
time of the power supply.
2.4.2 Self Calibration
The ADC08D1010 self-calibration must be run to achieve
specified performance. The calibration procedure is run upon
power-up and can be run any time on command. The cali-
bration procedure is exactly the same whether there is an
input clock present upon power up or if the clock begins some
time after application of power. The CalRun output indicator
is high while a calibration is in progress.
Note that the calibration delay selection is not possible in the
Extended Control mode and the short delay time is used.
2.4.2.1 Power-On Calibration
2.4.3 Output Edge Synchronization
Power-on calibration begins after a time delay following the
application of power. This time delay is determined by the
setting of CalDly, as described in the Calibration Delay Sec-
tion, below.
DCLK signals are available to help latch the converter output
data into external circuitry. The output data can be synchro-
nized with either edge of these DCLK signals. That is, the
output data transition can be set to occur with either the rising
edge or the falling edge of the DCLK signal, so that either
edge of that DCLK signal can be used to latch the output data
into the receiving circuit.
The calibration process will be not be performed if the CAL
pin is high at power up. In this case, the calibration cycle will
not begin until the on-command calibration conditions are
met. The ADC08D1010 will function with the CAL pin held
high at power up, but no calibration will be done and perfor-
mance will be impaired. A manual calibration, however, may
be performed after powering up with the CAL pin high. See
On-Command Calibration Section 2.4.2.2.
When OutEdge (pin 4) is high, the output data is synchronized
with (changes with) the rising edge of the DCLK+ (pin 82).
When OutEdge is low, the output data is synchronized with
the falling edge of DCLK+.
The internal power-on calibration circuitry comes up in an un-
known logic state. If the input clock is not running at power up
and the power on calibration circuitry is active, it will hold the
analog circuitry in power down and the power consumption
will typically be less than 200 mW. The power consumption
will be normal after the clock starts.
At the very high speeds of which the ADC08D1010 is capable,
slight differences in the lengths of the DCLK and data lines
can mean the difference between successful and erroneous
data capture. The OutEdge pin is used to capture data on the
DCLK edge that best suits the application circuit and layout.
2.4.4 LVDS Output Level Control
2.4.2.2 On-Command Calibration
The output level can be set to one of two levels with OutV
(pin3). The strength of the output drivers is greater with OutV
high. With OutV low there is less power consumption in the
output drivers, but the lower output level means decreased
noise immunity.
An on-command calibration may be run at any time in NOR-
MAL (non-DES) mode only. Do not run a calibration while
operating the ADC in Auto DES Mode.
If the ADC is operating in Auto DES mode and a calibration
cycle is required then the controlling application should bring
the ADC into normal (non DES) mode before an On Com-
mand calibration is initiated. Once calibration has completed,
the ADC can be put back into Auto DES mode.
For short LVDS lines and low noise systems, satisfactory per-
formance may be realized with the OutV input low. If the LVDS
lines are long and/or the system in which the ADC08D1010
is used is noisy, it may be necessary to tie the OutV pin high.
To initiate an on-command calibration, bring the CAL pin high
for a minimum of 80 input clock cycles after it has been low
for a minimum of 80 input clock cycles. Holding the CAL pin
high upon power up will prevent execution of power-on cali-
bration until the CAL pin is low for a minimum of 80 input clock
cycles, then brought high for a minimum of another 80 input
clock cycles. The calibration cycle will begin 80 input clock
cycles after the CAL pin is thus brought high. The CalRun
signal should be monitored to determine when the calibration
cycle has completed.
2.4.5 Dual Edge Sampling
IMPORTANT NOTE: When using the ADC in Extended Con-
trol Mode, the Configuration Register must only be written
when the DES Enable bit = 0. Writing to the Configuration
Register when the DES Enable bit = 1 can cause the internal
DES clock generation circuitry to stop.
The Dual Edge Sampling (DES) feature causes one of the two
input pairs to be routed to both ADCs. The other input pair is
deactivated. One of the ADCs samples the input signal on one
input clock edge (duty cycle corrected), the other samples the
input signal on the other input clock edge (duty cycle correct-
The minimum 80 input clock cycle sequences are required to
ensure that random noise does not cause a calibration to be-
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32
ed). The result is a 1:4 demultiplexed output with a sample
rate that is twice the input clock frequency.
results available on just one of the the two LVDS buses and
a 200 MHz input clock, decimating the 200 MSPS data by two.
To use this feature in the non-enhanced control mode, allow
pin 127 to float and the signal at the "I" channel input will be
sampled by both converters. The Calibration Delay will then
only be a short delay.
There is one LVDS output clock pair (DCLK+/-) available for
use to latch the LVDS outputs on all buses. Whether the data
is sent at the rising or falling edge of DCLK is determined by
the sense of the OutEdge pin, as described in Section 2.4.3.
In the enhanced control mode, either input may be used for
dual edge sampling. See Section 1.1.5.1.
DDR (Double Data Rate) clocking can also be used. In this
mode a word of data is presented with each edge of DCLK,
reducing the DCLK frequency to 1/4 the input clock frequency.
See the Timing Diagram section for details.
IMPORTANT NOTES :
1) For the Extended Control Mode - When using the Auto-
matic Clock Phase Control feature in dual edge sampling
mode, it is important that the automatic phase control is dis-
abled (set bit 14 of DES Enable register Dh to 0) before the
ADC is powered up. Not doing so may cause the device not
to wake-up from the power down state.
The OutV pin is used to set the LVDS differential output levels.
See Section 2.4.4.
The output format is Offset Binary. Accordingly, a full-scale
input level with VIN+ positive with respect to VIN− will produce
an output code of all ones, a full-scale input level with VIN−
positive with respect to VIN+ will produce an output code of all
zeros and when VIN+ and VIN− are equal, the output code will
vary between codes 127 and 128.
2) For the Non-Extended Control Mode - When the AD-
C08D1010 is powered up and DES mode is required, ensure
that pin 127 (CalDly/DES/SCS) is initially pulled low during or
after the power up sequence. The pin can then be allowed to
float or be tied to VA / 2 to enter the DES mode. This will en-
sure that the part enters the DES mode correctly.
2.6 POWER CONSIDERATIONS
A/D converters draw sufficient transient current to corrupt
their own power supplies if not adequately bypassed. A 33 µF
capacitor should be placed within an inch (2.5 cm) of the A/D
converter power pins. A 0.1 µF capacitor should be placed as
close as possible to each VA pin, preferably within one-half
centimeter. Leadless chip capacitors are preferred because
they have low lead inductance.
3) The automatic phase control should also be disabled if the
input clock is interrupted or stopped for any reason. This is
also the case if a large abrupt change in the clock frequency
occurs.
4) If a calibration of the ADC is required in Auto DES mode,
the device must be returned to the Normal Mode of operation
before performing a calibration cycle. Once the Calibration
has been completed, the device can be returned to the Auto
DES mode and operation can resume.
The VA and VDR supply pins should be isolated from each
other to prevent any digital noise from being coupled into the
analog portions of the ADC. A ferrite choke, such as the JW
Miller FB20009-3B, is recommended between these supply
lines when a common source is used for them.
2.4.6 Power Down Feature
As is the case with all high speed converters, the AD-
C08D1010 should be assumed to have little power supply
noise rejection. Any power supply used for digital circuitry in
a system where a lot of digital power is being consumed
should not be used to supply power to the ADC08D1010. The
ADC supplies should be the same supply used for other ana-
log circuitry, if not a dedicated supply.
The Power Down pins (PD and PDQ) allow the ADC08D1010
to be entirely powered down (PD) or the "Q" channel to be
powered down and the "I" channel to remain active. See Sec-
tion 1.1.7 for details on the power down feature.
The digital data (+/-) output pins are put into a high impedance
state when the PD pin for the respective channel is high. Upon
return to normal operation, the pipeline will contain meaning-
less information and must be flushed.
2.6.1 Supply Voltage
If the PD input is brought high while a calibration is running,
the device will not go into power down until the calibration
sequence is complete. However, if power is applied and PD
is already high, the device will not begin the calibration se-
quence until the PD input goes low. If a manual calibration is
requested while the device is powered down, the calibration
will not begin at all. That is, the manual calibration input is
completely ignored in the power down state.
The ADC08D1010 is specified to operate with a supply volt-
age of 1.9V ±0.1V. It is very important to note that, while this
device will function with slightly higher supply voltages, these
higher supply voltages may reduce product lifetime.
No pin should ever have a voltage on it that is in excess of the
supply voltage or below ground by more than 150 mV, not
even on a transient basis. This can be a problem upon appli-
cation of power and power shut-down. Be sure that the sup-
plies to circuits driving any of the input pins, analog or digital,
do not come up any faster than does the voltage at the AD-
C08D1010 power pins.
2.5 THE DIGITAL OUTPUTS
The ADC08D1010 demultiplexes the output data of each of
the two ADCs on the die onto two LVDS output buses (total
of four buses, two for each ADC). For each of the two con-
verters, the results of successive conversions started on the
odd falling edges of the CLK+ pin are available on one of the
two LVDS buses, while the results of conversions started on
the even falling edges of the CLK+ pin are available on the
other LVDS bus. This means that, the word rate at each LVDS
bus is 1/2 the ADC08D1010 input clock rate and the two bus-
es must be multiplexed to obtain the entire 1 GSPS conver-
sion result.
The Absolute Maximum Ratings should be strictly observed,
even during power up and power down. A power supply that
produces a voltage spike at turn-on and/or turn-off of power
can destroy the ADC08D1010. The circuit of Figure 15 will
provide supply overshoot protection.
Many linear regulators will produce output spiking at power-
on unless there is a minimum load provided. Active devices
draw very little current until their supply voltages reach a few
hundred millivolts. The result can be a turn-on spike that can
destroy the ADC08D1010, unless a minimum load is provided
for the supply. The 100Ω resistor at the regulator output pro-
vides a minimum output current during power-up to ensure
there is no turn-on spiking.
Since the minimum recommended input clock rate for this
device is 200 MSPS (normal non DES mode), the effective
rate can be reduced to as low as 100 MSPS by using the
33
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In the circuit of Figure 15, an LM317 linear regulator is satis-
factory if its input supply voltage is 4V to 5V . If a 3.3V supply
is used, an LM1086 linear regulator is recommended.
20146754
20146721
FIGURE 15. Non-Spiking Power Supply
FIGURE 16. Recommended Package Land Pattern
The output drivers should have a supply voltage, VDR, that is
within the range specified in the Operating Ratings table. This
voltage should not exceed the VA supply voltage.
Since a large aperture opening may result in poor release, the
aperture opening should be subdivided into an array of small-
er openings, similar to the land pattern of Figure 16.
If the power is applied to the device without an input clock
signal present, the current drawn by the device might be be-
low 200 mA. This is because the ADC08D1010 gets reset
through clocked logic and its initial state is random. If the reset
logic comes up in the "on" state, it will cause most of the ana-
log circuitry to be powered down, resulting in less than 100
mA of current draw. This current is greater than the power
down current because not all of the ADC is powered down.
The device current will be normal after the input clock is es-
tablished.
To minimize junction temperature, it is recommended that a
simple heat sink be built into the PCB. This is done by includ-
ing a copper area of about 2 square inches (6.5 square cm)
on the opposite side of the PCB. This copper area may be
plated or solder coated to prevent corrosion, but should not
have a conformal coating, which could provide some thermal
insulation. Thermal vias should be used to connect these top
and bottom copper areas. These thermal vias act as "heat
pipes" to carry the thermal energy from the device side of the
board to the opposite side of the board where it can be more
effectively dissipated. The use of 9 to 16 thermal vias is rec-
ommended.
2.6.2 Thermal Management
The ADC08D1010 is capable of impressive speeds and per-
formance at very low power levels for its speed. However, the
power consumption is still high enough to require attention to
thermal management. For reliability reasons, the die temper-
ature should be kept to a maximum of 130°C. That is, TA
(ambient temperature) plus ADC power consumption times
θJA (junction to ambient thermal resistance) should not ex-
ceed 130°C. This is not a problem if the ambient temperature
is kept to a maximum of +85°C as specified in the Operating
Ratings section.
The thermal vias should be placed on a 1.2 mm grid spacing
and have a diameter of 0.30 to 0.33 mm. These vias should
be barrel plated to avoid solder wicking into the vias during
the soldering process as this wicking could cause voids in the
solder between the package exposed pad and the thermal
land on the PCB. Such voids could increase the thermal re-
sistance between the device and the thermal land on the
board, which would cause the device to run hotter.
If it is desired to monitor die temperature, a temperature sen-
sor may be mounted on the heat sink area of the board near
the thermal vias. .Allow for a thermal gradient between the
temperature sensor and the ADC08D1010 die of θJ-PAD times
typical power consumption = 2.8 x 1.6 = 4.5°C. Allowing for a
5.5°C (including an extra 1°C) temperature drop from the die
to the temperature sensor, then, would mean that maintaining
a maximum pad temperature reading of 124.5°C will ensure
that the die temperature does not exceed 130°C, assuming
that the exposed pad of the ADC08D1010 is properly sol-
dered down and the thermal vias are adequate. (The inaccu-
racy of the temperature sensor is in addition to the above
calculation).
Please note that the following are general recommendations
for mounting exposed pad devices onto a PCB. This should
be considered the starting point in PCB and assembly pro-
cess development. It is recommended that the process be
developed based upon past experience in package mounting.
The package of the ADC08D1010 has an exposed pad on its
back that provides the primary heat removal path as well as
excellent electrical grounding to the printed circuit board. The
land pattern design for lead attachment to the PCB should be
the same as for a conventional LQFP, but the exposed pad
must be attached to the board to remove the maximum
amount of heat from the package, as well as to ensure best
product parametric performance.
To maximize the removal of heat from the package, a thermal
land pattern must be incorporated on the PC board within the
footprint of the package. The exposed pad of the device must
be soldered down to ensure adequate heat conduction out of
the package. The land pattern for this exposed pad should be
at least as large as the 5 x 5 mm of the exposed pad of the
package and be located such that the exposed pad of the
device is entirely over that thermal land pattern. This thermal
land pattern should be electrically connected to ground. A
clearance of at least 0.5 mm should separate this land pattern
from the mounting pads for the package pins.
2.7 LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essen-
tial to ensure accurate conversion. A single ground plane
should be used, instead of splitting the ground plane into ana-
log and digital areas.
Since digital switching transients are composed largely of
high frequency components, the skin effect tells us that total
ground plane copper weight will have little effect upon the
logic-generated noise. Total surface area is more important
than is total ground plane volume. Coupling between the typ-
ically noisy digital circuitry and the sensitive analog circuitry
can lead to poor performance that may seem impossible to
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34
isolate and remedy. The solution is to keep the analog cir-
cuitry well separated from the digital circuitry.
TABLE 6. Non-Extended Control Mode Operation (Pin 14
High or Low)
High power digital components should not be located on or
near any linear component or power supply trace or plane that
services analog or mixed signal components as the resulting
common return current path could cause fluctuation in the
analog input “ground” return of the ADC, causing excessive
noise in the conversion result.
Pin
Low
High
0.70VP-P
Output
Floating
0.50VP-P
Output
3
n/a
OutEdge =
Neg
OutEdge =
Pos
4
DDR
DES
Generally, we assume that analog and digital lines should
cross each other at 90° to avoid getting digital noise into the
analog path. In high frequency systems, however, avoid
crossing analog and digital lines altogether. The input clock
lines should be isolated from ALL other lines, analog AND
digital. The generally accepted 90° crossing should be avoid-
ed as even a little coupling can cause problems at high
frequencies. Best performance at high frequencies is ob-
tained with a straight signal path.
127
14
CalDly Low CalDly High
650 mVP-P 870 mVP-P
input range input range
Extended
Control Mode
Pin 3 can be either high or low in the non-extended control
mode. Pin 14 must not be left floating to select this mode. See
Section 1.2 for more information.
Pin 4 can be high or low or can be left floating in the non-
extended control mode. In the non-extended control mode,
pin 4 high or low defines the edge at which the output data
transitions. See Section 2.4.3 for more information. If this pin
is floating, the output clock (DCLK) is a DDR (Double Data
Rate) clock (see Section 1.1.5.3) and the output edge syn-
chronization is irrelevant since data is clocked out on both
DCLK edges.
The analog input should be isolated from noisy signal traces
to avoid coupling of spurious signals into the input. This is
especially important with the low level drive required of the
ADC08D1010. Any external component (e.g., a filter capaci-
tor) connected between the converter's input and ground
should be connected to a very clean point in the analog
ground plane. All analog circuitry (input amplifiers, filters, etc.)
should be separated from any digital components.
Pin 127, if it is high or low in the non-extended control mode,
sets the calibration delay. If pin 127 is floating, the calibration
delay is the same as it would be with this pin low and the
converter performs dual edge sampling (DES).
2.8 DYNAMIC PERFORMANCE
The ADC08D1010 is a.c. tested and its dynamic performance
is guaranteed. To meet the published specifications and avoid
jitter-induced noise, the clock source driving the CLK input
must exhibit low rms jitter. The allowable jitter is a function of
the input frequency and the input signal level, as described in
Section 2.3.
TABLE 7. Extended Control Mode Operation (Pin 14
Floating)
Pin
3
Function
SCLK (Serial Clock)
It is good practice to keep the ADC input clock line as short
as possible, to keep it well away from any other signals and
to treat it as a transmission line. Other signals can introduce
jitter into the input clock signal. The clock signal can also in-
troduce noise into the analog path if not isolated from that
path.
4
SDATA (Serial Data)
127
SCS (Serial Interface Chip Select)
2.10 COMMON APPLICATION PITFALLS
Failure to write all register locations when using extend-
ed control mode. When using the serial interface, all 8 user
registers must be written at least once with the default or de-
sired values before calibration and subsequent use of the
ADC. In addition, the first write to the DES Enable register
(Dh) must load the default value (0x3FFFh). Once all registers
have been written once, other desired settings, including en-
abling DES can be loaded.
Best dynamic performance is obtained when the exposed pad
at the back of the package has a good connection to ground.
This is because this path from the die to ground is a lower
impedance than offered by the package pins.
2.9 USING THE SERIAL INTERFACE
The ADC08D1010 may be operated in the non-extended con-
trol (non-Serial Interface) mode or in the extended control
mode. Table 6 and Table 7 describe the functions of pins 3,
4, 14 and 127 in the non-extended control mode and the ex-
tended control mode, respectively.
Driving the inputs (analog or digital) beyond the power
supply rails. For device reliability, no input should go more
than 150 mV below the ground pins or 150 mV above the
supply pins. Exceeding these limits on even a transient basis
may not only cause faulty or erratic operation, but may impair
device reliability. It is not uncommon for high speed digital
circuits to exhibit undershoot that goes more than a volt below
ground. Controlling the impedance of high speed lines and
terminating these lines in their characteristic impedance
should control overshoot.
2.9.1 Non-Extended Control Mode Operation
Non-extended control mode operation means that the Serial
Interface is not active and all controllable functions are con-
trolled with various pin settings. That is, the full-scale range,
single-ended or differential input and input coupling (a.c. or
d.c.) are all controlled with pin settings. The non-extended
control mode is used by setting pin 14 high or low, as opposed
to letting it float. Table 6 indicates the pin functions of the AD-
C08D1010 in the non-extended control mode.
Care should be taken not to overdrive the inputs of the AD-
C08D1010. Such practice may lead to conversion inaccura-
cies and even to device damage.
Incorrect analog input common mode voltage in the d.c.
coupled mode. As discussed in section 1.1.4 and 2.2, the
Input common mode voltage must remain within 50 mV of the
VCMO output , which has a variability with temperature that
must also be tracked. Distortion performance will be degrad-
ed if the input common mode voltage is more than 50 mV from
VCMO
.
35
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Using an inadequate amplifier to drive the analog input.
Use care when choosing a high frequency amplifier to drive
the ADC08D1010 as many high speed amplifiers will have
higher distortion than will the ADC08D1010, resulting in over-
all system performance degradation.
Inadequate input clock levels. As described in Section 2.3,
insufficient input clock levels can result in poor performance.
Excessive input clock levels could result in the introduction of
an input offset.
Using a clock source with excessive jitter, using an ex-
cessively long input clock signal trace, or having other
signals coupled to the input clock signal trace. This will
cause the sampling interval to vary, causing excessive output
noise and a reduction in SNR performance.
Driving the VBG pin to change the reference voltage. As
mentioned in Section 2.1, the reference voltage is intended to
be fixed to provide one of two different full-scale values (650
mVP-P and 870 mVP-P). Over driving this pin will not change
the full scale value, but can be used to change the LVDS
common mode voltage from 0.8V to 1.2V by tying the VBG pin
to VA.
Failure to provide adequate heat removal. As described in
Section 2.6.2, it is important to provide adequate heat removal
to ensure device reliability. This can either be done with ad-
equate air flow or the use of a simple heat sink built into the
board. The backside pad should be grounded for best perfor-
mance.
Driving the clock input with an excessively high level
signal. The ADC input clock level should not exceed the level
described in the Operating Ratings Table or the input offset
could change.
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Physical Dimensions inches (millimeters) unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
REFERENCE JEDEC REGISTRATION MS-026, VARIATION BFB.
128-Lead Exposed Pad LQFP
Order Number ADC08D1010DIYB
NS Package Number VNX128A
37
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