ADC0854CCN [NSC]
Multiplexed Comparator with 8-Bit Reference Divider; 多重比较与8位参考分频器
| 型号： | ADC0854CCN |
| 厂家： | 
National Semiconductor |
| 描述： | Multiplexed Comparator with 8-Bit Reference Divider |
| 文件： | 总20页 (文件大小：327K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1995
ADC0852/ADC0854
Multiplexed Comparator with 8-Bit Reference Divider
General Description
The ADC0852 and ADC0854 are CMOS devices that com-
bine a versatile analog input multiplexer, voltage compara-
tor, and an 8-bit DAC which provides the comparator’s
once each clock cycle up to a maximum clock rate of
400 kHz.
threshold voltage (V ). The comparator provides a ‘‘1-bit’’
TH
Features
Y
output as a result of a comparison between the analog input
and the DAC’s output. This allows for easy implementation
of set-point, on-off or ‘‘bang-bang’’ control systems with
several advantages over previous devices.
2 or 4 channel multiplexer
Y
Differential or Single-ended input, software controlled
Y
Serial digital data interface
Y
256 programmable reference voltage levels
The ADC0854 has a 4 input multiplexer that can be software
configured for single ended, pseudo-differential, and full-dif-
ferential modes of operation. In addition the DAC’s refer-
ence input is brought out to allow for reduction of the span.
Y
Continuous comparison after programming
Y
Fixed, ratiometric, or reduced span reference capability
(ADC 0854)
The ADC0852 has a two input multiplexer that can be con-
figured as 2 single-ended or 1 differential input pair. The
Key Specifications
Y
g
g
1 LSB of Reference (0.2%)
Accuracy,
(/2 LSB or
DAC reference input is internally tied to V
.
CC
Y
Y
Single 5V power supply
Low Power, 15 mW
The multiplexer and 8-bit DAC are programmed via a serial
data input word. Once programmed the output is updated
TL/H/5521–1
FIGURE 1. ADC0854 Simplified Block Diagram (ADC0852 has 2 input channels,
a
COM tied to GND, V
tied to V , V omitted, and one GND connection)
CC
REF
2 Channel and 4 Channel Pin Out
ADC0852 2-CHANNEL MUX
Dual-In-Line Package
ADC0854 4-CHANNEL MUX
Dual-In-Line Package
TL/H/5521–10
Top View
AGND and COM internally connected to GND
V
REF
internally connected to V
CC
TL/H/5521–11
Top View
Order Number ADC0852
See NS Package Number N08E
Order Number ADC0854
See NS Package Number N14A
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/5521
RRD-B30M75/Printed in U. S. A.
Absolute Maximum Ratings (Notes 1 and 2)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
260 C
§
2000V
ESD Susceptibility (Note 14)
Current into Va (Note 3)
15 mA
6.5V
Operating Conditions
Supply Voltage, V
CC
Supply Voltage, V (Note 3)
CC
4.5V to 6.3V
DC
Voltage
DC
b
a
0.3V
Logic and Analog Inputs
0.3V to V
CC
s
s
T
Temperature Range
T
MIN
T
A
MAX
g
Input Current per Pin
Input Current per Package
Storage Temperature
Package Dissipation
5 mA
s
s
70 C
ADC0854CCN, ADC0852CCN
0 C
§
T
A
§
g
20 mA
b
a
65 C to 150 C
§
§
e
at T
25 C (Board Mount)
§
0.8W
A
Va
e
250 kHz unless otherwise specified. Boldface limits apply from T
5V (no Va on ADC0852),
to T ; all other limits T
A
e
Electrical Characteristics The following specifications apply for V
CC
s
e
a
e
V
V
0.1V, f
CLK
REF
T
CC
25 C.
§
MIN
MAX
e
J
ADC0852CCN
ADC0854CCN
Units
Parameter
Conditions
Tested
Limit
Design
Limit
Typ
(Note 4)
(Note 5)
(Note 6)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
Total Unadjusted
Error (Note 7)
V
Forced to
REF
5.000 V
DC
g
g
1
ADC0852/4/CCN
1
LSB
mV
kX
kX
V
Comparator Offset
ADC0852/4/CCN
2.5
3.5
3.5
20
1.3
5.9
Minimum Total Ladder
Resistance
ADC0854
(Note 15)
1.3
5.4
Maximum Total Ladder
Resistance
ADC0854
(Note 15)
Minimum Common-Mode
Input (Note 8)
All MUX Inputs
and COM Input
GND–0.05
GND–0.05
Maximum Common-Mode
Input (Note 8)
All MUX Inputs
and COM Input
a
a
0.05
V
CC
0.05
V
V
CC
g
g
g
g
(4
DC Common-Mode Error
Power Supply Sensitivity
(/16
(/16
(/4
LSB
LSB
e
g
5V 5%
g
g
(4
V
CC
(/4
a
V , Internal
Z
diode
15 mA into V
MIN
6.3
8.5
V
V
breakdown
at Va (Note 3)
MAX
e
e
b
a
I , Off Channel Leakage
OFF
Current (Note 9)
On Channel
Off Channel
5V,
0V
1
1
mA
nA
b
200
200
e
e
On Channel
Off Channel
0V,
5V
mA
nA
a
2
Electrical Characteristics (Continued)
Va
5V (no Va on ADC0852), f
250 kHz unless otherwise specified.
e
CLK
e
e
The following specifications apply for V
Boldface limits apply from T
CC
e
e
to T
; all other limits T
MAX
T
J
25 C.
§
MIN
A
ADC0852CCN
ADC0854CCN
Units
Parameter
Conditions
Tested
Limit
Design
Limit
Typ
(Note 4)
(Note 5)
(Note 6)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
e
e
a
b
I
, On Channel Leakage
ON
On Channel
Off Channel
5V,
0V
1
1
mA
a
b
Current (Note 9)
200
200
nA
e
e
On Channel
Off Channel
0V,
5V
mA
nA
DIGITAL AND DC CHARACTERISTICS
e
e
V
, Logical ‘‘1’’ Input
V
V
V
V
V
5.25V
2.0
0.8
1
2.0
0.8
1
V
V
IN(1)
CC
CC
IN
Voltage
V
, Logical ‘‘0’’ Input
4.75V
IN(0)
Voltage
e
I
, Logical ‘‘1’’ Input
IN(1)
V
0.005
mA
mA
CC
Current
e
b
b
b
1
I
, Logical ‘‘0’’ Input
0V
0.005
1
IN(0)
Current
IN
e
4.75V
e b
e b
V
, Logical ‘‘1’’ Output
OUT(1)
Voltage
CC
OUT
OUT
I
I
360 mA
2.4
4.5
2.4
4.5
V
V
10 mA
e
e
V
, Logical ‘‘0’’ Output
I
1.6 mA,
4.75V
OUT(0)
Voltage
OUT
V
0.4
0.4
V
CC
e
I
, TRI-STATE Output
É
CS
Logical ‘‘1’’
OUT
Current (DO)
e
e
b
b
b
3
V
V
0.4V
5V
0.1
3
mA
mA
OUT
OUT
0.1
3
3
b
b
b
I
I
I
V
Short to GND
14
7.5
6.5
mA
mA
SOURCE
SINK
OUT
OUT
V
Short to V
CC
16
9.0
8.0
Supply Current
Includes DAC
CC
ADC0852
Ladder Current
2.7
0.9
6.5
2.5
6.5
2.5
mA
mA
I
Supply Current
Does not Include DAC
Ladder Current
CC
ADC0854 (Note 3)
3
e
e
e
20 ns, T 25 C
A
AC Characteristics t
t
f
§
r
Tested
Limit
Design
Limit
Typ
Symbol
Parameter
Conditions
Units
(Note 4)
(Note 5)
(Note 6)
f
Clock Frequency
(Note 12)
MIN
10
kHz
kHz
CLK
D1
r
MAX
400
e
t
t
Rising Edge of Clock
to ‘‘DO’’ Enabled
C
L
100 pF
650
1000
ns
a
Comparator Response
Time (Note 13)
Not Including
2
1 ms
1/f
CLK
Addressing Time
Clock Duty Cycle
(Note 10)
MIN
40
60
%
MAX
%
t
CS Falling Edge or
Data Input Valid to
CLK Rising Edge
MAX
250
ns
SET-UP
HOLD
t
t
Data Input Valid after
CLK Rising Edge
MIN
90
ns
ns
e
, t
pd1 pd0
CLK Falling Edge to
Output Data Valid
(Note 11)
MAX
C
100 pF
650
125
1000
L
e
e
e
10k
t
, t
1H 0H
Rising Edge of CS to
Data Output Hi-Z
MAX
C
C
10 pF, R
250
500
ns
ns
L
L
e
100 pF, R
2k
500
L
L
(see TRI-STATE Test Circuits)
C
C
Capacitance of Logic
Input
5
5
pF
pF
IN
Capacitance of Logic
Outputs
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when
operating the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to ground.
a
a
Note 3: Internal zener diodes (approx. 7V) are connected from V to GND and V to GND. The zener at V can operate as a shunt regulator and is connected
CC
to V
CC
device is powered from V . Functionality is therefore guaranteed for V operation even though the resultant voltage at V may exceed the specified Absolute
via a conventional diode. Since the zener voltage equals the A/D’s breakdown voltage, the diode ensures that V will be below breakdown when the
CC
a
a
CC
a
Max of 6.5V. It is recommended that a resistor be used to limit the max current into V
.
Note 4: Typicals are at 25 C and represent most likely parametric norm.
§
Note 5: Tested and guaranteed to National AOQL (Average Outgoing Quality Level).
Note 6: Guaranteed, but not 100% production tested. These limits are not used to calculate outgoing quality levels.
Note 7: Total unadjusted error includes comparator offset, DAC linearity, and multiplexer error. It is expressed in LSBs of the threshold DAC’s input code.
t
b
a
) the output will be 0. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward conduct for analog input
Note 8: For V
IN
(
)
V
IN
(
voltages one diode drop below ground or one diode drop greater than the V supply. Be careful, during testing at low V levels (4.5V), as high level analog inputs
CC CC
(5V) can cause this input diode to conductÐespecially at elevated temperatures, and cause errors for analog inputs near full-scale. The spec allows 50 mV forward
bias of either diode. This means that as long as the analog V or V does not exceed the supply voltage by more than 50 mV, the output code will be correct. To
IN
REF
achieve an absolute 0 V to 5 V input voltage range will therefore require a minimum supply voltage of 4.950 V over temperature variations, initial tolerance
DC DC DC
and loading.
Note 9: Leakage current is measured with the clock not switching.
Note 10: A 40% to 60% clock duty cycle range ensures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of
s
s
s
s
%
CLK HIGH
these limits then 1.6 mS
CLK Low
60 mS and 1.6 mS
.
Note 11: With CS low and programming complete, D0 is updated on each falling CLK edge. However, each new output is based on the comparison completed 0.5
clock cycles prior (see Figure 5).
Note 12: Error specs are not guaranteed at 400 kHz (see graph: Comparator Error vs. f
Note 13: See text, section 1.2.
).
CLK
Note 14: Human body model, 100 pF discharged through a 1.5 kX resistor.
Note 15: Because the reference ladder of the ADC0852 is internally connected to V , ladder resistance cannot be directly tested for the ADC0852. Ladder
CC
current is included in the ADC0852’s supply current specification.
4
Typical Performance Characteristics
Internal DAC Linearity
Error vs V Voltage
Internal DAC Linearity
Error vs Temperature
Comparator Error vs f
CLK
REF
4
TL/H/5521–2
*For ADC0852 add I
REF
5
Timing Diagrams
Data Input Timing
Data Output Timing
TL/H/5521–4
TL/H/5521–3
TRI-STATE Test Circuits and Waveforms
TL/H/5521–5
Leakage Test Circuit
TL/H/5521–6
6
7
8
Functional Description
1. 1 The Sampled-data Comparator
In the first cycle (Figure 4a), one input switch and the invert-
er’s feedback switch are closed. In this interval, the input
capacitor (C) is charged to the connected input (V1) less the
The ADC0852 and ADC0854 utilize a sampled-data com-
parator structure to compare the analog difference between
inverter’s bias voltage (V , approx. 1.2 volts). In the second
B
a
b
a selected ‘‘ ’’ and ‘‘ ’’ input to an 8-bit programmable
threshold.
cycle (Figure 4b) these two switches are opened and the
other (V2) input’s switch is closed. The input capacitor now
subtracts its stored voltage from the second input and the
difference is amplified by the inverter’s open loop gain. The
C
This comparator consists of a CMOS inverter with a capaci-
tively coupled input (Figure 4). Analog switches connect the
two comparator inputs to the input capacitor and also con-
nect the inverter’s input and output. This device in effect
now has one differential input pair. A comparison requires
two cycles, one for zeroing the comparator and another for
making the comparison.
b
b
V2)
inverter input (V ’) becomes V
(V1
and
B
B
a
the output will go high or low depending on the sign of V ’-
C
C
S
B
V .
B
FIGURE 4. Sampled-Data Comparator
e
V
V
#
#
#
#
0
B
e
V on C
V –V
1 B
e
e
C
Stray Input Node Cap.
S
V
B
Inverter Input Bias Voltage
TL/H/5521–8
FIGURE 4a. Zeroing Phase
C
b
e
e
b
(V V )
2
V
V
#
B
B
1
Ê
a
C
C
S
b
A
b
CV CV
[
]
V
V
#
#
0
2
1
a
C
C
S
b
is dependent on V
V
1
0
2
TL/H/5521–9
FIGURE 4b. Compare Phase
b
A
e
b
a
b
]
V )
3
[
V
0
C
(V
V )
1
C
2
(V
1
2
4
a
a
C
1
C
2
C
S
b
A
e
a
D Q C
[
]
D Q C
1
2
a
a
C
C
1
C
2
S
* Comparator Reads V from Internal DAC Differentially
TH
TL/H/5521–14
FIGURE 4c. Multiple Differential Inputs
9
Functional Description (Continued)
In actual practice, the devices used in the ADC0852/4 are a
simple but important expansion of the basic comparator de-
scribed above. As shown in Figure 4c, multiple differential
comparisons can be made. In this circuit, the feedback
switch and one input switch on each capacitor (A switches)
are closed in the first cycle. Then the other input on each
capacitor is connected while all of the first switches are
opened. The change in voltage at the inverter’s input, as a
result of the change in charge on each input capacitor (C1,
C2), will now depend on both input signal differences.
vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential operation.
The analog signal conditioning required in transducer-input
and other types of data acquisition systems is significantly
simplified with this type of input flexibility. One device pack-
age can now handle ground referenced inputs as well as
signals with some arbitrary reference voltage.
On the ADC0854, the ‘‘common’’ pin (pin 6) is used as the
b
‘‘ ’’ input for all channels in single-ended mode. Since this
input need not be at analog ground, it can be used as the
common line for pseudo-differential operation. It may be tied
to a reference potential that is common to all inputs and
within the input range of the comparator. This feature is
especially useful in single-supply applications where the an-
alog circuitry is biased to a potential other than ground.
1.2 Input Sampling and Response Time
The input phases of the comparator relate to the device
clock (CLK) as shown in Figure 5. Because the comparator
is a sampling device, its response characteristics are some-
a
what different from those of linear comparators. The V
input is sampled first (CLK high) followed by V
IN
(
)
IN
A particular input configuration is assigned during the MUX
addressing sequence which occurs prior to the start of a
comparison. The MUX address selects which of the analog
channels is to be enabled, what the input mode will be, and
the input channel polarity. One limitation is that differential
inputs are restricted to adjacent channel pairs. For example,
channel 0 and 1 may be selected as a differential pair but
they cannot act differentially with any other channel.
b
( ) (CLK
low). The output responds to those inputs, one half cycle
later, on CLK’s falling edge.
The comparator’s response time to an input step is depen-
dent on the step’s phase relation to the CLK signal. If an
input step occurs too late to influence the most imminent
comparator decision, one more CLK cycle will pass before
the output is correct. In effect, the response time for the
The channel and polarity selection is done serially via the DI
input. A complete listing of the input configurations and cor-
responding MUX addresses for the ADC0852 and ADC0854
is shown in tables I and II. Figure 6 illustrates the analog
connections for the various input options.
a
a
V
(
) input has a minimum of 1 CLK cycle
1 mS and a
b
) input’s delay
IN
maximum of 2 CLK cycles
will range from 1/2 CLK cycle
1 mS since it is sampled after V
a
1 mS. The V
IN
(
a
a
1 mS to 1.5 CLK cycles
a
(
IN
).
The sampled inputs also affect the device’s response to
pulsed signals. As shown in the shaded areas in Figure 5,
pulses that rise and/or fall near the latter part of a CLK half-
cycle may be ignored.
The analog input voltage for each channel can range from
(typically 5V)
50 mV below ground to 50 mV above V
without degrading accuracy.
CC
1.3 Input Multiplexer
A unique input multiplexing scheme has been utilized to pro-
TL/H/5521–13
FIGURE 5. Analog Input Timing
10
Functional Description (Continued)
TABLE I. MUX Addressing: ADC0854
Single-Ended MUX Mode
TABLE II. MUX Addressing: ADC0852
Single Ended MUX Mode
MUX Address
SGL/ ODD/
Channel
MUX Address
Channel
SGL/
ODD/
SIGN
SELECT
0
1
2
3
COM
0
1
DIF
SIGN
DIF
a
b
b
b
b
a
1
0
0
1
1
0
1
0
1
1
0
1
a
a
1
1
a
1
COM is internally tied to A GND
Differential MUX Mode
MUX Address
a
1
Channel
Differential MUX Mode
SGL/
DIF
ODD/
SIGN
0
1
MUX Address
ODD/
Channel
a
b
b
a
0
0
0
1
SGL/
DIF
SELECT
0
1
2
3
SIGN
a
b
0
0
0
0
0
0
1
1
0
1
0
1
a
b
b
a
b
a
4 Single-Ended
4 Pseudo-Differential
TL/H/5521–15
FIGURE 6. Analog Input Multiplexer Options for the ADC0854
11
Functional Description (Continued)
be done indefinitely, without reprogramming the device, as
long as CS remains low. Each new comparator decision will
be shifted to the output on the falling edge of the clock.
However, the output will, in effect, ‘‘lag’’ the analog input by
0.5 to 1.5 clock cycles because of the time required to make
the comparison and latch the output (see Figure 5).
2.0 THE DIGITAL INTERFACE
An important characteristic of the ADC0852 and ADC0854
is their serial data link with the controlling processor. A seri-
al communication format eliminates the transmission of low
level analog signals by locating the comparator close to the
signal source. Thus only highly noise immune digital signals
need to be transmitted back to the host processor.
8. All internal registers are cleared when the CS line is
brought high. If another comparison is desired CS must
make a high to low transition followed by new address and
threshold programming.
To understand the operation of these devices it is best to
refer to the timing diagrams (Figure 3) and functional block
diagram (Figure 2) while following a complete comparison
sequence.
3.0 REFERENCE CONSIDERATIONS / RATIOMETRIC
OPERATION
1. A comparison is initiated by first pulling the CS (chip se-
lect) line low. This line must be held low for the entire ad-
dressing sequence and comparison. The comparator then
waits for a start bit, its MUX assignment word, and an 8-bit
code to set the internal DAC which supplies the compara-
The voltage applied to the ‘‘V ’’ input of the DAC defines
REF
the voltage span that can be programmed to appear at the
threshold input of the comparator. The ADC0854 can be
used in either ratiometric applications or in systems with
tor’s threshold voltage (V ).
TH
absolute references. The V pin must be connected to a
REF
source capable of driving the DAC ladder resistance (typ.
2. An external clock is applied to the CLK input. This clock
can be applied continuously and need not be gated on and
off.
2.4 kX) with a stable voltage.
In ratiometric systems, the analog input voltage is normally
a proportion of the DAC’s or A/D’s reference voltage. For
example, a mechanical position servo using a potentiometer
to indicate rotation, could use the same voltage to drive the
reference as well as the potentiometer. Changes in the val-
3. On each rising edge of the clock, the level present on the
DI line is clocked into the MUX address shift register. The
start bit is the first logic ‘‘1’’ that appears on this line. All
leading zeroes are ignored. After the start bit, the ADC0852
expects the next 2 bits to be the MUX assignment word
while the ADC0854, with more MUX configurations, looks
for 3 bits.
ue of V
REF
would not affect system accuracy since only the
relative value of these signals to each other is important.
This technique relaxes the stability requirements of the sys-
tem reference since the analog input and DAC reference
move together, thus maintaining the same comparator out-
put for a given input condition.
4. Immediately after the MUX assignment word has been
clocked in, the shift register then reads the next eight bits as
the input code to the internal DAC. This eight bit word is
read LSB first and is used to set the voltage applied to the
comparator’s threshold input (internal).
In the absolute case, the V
input can be driven with a
REF
stable voltage source whose output is insensitive to time
and temperature changes. The LM385 and LM336 are good
low current devices for this purpose.
5. After the rising edge of the 11th or 12th clock (ADC0852
or ADC0854 respectively) following the start bit, the com-
parator and DAC programming is complete. At this point the
DI line is disabled and ignores further inputs. Also at this
time the data out (DO) line comes out of TRI-STATE and
enters a don’t care state (undefined output) for 1.5 clock
cycles.
The maximum value of V
is limited to the V
supply
CC
REF
voltage. The minimum value can be quite small (see typical
performance curves) allowing the effective resolution of the
e
2.0 mV). This in turn lets the designer
comparator threshold DAC to also be small (V
e
0.5V,
REF
DAC resolution
have finer control over the comparator trip point. In such
instances however, more care must be taken with regard to
noise pickup, grounding, and system error sources.
6. The result of the comparison between the programmed
threshold voltage and the difference between the two se-
a b
b
)) is output to the DO line on
lected inputs (V
each subsequent high to low clock transition.
(
)
V
IN
(
IN
7. After programming, continuous comparison on the same
selected channel with the same programmed threshold can
TL/H/5521–16
a) Ratiometric
b) Absolute with a Reduced Span
FIGURE 7. Referencing Examples
12
Functional Description (Continued)
4.0 ANALOG INPUTS
resistance. An op-amp RC active low pass filter can provide
both impedance buffering and noise filtering should a high
impedance source be required.
4. 1 Differential Inputs
The serial interface of the ADC0852 and ADC0854 allows
them to be located right at the analog signal source and to
communicate with a controlling processor via a few fairly
noise immune digital lines. This feature in itself greatly re-
duces the analog front end circuitry often needed to main-
tain signal integrity. Nevertheless, a few words are in order
with regard to the analog inputs should the input be noisy to
begin with or possibly riding on a large common mode volt-
age.
4. 3 Arbitrary Analog Input/Reference Range
The total span of the DAC output and hence the compara-
tor’s threshold voltage is determined by the DAC reference.
For example, if V
REF
is set to 1 volt then the comparator’s
threshold can be programmed over a 0 to 1 volt range with
8 bits of resolution. From the analog input’s point of view,
this span can also be shifted by applying an offset potential
to one of the comparator’s selected analog input lines (usu-
b
ally ‘‘ ’’). This gives the designer greater control of the
The differential input of the comparator actually reduces the
effect of common-mode input noise, i.e. signals common to
ADC0852/4’s input range and resolution and can help sim-
plify or eliminate expensive signal conditioning electronics.
a
b
both selected ‘‘ ’’ and ‘‘ ’’ inputs such as 60 Hz line
noise. The time interval between sampling the ‘‘ ’’ input
An example of this capability is shown in the ‘‘Load Cell
Limit Comparator’’ of Figure 15. In this circuit, the ADC0852
allows the load-cell signal conditioning to be done with only
one dual op-amp and without complex, multiple resistor
matching.
a
b
and then the ‘‘ ’’ input is (/2 of a clock period (see Figure
5).
The change in the common-mode voltage during this short
time interval can cause comparator errors. For a sinusoidal
common-mode signal this error is:
5.0 POWER SUPPLY
e
V
(MAX)
V
(2q f /2 f )
CM CLK
A unique feature of the ADC0854 is the inclusion of a 7 volt
a
(Figures 2 and8) ‘‘V ’’ also connects to ‘‘V ’’ via a silicon
CC
diode. The zener is intended for use as a shunt voltage
regulator to eliminate the need for additional regulating
components. This is especially useful if the ADC0854 is to
be remotely located from the system power source.
ERROR
PEAK
zener diode connected from the ‘‘V ’’ terminal to ground
a
where f
is the frequency of the common-mode signal,
is the DAC clock
CLK
CM
is its peak voltage value, and f
V
peak
frequency.
For example, 1 V
60 Hz noise superimposed on both
PP
sides of a differential input signal would cause an error (re-
ferred to the input) of 0.75 mV. This amounts to less than
(/25 of an LSB referred to the threshold DAC, (assuming
a
An important use of the interconnecting diode between V
and V is shown in Figures 10 and 11. Here this diode is
e
e
250 kHz).
CC
V
5V and f
REF
CLK
used as a rectifier to allow the V supply for the converter
CC
4. 2 Input Currents and Filtering
to be derived from the comparator clock. The low device
current requirements and the relatively high clock frequen-
cies used (10 kHz–400 kHz) allows use of the small value
filter capacitor shown. The shunt zener regulator can also
be used in this mode however this requires a clock voltage
swing in excess of 7 volts. Current limiting for the zener is
also needed, either built into the clock generator or through
Due to the sampling nature of the analog inputs, short
a
b
spikes of current enter the ‘‘ ’’ input and leave the ‘‘ ’’ at
the clock edges during a comparison. These currents decay
rapidly and do not cause errors as the comparator is
strobed at the end of the clock period (see Figure 5).
The source resistance of the analog input is important with
regard to the DC leakage currents of the input multiplexer.
a
a resistor connected from the clock to V
.
g
The worst-case leakage currents of 1 mA over tempera-
ture will create a 1 mV input error with a 1 kX source
Typical Applications
TL/H/5521–17
FIGURE 8. An On-Chip Shunt Regulator Diode
TL/H/5521–18
FIGURE 9. Using the ADC0854 as the
System Supply Regulator
13
Typical Applications (Continued)
TL/H/5521–19
FIGURE 10. Generating V from the Comparator Clock
CC
TL/H/5521–20
FIGURE 11. Remote SensingÐClock
and Power on One Wire
TL/H/5521–21
FIGURE 12. Protecting the Analog Input
TL/H/5521–22
FIGURE 13. One Component Window Comparator
Requires no additional parts. Window comparisons can be accomplished by
inputting the upper and lower window limits into DI on successive compari-
sons and observing the two outputs:
l
Two high outputs
Two low outputs
x
x
input
input
x
window
window
k
One low and one high
input is within window
14
Typical Applications (Continued)
TL/H/5521–23
FIGURE 14. Serial Input Temperature Controller
Note 1: ADC0854 does not require constant service from computer. Self controlled after one write to DI if CS remains low.
Ý
Note 2: U : Solid State Relay, Potter Brumfield EOM1DB22
1
Note 3: Set Temp via. DI. Range: 0 to 125 C
§
TL/H/5521–24
FIGURE 15. Load Cell Limit Comparator
Differential Input elliminates need for instrumentation amplifier
A total of 4 load cells can be monitored by ADC0854
#
#
15
Typical Applications (Continued)
TL/H/5521–26
TL/H/5521–29
e
* Q used in inverted mode for low V
1
Hysteresis band
50 mV
SAT
FIGURE 16. Adding Comparator Hysteresis
TL/H/5521–27
FIGURE 17. Pulse-Width Modulator
Range of pulse-widths controlled via R , C
1
#
1
16
Typical Applications (Continued)
TL/H/5521–28
FIGURE 18. Serial Input 8-Bit DAC
Ordering Information
Analog Input
Part Number
Channels
Total
Temperature
Package
Unadjusted Error
Range
g
g
ADC0852CCN
ADC0854CCN
2
4
1
1
N08E
N14A
0 C to 70 C
§
§
0 C to 70 C
§ §
17
18
Physical Dimensions inches (millimeters)
Dual-In-Line Package
Order Number ADC0852CCN
NS Package Number N08E
19
Physical Dimensions inches (millimeters) (Continued)
Dual-In-Line Package
Order Number ADC0854CCN
NS Package Number N14A
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