ADC08238CIN [NSC]
8-Bit 2 ms Serial I/O A/D Converters with MUX, Reference, and Track/Hold; 8位2毫秒串行I / OA / D转换器，复用器，参考和采样/保持
| 型号： | ADC08238CIN |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit 2 ms Serial I/O A/D Converters with MUX, Reference, and Track/Hold |
| 文件： | 总24页 (文件大小：420K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 1994
ADC08231/ADC08234/ADC08238 8-Bit 2 ms Serial I/O
A/D Converters with MUX, Reference, and Track/Hold
General Description
Features
Y
Serial digital data link requires few I/O pins
The ADC08231/ADC08234/ADC08238 are 8-bit succes-
sive approximation A/D converters with serial I/O and con-
figurable input multiplexers with up to 8 channels. The serial
I/O is configured to comply with the NSC MICROWIRETM
serial data exchange standard for easy interface to the
COPSTM family of controllers, and can easily interface with
standard shift registers or microprocessors.
Y
Analog input track/hold function
Y
4- or 8-channel input multiplexer options with address
logic
Y
g
On-chip 2.5V band-gap reference ( 2% over tempera-
ture guaranteed)
Y
Y
Y
No zero or full scale adjustment required
TTL/CMOS input/output compatible
0V to 5V analog input range with single 5V power
supply
Designed for high-speed/low-power applications, the devic-
es are capable of a fast 2 ms conversion when used with a
4 MHz clock.
All three devices provide a 2.5V band-gap derived reference
with guaranteed performance over temperature.
Y
Pin compatible with Industry-Standards ADC0831/4/8
A track/hold function allows the analog voltage at the posi-
tive input to vary during the actual A/D conversion.
Key Specifications
Y
Resolution
8 Bits
2 ms (Max)
The analog inputs can be configured to operate in various
combinations of single-ended, differential, or pseudo-differ-
ential modes. In addition, input voltage spans as small as 1V
can be accommodated.
Y
e
Conversion time (f
Power dissipation
Single supply
4 MHz)
C
Y
Y
Y
Y
Y
Y
20 mW (Max)
g
(/2 LSB and 1 LSB
5 V
(
5%)
DC
g
g
Total unadjusted error
e
No missing codes (over temperature)
g
(/2 LSB
Linearity Error (V
2.5V)
REF
Applications
Y
High-speed data acquisition
a
g
2.5V 1.5% (Max)
On-board Reference
Y
Digitizing automotive sensors
Y
Process control/monitoring
Y
Remote sensing in noisy environments
Y
Disk drives
Y
Portable instrumentation
Y
Test systems
ADC08238 Simplified Block Diagram
TL/H/11015–4
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
COPSTM microcontrollers and MICROWIRETM are trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/H/11015
RRD-B30M75/Printed in U. S. A.
Ordering Information
Industrial
s
Package
s
b
a
(
40 C
§
T
85 C)
§
A
ADC08231BIN, ADC08231CIN
ADC08234BIN, ADC08234CIN
ADC08234CIMF
N08E, DIP
N14A, DIP
MTB24, TSSOP
N20A, DIP
ADC08238BIN, ADC08238CIN
ADC08231BIWM, ADC08231CIWM
ADC08234BIWM, ADC08234CIWM
ADC08238BIWM, ADC08238CIWM
M14B, SO
M14B, SO
M20B, SO
Connection Diagrams
ADC08234
SO and DIP
ADC08238
SO and DIP
TL/H/11015–2
ADC08234
TSSOP
TL/H/11015–1
ADC08231
DIP
TL/H/11015–3
ADC08231
SO
TL/H/11015–27
TL/H/11015–26
2
Absolute Maximum Ratings (Notes 1 & 3)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Operating Ratings (Notes 2 & 3)
s
s
T
Temperature Range
T
MIN
T
A
A
MAX
s
s
a
b
ADC08231BIN, ADC08231CIN,
ADC08234BIN, ADC08234CIN,
ADC08238BIN, ADC08238CIN,
ADC08231BIWM, ADC08231CIWM,
ADC08234BIWM, ADC08238BIWM,
ADC08234CIWM, ADC08238CIWM,
ADC08234CIMF
40 C
§
T
85 C
§
Supply Voltage (V
)
6.5V
0.3V
5 mA
CC
b
a
g
Voltage at Inputs and Outputs
Input Current at Any Pin (Note 4)
Package Input Current (Note 4)
0.3V to V
CC
g
20 mA
e
Power Dissipation at T
25 C (Note 5)
§
800 mW
1500V
A
ESD Susceptibility (Note 6)
Supply Voltage (V
)
CC
4.5 V to 6.3 V
DC DC
Soldering Information
N Package (10 sec.)
TSSOP and SO Package (Note 7):
Vapor Phase (60 sec.)
Infrared (15 sec.)
260 C
§
215 C
§
220 C
§
b
a
65 C to 150 C
Storage Temperature
§
§
Electrical Characteristics
The following specifications apply for V
CC
e a
e a
e
e
4 MHz, R 50X unless otherwise
Source
5 V , V
DC REF
2.5 V and f
DC CLK
e
e
e
e
T 25 C.
J
specified. Boldface limits apply for T
T
T
MIN
to T
; all other limits T
MAX
§
A
J
A
ADC08231,
ADC08234 and
ADC08238 with BIN,
CIN, BIWM,
Units
Symbol
Parameter
Conditions
(Limits)
CIWM, or CIMF Suffixes
Typical Limits
(Note 9)
(Note 8)
CONVERTER AND MULTIPLEXER CHARACTERISTICS
e a
e a
e a
e a
Linearity Error
BIN, BIWM
V
V
V
V
2.5 V
2.5 V
2.5 V
REF
REF
REF
REF
DC
DC
DC
g
(2
LSB (max)
LSB (max)
g
CIN, CIMF, CIWM
1
Gain Error
g
g
BIN, BIWM
1
1
LSB (max)
LSB (max)
CIN, CIMF, CIWM
Zero Error
g
g
BIN, BIWM
1
1
LSB (max)
LSB (max)
CIN, CIMF, CIWM
Total Unadjusted Error
BIN, BIWM
5 V
DC
g
g
(Note 10)
1
1
LSB (max)
LSB (max)
CIN, CIMF, CIWM
e a
Differential Linearity
V
REF
2.5 V
8
Bits (min)
DC
R
REF
Reference Input Resistance
(Note 11)
3.5
kX
1.3
6.0
kX (min)
kX (max)
a
V
IN
Analog Input Voltage
(Note 12)
(V
CC
0.05)
V (max)
V (min)
b
(GND 0.05)
3
Electrical Characteristics (Continued)
e a
e a
e
e
50X unless otherwise
The following specifications apply for V
specified. Boldface limits apply for T
5 V , V
DC REF
2.5 V and f
DC
4 MHz, R
CC
CLK
source
e
T 25 C.
J
e
e
e
T
J
T
to T
; all other limits T
MAX
§
A
MIN
A
ADC08231,
ADC08234 and
ADC08238 with BIN,
CIN, BIWM,
Units
Symbol
Parameter
Conditions
(Limits)
CIWM, or CIMF Suffixes
Typical
(Note 8)
Limits
(Note 9)
CONVERTER AND MULTIPLEXER CHARACTERISTICS (Continued)
e a
g
g
DC Common-Mode Error
Power Supply Sensitivity
V
2.5 V
DC
(/2
LSB (max)
LSB (max)
REF
e a
g
5V 5%,
V
V
CC
(4
e a
2.5 V
REF
DC
e
e
On Channel Leakage
Current (Note 13)
On Channel
Off Channel
5V,
0V
0.2
mA (max)
mA (max)
mA (max)
mA (max)
1
e
e
b
0.2
On Channel
Off Channel
0V,
5V
b
1
e
e
b
0.2
Off Channel Leakage
Current (Note 13)
On Channel
Off Channel
5V,
0V
b
1
e
e
On Channel
Off Channel
0V,
5V
0.2
1
DYNAMIC CHARACTERISTICS (see Typical Converter Performance Characteristics)
S
e a
5V
Signal-to-
a
V
REF
Sample Rate
a
N
D
e
(Noise
Ratio
Distortion)
286 kHz
e a
V
IN
5 V
p-p
e
f
IN
f
IN
f
IN
10 kHz
50 kHz
100 kHz
48.35
48.00
47.40
dB
dB
dB
e
e
DIGITAL AND DC CHARACTERISTICS
e
CC
V
V
Logical ‘‘1’’ Input Voltage
Logical ‘‘0’’ Input Voltage
Logical ‘‘1’’ Input Current
Logical ‘‘0’’ Input Current
Logical ‘‘1’’ Output Voltage
V
V
V
V
V
5.25V
4.75V
5.0V
2.0
0.8
1
V (min)
V (max)
IN(1)
IN(0)
IN(1)
IN(0)
e
CC
IN
e
I
I
mA (max)
mA (max)
e
b
1
0V
IN
e
e b
e b
V
4.75V:
OUT(1)
CC
OUT
OUT
I
I
360 mA
10 mA
2.4
4.5
V (min)
V (min)
e
e
V
I
Logical ‘‘0’’ Output Voltage
V
4.75V
1.6 mA
0.4
V (max)
OUT(0)
CC
I
OUT
e
OUT
b
TRI-STATE Output Current
É
V
0V
5V
3.0
mA (max)
mA (max)
OUT
e
e
e
V
3.0
OUT
OUT
OUT
b
I
I
I
Output Source Current
Output Sink Current
V
0V
6.5
mA (min)
mA (min)
SOURCE
SINK
V
V
CC
8.0
e
HIGH
Supply Current
CS
CC
ADC08234, ADC08238
ADC08231 (Note 16)
3.0
6.0
mA (max)
mA (max)
4
Electrical Characteristics (Continued)
e a
e
4 MHz unless otherwise specified. Boldface limits apply for
The following specifications apply for V
CC
5 V and f
DC CLK
e
e
e
e
T 25 C.
J
T
T
J
T
to T
; all other limits T
MAX
§
A
MIN
A
ADC08231,
ADC08234 and
ADC08238 with BIN,
Units
CIN, BIWM,
Symbol
Parameter
Conditions
(Limits)
CIWM, or CIMF Suffixes
Typical
(Note 8)
Limits
(Note 9)
REFERENCE CHARACTERISTICS
V OUT
REF
Output Voltage
BIN, BIJ,
BIWM
2.5
g
2.5 1.5%
g
2%
V
CIN, CIJ,
2.5
g
2.5 3.0%
g
CIWM, CMJ
3.5%
DV
DV
/DT
REF
Temperature Coefficient
40
ppm/ C
§
/DI
REF
Load Regulation
(Note 17)
Sourcing
s
L
s
a
(0
I
4 mA)
L
ADC08234,
ADC08238
0.003
0.003
0.2
0.1
0.1
0.5
Sourcing
s
s
a
(0
I
2 mA)
L
ADC08231
%/mA
(max)
Sinking
s s
I
L
b
(
1
0 mA)
ADC08234,
ADC08238
Sinking
s
s
0 mA)
b
ADC08231
(
1
I
L
0.2
0.5
0.5
6
s
s
Line Regulation
4.75V
V
CC
5.25V
mV
(max)
e
I
Short Circuit Current
V
REF
0V
SC
ADC08234,
ADC08238
8
25
25
mA
(max)
e
ADC08231
V
REF
0V
8
T
SU
Start-Up Time
V
: 0V
CC
e
x
100 mF
5V
20
ms
C
L
DV
/Dt
REF
Long Term Stability
200
ppm/1 kHr
5
Electrical Characteristics (Continued)
e a
e a
; all other limits T
e
e
t 20 ns unless otherwise specified.
f
The following specifications apply for V
e
5 V , V
DC REF
2.5 V
and t
CC
T
DC
e
r
e
e
T 25 C.
J
Boldface limits apply for T
T
to T
§
A
J
MIN
MAX
A
Typical
(Note 8)
Limits
(Note 9)
Units
(Limits)
Symbol
Parameter
Clock Frequency
Conditions
f
10
kHz (min)
MHz (max)
CLK
4
Clock Duty Cycle
(Note 14)
40
60
% (min)
% (max)
e
f
CLK
T
C
Conversion Time (Not Including
MUX Addressing Time)
4 MHz
8
2
1/f (max)
CLK
ms (max)
t
t
t
Acquisition Time
1(2
1/f (max)
CA
CLK
ns
CLK High while CS is High
50
SELECT
SET-UP
CS Falling Edge or Data Input
Valid to CLK Rising Edge
25
20
ns (min)
ns (min)
t
Data Input Valid after CLK
Rising Edge
HOLD
e
100 pF:
Data MSB First
Data LSB First
t , t
pd1 pd0
CLK Falling Edge to Output
Data Valid (Note 15)
C
L
250
200
ns (max)
ns (max)
e
(see TRI-STATE Test Circuits)
e
L
t , t
1H 0H
TRI-STATE Delay from Rising Edge
of CS to Data Output and SARS Hi-Z
C
L
10 pF, R
10 kX
50
ns
e
e
2 kX
C
L
100 pF, R
180
ns (max)
pF
L
C
C
Capacitance of Logic Inputs
Capacitance of Logic Outputs
5
5
IN
pF
OUT
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur.
Note 2: Operating Ratings indicate conditions for which the device is functional. These ratings do not guarantee specific performance limits. For guaranteed
specifications and test conditions, see the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance
characteristics may degrade when the device is not operated under the listed test conditions.
e
e
0 V , unless otherwise specified.
DC
Note 3: All voltages are measured with respect to AGND
DGND
k
l
AV ,) the current at that pin should be limited to
CC
Note 4: When the input voltage (V ) at any pin exceeds the power supplies (V
IN IN
(AGND or DGND) or V
IN
5 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 5 mA to four
pins.
Note 5: The maximum power dissipation must be derated at elevated temperatures and is dictated by T
b
T
, i and the ambient temperature, T . The maximum
JA
)/i or the number given in the Absolute Maximum Ratings, whichever is lower. For devices
J
A
MAX
e
allowable power dissipation at any temperature is P
(T
J
D
with suffixes BIN, CIN, BIJ, CIJ, BIWM, and CIWM T
A JA
125 C. For devices with suffix CMJ, T
MAX
e
parts when board mounted follow: ADC08231 with BIN and CIN suffixes 120 C/W, ADC08234 with BIN and CIN suffixes 95 C/W, ADC08234 with CIMF suffix
e
150 C. The typical thermal resistances (i ) of these
§
§
J
J
JA
MAX
MAX
§
§
167 C/W, ADC08238 with BIN and CIN suffixes 80 C/W. ADC08231 with BIWM and CIWM suffixes 140 C/W, ADC08234 with BIWM and CIWM suffixes 140 C/W,
§
ADC08238 with BIWM and CIWM suffixes 91 C/W,
§
§
§
§
Note 6: Human body model, 100 pF capacitor discharged through a 1.5 kX resistor.
Note 7: See AN450 ‘‘Surface Mounting Methods and Their Effect on Product Reliability’’ or Linear Data Book section ‘‘Surface Mount’’ for other methods of
soldering surface mount devices.
e
Note 8: Typicals are at T
25 C and represent the most likely parametric norm.
§
Note 9: Guaranteed to National’s AOQL (Average Outgoing Quality Level).
J
e
a
5V only applies to the ADC08234
Note 10: Total unadjusted error includes zero, full-scale, linearity, and multiplexer error. Total unadjusted error with V
REF
and ADC08238. See Note 16.
Note 11: Cannot be tested for the ADC08231.
t
Note 12: For V
IN(
V
the digital code will be 0000 0000. Two on-chip diodes are tied to each analog input (see Block Diagram) which will forward-conduct
a
)
b
)
IN(
for analog input voltages one diode drop below ground or one diode drop greater than V supply. During testing at low V levels (e.g., 4.5V), high level analog
CC CC
inputs (e.g., 5V) can cause an input diode to conduct, especially at elevated temperatures. This will cause errors for analog inputs near full-scale. The specification
allows 50 mV forward bias of either diode; this means that as long as the analog V does not exceed the supply voltage by more than 50 mV, the output code will
IN
be correct. Exceeding this range on an unselected channel will corrupt the reading of a selected channel. Achievement of an absolute 0 V to 5 V input voltage
DC DC
range will therefore require a minimum supply voltage of 4.950 V
DC
over temperature variations, initial tolerance and loading.
Note 13: Channel leakage current is measured after a single-ended channel is selected and the clock is turned off. For off channel leakage current the following
two cases are considered: one, with the selected channel tied high (5 V ) and the remaining off channels tied low (0 V ), total current flow through the off
DC DC
channels is measured; two, with the selected channel tied low and the off channels tied high, total current flow through the off channels is again measured. The two
cases considered for determining on channel leakage current are the same except total current flow through the selected channel is measured.
Note 14: A 40% to 60% duty cycle range insures proper operation at all clock frequencies. In the case that an available clock has a duty cycle outside of these
limits the minimum time the clock is high or low must be at least 120 ns. The maximum time the clock can be high or low is 100 ms.
Note 15: Since data, MSB first, is the output of the comparator used in the successive approximation loop, an additional delay is built in (see Block Diagram) to
allow for comparator response time.
Note 16: For the ADC08231 V
REF
IN is internally tied to the on chip 2.5V band-gap reference output; therefore, the supply current is larger because it includes the
reference current (700 mA typical, 2 mA maximum).
Note 17: Load regulation test conditions and specifications for the ADC08231 differ from those of the ADC08234 and ADC08238 because the ADC08231 has the
on-board reference as a permanent load.
6
Typical Performance Characteristics
Linearity Error vs
Reference Voltage
Linearity Error vs
Temperature
Linearity Error vs
Clock Frequency
Note: For ADC08231 add I
(Note 16)
TL/H/11015–5
REF
Spectral Response with
10 kHz Sine Wave Input
Spectral Response with
50 kHz Sine Wave Input
Spectral Response with
100 kHz Sine Wave Input
TL/H/11015–6
7
Typical Reference Performance Characteristics
Output Drift
vs Temperature
(3 Typical Parts)
Line Regulation
(3 Typical Parts)
Load Regulation
TL/H/11015–7
8
TRI-STATE Test Circuits and Waveforms
t
1H
t
1H
TL/H/11015–8
TL/H/11015–9
Timing Diagrams
Data Input Timing
TL/H/11015–10
*To reset these devices, CLK and CS must be simultaneously high for a period of t
or greater.
SELECT
Data Output Timing
TL/H/11015–11
ADC08231 Start Conversion Timing
TL/H/11015–12
9
Timing Diagrams (Continued)
ADC08231 Timing
TL/H/11015–13
*LSB first output not available on ADC08231.
LSB information is maintained for remainder of clock periods until CS goes high.
To reset the ADC08231, CLK and CS must be simultaneusly high for a period of t
or greater. The ADC08231 also has one extra clock period for sampling
SELECT
the analog signal (t ). Otherwise it is compatible with the ADC0831.
ca
ADC08234 Timing
TL/H/11015–14
or greater. The ADC08234 also has one extra clock period for sampling
To reset the ADC08234, CLK and CS must be simultaneously high for a period of t
SELECT
the analog signal (t ). Otherwise it is compatible with the ADC0834.
ca
10
Timing Diagrams (Continued)
11
ADC08238 Functional Block Diagram
12
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of these converters utilizes a comparator struc-
ture with built-in sample-and-hold which provides for a dif-
ferential analog input to be converted by a successive-
approximation routine.
differentially with any other channel. In addition to selecting
differential mode the polarity may also be selected. Channel
0 may be selected as the positive input and channel 1 as
the negative input or vice versa. This programmability is
best illustrated by the MUX addressing codes shown in the
following tables for the various product options.
The actual voltage converted is always the difference be-
a
b
tween an assigned ‘‘ ’’ input terminal and a ‘‘ ’’ input ter-
minal. The polarity of each input terminal of the pair indi-
cates which line the converter expects to be the most posi-
The MUX address is shifted into the converter via the DI
line. Because the ADC08231 contains only one differential
input channel with a fixed polarity assignment, it does not
require addressing.
a
b
tive. If the assigned ‘‘ ’’ input voltage is less than the ‘‘ ’’
input voltage the converter responds with an all zeros out-
put code.
The common input line (COM) on the ADC08238 can be
used as a pseudo-differential input. In this mode the voltage
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels with software-configurable
single-ended, differential, or pseudo-differential (which will
convert the difference between the voltage at any analog
input and a common terminal) operation. The analog signal
conditioning required in transducer-based data acquisition
systems is significantly simplified with this type of input flexi-
bility. One converter package can now handle ground refer-
enced inputs and true differential inputs as well as signals
with some arbitrary reference voltage.
b
on this pin is treated as the ‘‘ ’’ input for any of the other
input channels. This voltage does not have to be analog
ground; it can be any reference potential which is common
to all of the inputs. This feature is most useful in single-sup-
ply applications where the analog circuitry may be biased up
to a potential other than ground and the output signals are
all referred to this potential.
TABLE I. Multiplexer/Package Options
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-
tial. Differential inputs are restricted to adjacent channel
pairs. For example, channel 0 and channel 1 may be select-
ed as a differential pair but channel 0 or 1 cannot act
Part
Number of Analog Channels Number of
Number
Package Pins
Single-Ended Differential
ADC08231
ADC08234
ADC08238
1
4
8
1
2
4
8
14
20
TABLE II. MUX Addressing: ADC08238
Single-Ended MUX Mode
MUX Address
Ý
Analog Single-Ended Channel
SGL/
DIF
ODD/
SIGN
SELECT
START
0
1
2
3
4
5
6
7
COM
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
a
b
b
b
b
b
b
b
b
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
a
a
a
a
a
a
a
13
Functional Description (Continued)
TABLE II. MUX Addressing: ADC08238 (Continued)
Differential MUX Mode
MUX Address
Ý
Analog Differential Channel-Pair
SGL/
DIF
ODD/
SIGN
SELECT
0
1
2
3
START
1
0
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
a
b
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
a
b
a
b
a
b
b
a
b
a
b
a
b
a
TABLE III. MUX Addressing: ADC08234
Single-Ended MUX Mode
Ý
MUX Address
Channel
1
SGL/
DIF
ODD/
SIGN
SELECT
START
0
2
3
1
0
1
0
1
a
1
1
1
1
1
1
1
1
0
0
1
1
a
a
a
COM is internally tied to AGND
Differential MUX Mode
MUX Address
Ý
Channel
1
SGL/
ODD/
SIGN
SELECT
START
0
2
3
DIF
1
0
1
0
1
a
b
a
1
1
1
1
0
0
0
0
0
0
1
1
a
b
b
a
b
14
Functional Description (Continued)
Since the input configuration is under software control, it
can be modified as required before each conversion. A
channel can be treated as a single-ended, ground refer-
enced input for one conversion; then it can be reconfigured
as part of a differential channel for another conversion. Fig-
ure 1 illustrates the input flexibility which can be achieved.
To understand the operation of these converters it is best to
refer to the Timing Diagrams and Functional Block Diagram
and to follow a complete conversion sequence. For clarity a
separate timing diagram is shown for each device.
1. A conversion is initiated by pulling the CS (chip select)
line low. This line must be held low for the entire conver-
sion. The converter is now waiting for a start bit and its
MUX assignment word.
The analog input voltages for each channel can range from
50mV below ground to 50mV above V (typically 5V) with-
CC
out degrading conversion accuracy.
2. On each rising edge of the clock the status of the data in
(DI) line is clocked into the MUX address shift register.
The start bit is the first logic ‘‘1’’ that appears on this line
(all leading zeros are ignored). Following the start bit the
converter expects the next 2 to 4 bits to be the MUX
assignment word.
2.0 THE DIGITAL INTERFACE
A most important characteristic of these converters is their
serial data link with the controlling processor. Using a serial
communication format offers two very significant system im-
provements; it allows many functions to be included in a
small package and it can eliminate the transmission of low
level analog signals by locating the converter right at the
analog sensor; transmitting highly noise immune digital data
back to the host processor.
l
TL/H/11015–17
FIGURE 1. Analog Input Multiplexer Options for the ADC08238
15
Functional Description (Continued)
3. When the start bit has been shifted into the start location
of the MUX register, the input channel has been assigned
and a conversion is about to begin. An interval of 1(/2
clock periods is automatically inserted to allow for sam-
pling the analog input. The SARS line goes high at the
end of this time to signal that a conversion is now in prog-
ress and the DI line is disabled (it no longer accepts
data).
This is possible because the DI input is only ‘‘looked-at’’
during the MUX addressing interval while the DO line is
still in a high impedance state.
3.0 REFERENCE CONSIDERATIONS
The V IN pin on these converters is the top of a resistor
REF
divider string and capacitor array used for the successive
approximation conversion. The voltage applied to this refer-
ence input defines the voltage span of the analog input (the
4. The data out (DO) line now comes out of TRI-STATE and
provides a leading zero.
difference between V
IN(MAX)
and V over which the
IN(MIN)
256 possible output codes apply). The reference source
must be capable of driving the reference input resistance,
which can be as low as 1.3 kX.
5. During the conversion the output of the SAR comparator
indicates whether the analog input is greater than (high)
or less than (low) a series of successive voltages gener-
ated internally from a ratioed capacitor array (first 5 bits)
and a resistor ladder (last 3 bits). After each comparison
the comparator’s output is shipped to the DO line on the
falling edge of CLK. This data is the result of the conver-
sion being shifted out (with the MSB first) and can be
read by the processor immediately.
For absolute accuracy, where the analog input varies be-
tween specific voltage limits, the reference input must be
biased with a stable voltage source. The ADC08234 and the
ADC08238 provide the output of a 2.5V band-gap reference
at V
OUT. This voltage does not vary appreciably with
REF
temperature, supply voltage, or load current (see Reference
Characteristics in the Electrical Characteristics tables) and
6. After 8 clock periods the conversion is completed. The
SARS line returns low to indicate this (/2 clock cycle later.
can be tied directly to V
IN for an analog input span of 0V
REF
to 2.5V. This output can also be used to bias external cir-
cuits and can therefore be used as the reference in ratio-
7. The stored data in the successive approximation register
is loaded into an internal shift register. If the programmer
prefers, the data can be provided in an LSB first format
metric applications. Bypassing V
pacitor is recommended.
OUT with a 100 mF ca-
REF
[
]
this makes use of the shift enable (SE) control line . On
For the ADC08231, the output of the on-board reference is
internally tied to the reference input. Consequently, the ana-
log input span for this device is set at 0V to 2.5V. The pin
the ADC08238 the SE line is brought out and if held high
the value of the LSB remains valid on the DO line. When
SE is forced low the data is clocked out LSB first. On
devices which do not include the SE control line, the
data, LSB first, is automatically shifted out the DO line
after the MSB first data stream. The DO line then goes
low and stays low until CS is returned high. The
ADC08231 is an exception in that its data is only output in
MSB first format.
V C is provided for bypassing purposes and biasing ex-
REF
ternal circuits as suggested above.
The maximum value of the reference is limited to the V
CC
supply voltage. The minimum value, however, can be quite
small (see Typical Performance Characteristics) to allow di-
rect conversions of transducer outputs providing less than a
5V output span. Particular care must be taken with regard to
noise pickup, circuit layout and system error voltage sourc-
es when operating with a reduced span due to the in-
8. All internal registers are cleared when the CS line is high
requirement is met. See Data Input Tim-
and the t
SELECT
ing under Timing Diagrams. If another conversion is de-
sired CS must make a high to low transition followed by
address information.
creased sensitivity of the converter (1 LSB equals V
256).
REF/
The DI and DO lines can be tied together and controlled
through a bidirectional processor I/O bit with one wire.
TL/H/11015–19
TL/H/11015–18
b) Absolute
a) Ratiometric
FIGURE 2. Reference Examples
16
Functional Description (Continued)
4.0 THE ANALOG INPUTS
The zero error of the A/D converter relates to the location
of the first riser of the transfer function and can be mea-
The most important feature of these converters is that they
can be located right at the analog signal source and through
just a few wires can communicate with a controlling proces-
sor with a highly noise immune serial bit stream. This in itself
greatly minimizes circuitry to maintain analog signal accura-
cy which otherwise is most susceptible to noise pickup.
However, a few words are in order with regard to the analog
inputs should the input be noisy to begin with or possibly
riding on a large common-mode voltage.
b
sured by grounding the V
IN
( ) input and applying a small
a
) input. Zero error
magnitude positive voltage to the V
IN
(
is the difference between the actual DC input voltage which
is necessary to just cause an output digital code transition
from 0000 0000 to 0000 0001 and the ideal (/2 LSB value
e
e
5.000V ).
DC
((/2 LSB
9.8mV for V
REF
5.2 Full Scale
A full-scale adjustment can be made by applying a differen-
tial input voltage which is 1(/2 LSB down from the desired
analog full-scale voltage range and then adjusting the mag-
The differential input of these converters actually reduces
the effects of common-mode input noise, a signal common
a
b
to both selected ‘‘ ’’ and ‘‘ ’’ inputs for a conversion
(60 Hz is most typical). The time interval between sampling
nitude of the V
IN input for a digital output code which is
just changing from 1111 1110 to 1111 1111 (See figure enti-
REF
a
b
the ‘‘ ’’ input and then the ‘‘ ’’ input is (/2 of a clock peri-
od. The change in the common-mode voltage during this
short time interval can cause conversion errors. For a sinus-
oidal common-mode signal this error is:
s
s
tled ‘‘Span Adjust; 0V
with the ADC08234 and ADC08238. (The reference is inter-
nally connected to V IN of the ADC08231).
V
3V’’). This is possible only
IN
REF
5.3 Adjusting for an Arbitrary Analog Input
Voltage Range
0.5
e
V
(max)
error
V
PEAK
(2qf
)
CM
f
# J
CLK
If the analog zero voltage of the A/D is shifted away from
ground (for example, to accommodate an analog input sig-
nal which does not go to ground), this new zero reference
where f
V
is the frequency of the common-mode signal,
is its peak voltage value
CM
PEAK
a
) voltage which
equals this desired zero reference plus (/2 LSB (where the
should be properly adjusted first. A V
IN
(
and f
CLK
is the A/D clock frequency.
For a 60Hz common-mode signal to generate a (/4 LSB er-
LSB is calculated for the desired analog span, using 1 LSB
e a
analog span/256) is applied to selected ‘‘ ’’ input and
the zero reference voltage at the corresponding ‘‘ ’’ input
&
ror ( 5mV) with the converter running at 250kHz, its peak
value would have to be 6.63V which would be larger than
b
allowed as it exceeds the maximum analog input limits.
should then be adjusted to just obtain the 00
code transition.
to 01
HEX
HEX
Source resistance limitation is important with regard to the
DC leakage currents of the input multiplexer. While operat-
ing near or at maximum speed, bypass capacitors should
not be used if the source resistance is greater than 1kX.
[
The full-scale adjustment should be made with the proper
a
)
b
]
) voltage applied by forcing a voltage to the V
V
(
(
IN
input which is given by:
IN
g
The worst-case leakage current of 1mA over temperature
b
(V
MAX
V
MIN
)
will create a 1mV input error with a 1kX source resistance.
An op amp RC active low pass filter can provide both im-
pedance buffering and noise filtering should a high imped-
ance signal source be required.
a
e
b
1.5
MAX
V
(
) fs adj
V
IN
256
Ð
(
where:
e
V
and
V
the high end of the analog input range
MAX
5.0 OPTIONAL ADJUSTMENTS
e
5.1 Zero Error
the low end (the offset zero) of the analog range.
(Both are ground referenced.)
MIN
The zero of the A/D does not require adjustment. If the
minimum analog input voltage value, V
, is not ground
IN(MIN)
The V
REF
code change from FE
justment procedure.
IN (or V ) voltage is then adjusted to provide a
CC
a zero offset can be done. The converter can be made to
output 0000 0000 digital code for this minimum input voltage
to FF . This completes the ad-
HEX
HEX
b
by biasing any V
(
) input at this V
value. This
IN(MIN)
IN
utilizes the differential mode operation of the A/D.
17
Applications
A ‘‘Stand-Alone’’ Hook-Up for ADC08238 Evaluation
*Pinouts sh
For all oth
TL/H/11015–21
18
Applications (Continued)
Protecting the Input
TL/H/11015–22
Operating with Ratiometric Transducers
b
e
0.15 V
REF
*V
(
)
IN
15% of V
s
s
85% of V
V
XDR
REF
REF
TL/H/11015–23
s
s
3V
Span Adjust; 0V
V
IN
TL/H/11015–24
19
Applications (Continued)
s
s
5V
Zero-Shift and Span Adjust: 2V
V
IN
TL/H/11015–25
20
Physical Dimensions inches (millimeters)
Order Number ADC08231BIWM, ADC08231CIWM,
ADC08234BIWM or ADC08234CIWM
NS Package Number M14B
Order Number ADC08238BIWM or ADC08238CIWM
NS Package Number M20B
21
Physical Dimensions inches (millimeters) (Continued)
TSSOP Molded Package
Order Number ADC08234CIMF
NS Package Number MTB24
Order Number ADC08231BIN or ADC08231CIN
NS Package Number N08E
22
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC08234BIN or ADC08234CIN
NS Package Number N14A
23
Physical Dimensions inches (millimeters) (Continued)
Molded Dual-In-Line Package (N)
Order Number ADC08238CIN or ADC08238BIN
NS Package Number N20A
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