9403ADCQR [NSC]
IC 16 X 4 OTHER FIFO, CDIP24, CERAMIC, DIP-24, FIFO;
| 型号： | 9403ADCQR |
| 厂家： | 
National Semiconductor |
| 描述： | IC 16 X 4 OTHER FIFO, CDIP24, CERAMIC, DIP-24, FIFO 先进先出芯片 CD 内存集成电路 |
| 文件： | 总20页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1989
9403A
First-In First-Out (FIFO) Buffer Memory
General Description
Features
Y
Serial or parallel input
The 9403A is an expandable fall-through type high-speed
First-In First-Out (FIFO) Buffer Memory optimized for high-
speed disk or tape controllers and communication buffer
applications. It is organized as 16-words by 4-bits and may
be expanded to any number of words or any number of bits
in multiples of four. Data may be entered or extracted asyn-
chronously in serial or parallel, allowing economical imple-
mentation of buffer memories.
Y
Serial or parallel output
Y
Expandable without external logic
Y
TRI-STATE outputs
Y
Fully compatible with all TTL families
Y
Slim 24-pin package
The 9403A has TRI-STATE outputs which provide added
É
versatility and is fully compatible with all TTL families.
Connection Diagrams
Pin Assignment
for DIP, SOIC and Flatpak
Pin Assignment
for LCC and PCC
TL/F/10193–1
TL/F/10193–2
FASTÉ and TRI-STATEÉ are registered trademarks of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/10193
RRD-B30M105/Printed in U. S. A.
Logic Symbol
TL/F/10193–3
Unit Loading/Fan Out
U.L.
Input I /I
IH IL
Pin Names
Description
HIGH/LOW
Output I /I
OH OL
D –D
0
Parallel Data Inputs
Serial Data Input
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
2.0/0.667
285/26.7
285/26.7
20/13.3
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
40 mA/400 mA
5.7 mA/16 mA
5.7 mA/16 mA
3
D
S
PL
Parallel Load Input
Serial Input Clock
Serial Input Enable
Transfer to Stack Input
Serial Output Enable
Transfer Out Serial
Transfer Out Parallel
Master Reset
CPSI
IES
TTS
OES
TOS
TOP
MR
OE
Output Enable
CPSO
Q –Q
Serial Output Clock
Parallel Data Outputs
Serial Data Output
Input Register Full
Output Register Empty
0
3
Q
S
b
IRF
400 mA/8 mA
400 mA/8 mA
b
ORE
20/13.3
2
Block Diagram
TL/F/10193–4
Functional Description
As shown in the block diagram the 9403A consists of three
sections:
the F flip-flop and resetting the other flip-flops. The Q out-
3
put of the last flip-flop (FC) is brought out as the ‘Input Reg-
ister Full’ output (IRF). After initialization this output is HIGH.
1. An Input Register with parallel and serial data inputs as
well as control inputs and outputs for input handshaking
and expansion.
Parallel EntryÐA HIGH on the PL input loads the D –D
0
3
inputs into the F –F flip-flops and sets the FC flip-flop. This
0
3
forces the IRF output LOW indicating that the input register
is full. During parallel entry, the CPSI input must be LOW. If
parallel expansion is not being implemented, IES must be
LOW to establish row mastership (see Expansion section).
2. A 4-bit wide, 14-word deep fall-through stack with self-
contained control logic.
3. An Output Register with parallel and serial data outputs
as well as control inputs and outputs for output hand-
shaking and expansion.
Serial EntryÐData on the D input is serially entered into
S
the F , F , F , F , FC shift register on each HIGH-to-LOW
3
2
1
0
Since these three sections operate asynchronously and al-
most independently, they will be described separately be-
low.
transition of the CPSI clock input, provided IES and PL are
LOW.
After the fourth clock transition, the four data bits are locat-
ed in the four flip-flops, F –F . The FC flip-flop is set, forc-
INPUT REGISTER (DATA ENTRY)
0
3
The Input Register can receive data in either bit-serial or in
4-bit parallel form. It stores this data until it is sent to the fall-
through stack and generates the necessary status and con-
trol signals.
ing the IRF output LOW and internally inhibiting CPSI clock
pulses from affecting the register, Figure 2 illustrates the
final positions in a 9403A resulting from a 64-bit serial bit
train. B is the first bit, B the last bit.
63
0
Figure 1 is a conceptual logic diagram of the input section.
As described later, this 5-bit register is initialized by setting
3
Functional Description (Continued)
TL/F/10193–5
FIGURE 1. Conceptual Input Section
through’ action. If the top location of the stack is empty,
data is loaded into the stack and the input register is re-ini-
tialized. Note that this initialization is postponed until PL is
LOW again. Thus, automatic FIFO action is achieved by
connecting the IRF output to the TTS input.
An RS Flip-Flop (the Request Initialization Flip-Flop shown
in Figure 10 ) in the control section records the fact that
data has been transferred to the stack. This prevents multi-
ple entry of the same word into the stack despite the fact
the IRF and TTS may still be LOW. The Request Initializa-
tion Flip-Flop is not cleared until PL goes LOW. Once in the
stack, data falls through the stack automatically, pausing
only when it is necessary to wait for an empty next location.
In the 9403A as in most modern FIFO designs, the MR input
only initializes the stack control section and does not clear
the data.
OUTPUT REGISTER (DATA EXTRACTION)
The Output Register receives 4-bit data words from the bot-
tom stack location, stores it and outputs data on a TRI-
STATE 4-bit parallel data bus or on a TRI-STATE serial data
bus. The output section generates and receives the neces-
sary status and control signals. Figure 3 is a conceptual
logic diagram of the output section.
TL/F/10193–6
FIGURE 2. Final Positions in a 9403A Resulting from a
64-Bit Serial Train
Transfer to the StackÐThe outputs of Flip-Flops F –F
0
3
feed the stack. A LOW level on the TTS input initiates a ‘fall-
4
Functional Description (Continued)
TL/F/10193–7
FIGURE 3. Conceptual Output Section
Parallel Data ExtractionÐWhen the FIFO is empty after a
LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided the ‘Trans-
fer Out Parallel’ (TOP) input is HIGH. As a result of the data
transfer ORE goes HIGH, indicating valid data on the data
outputs (provided the TRI-STATE buffer is enabled). TOP
can now be used to clock out the next word. When TOP
goes LOW, ORE will go LOW indicating that the output data
has been extracted, but the data itself remains on the output
bus until the next HIGH level at TOP permits the transfer of
the next word (if available) into the Output Register. During
parallel data extraction CPSO should be LOW. TOS should
be grounded for single slice operation or connected to the
appropriate ORE for expanded operation (see Expansion
section).
control circuitry prevents the same data from being trans-
ferred twice. If TOP goes HIGH and returns to LOW before
data is available from the stack, ORE remains LOW indicat-
ing that there is no valid data at the outputs.
Serial Data ExtractionÐWhen the FIFO is empty after a
LOW pulse is applied to MR, the Output Register Empty
(ORE) output is LOW. After data has been entered into the
FIFO and has fallen through to the bottom stack location, it
is transferred into the Output Register provided TOS is LOW
and TOP is HIGH. As a result of the data transfer ORE goes
HIGH indicating valid data in the register. The TRI-STATE
Serial Data Output, Q , is automatically enabled and puts
S
the first data bit on the output bus. Data is serially shifted
out on the HIGH-to-LOW transition of CPSO. To prevent
false shifting, CPSO should be LOW when the new word is
being loaded into the Output Register. The fourth transition
empties the shift register, forces ORE output LOW and dis-
TOP is not edge triggered. Therefore, if TOP goes HIGH
before data is available from the stack, but data does be-
come available before TOP goes LOW again, that data will
be transferred into the Output Register. However, internal
ables the serial output, Q (refer to Figure 3 ). For serial
S
operation the ORE output may be tied to the TOS input,
requesting a new word from the stack as soon as the previ-
ous one has been shifted out.
5
Functional Description (Continued)
EXPANSION
a
(15n 1)-words by 4-bits can be constructed, where n is the
number of devices. Note that expansion does not sacrifice
any of the 9403A’s flexibility for serial/parallel input and out-
put.
Vertical ExpansionÐThe 9403A may be vertically expand-
ed to store more words without external parts. The intercon-
nection is necessary to form a 46-word by 4-bit FIFO are
shown in Figure 4. Using the same technique, and FIFO of
TL/F/10193–8
FIGURE 4. A Vertical Expansion Scheme
6
Functional Description (Continued)
Horizontal ExpansionÐThe 9403A can also be horizontal-
ly expanded to store long words (in multiples of four bits)
without external logic. The interconnections necessary to
form a 16-word by 12-bit FIFO are shown in Figure 5. Using
the same technique, any FIFO of 16 words by 4n bits can be
constructed, where n is the number of devices. The IRF
output of the right most device (most significant device) is
connected to the TTS inputs of all devices. Similarly, the
ORE output of the most significant device is connected to
the TOS inputs of all devices. As in the vertical expansion
scheme, horizontal expansion does not sacrifice any of the
9403A’s flexibility for serial/parallel input and output.
master in their row. No slave in a given row will initialize its
Input Register until it has received LOW on its IES input
from a row master or a slave of higher priority.
In a similar fashion, the ORE outputs of slaves will not go
HIGH until their OES inputs have gone HIGH. This interlock-
ing scheme ensures that new input data may be accepted
by the array when the IRF output of the final slave in that
row goes HIGH and that output data for the array may be
extracted when the ORE of the final slave in the output row
goes HIGH.
The row master is established by connecting its IES input to
ground while a slave receives its IES input from the IRF
output of the next higher priority device. When an array of
9403A FIFOs is initialized with a LOW on the MR inputs of
all devices, the IRF outputs of all devices will be HIGH.
Thus, only the row master receives a LOW on the IES input
during initialization. Figure 10 is a conceptual logic diagram
of the internal circuitry which determines master/slave oper-
ation. Whenever MR and IES are LOW, the Master Latch is
set. Whenever TTS goes LOW the Request Initialization
Flip-Flop will be set. If the Master Latch is HIGH, the Input
Register will be immediately initialized and the Request Ini-
tialization Flip-Flop reset. If the Master Latch is reset, the
Input Register is not initialized until IES goes LOW. In array
operation, activating the TTS initiates a ripple input register
initialization from the row master to the last slave.
Horizontal and Vertical ExpansionÐThe 9403A can be
expanded in both the horizontal and vertical directions with-
out any external parts and without sacrificing any of its FI-
FO’s flexibility for serial/parallel input and output. The inter-
connections necessary to form a 31-word by 16-bit FIFO are
shown in Figure 6. Using the same technique, any FIFO of
a
(15m 1)-words by (4n)-bits can be constructed, where m is
the number of devices in a column and n is the number of
devices in a row. Figures 7 and 8 show the timing diagrams
for serial data entry and extraction for the 31-word by 16-bit
FIFO shown in Figure 6. The final position of data after seri-
al insertion of 496 bits into the FIFO array of Figure 6 is
shown in Figure 9.
Interlocking CircuitryÐMost conventional FIFO designs
provide status signals analogous to IRF and ORE. However,
when these devices are operated in arrays, variations in unit
to unit operating speed require external gating to assure all
devices have completed an operation. The 9403A incorpo-
rates simple but effective ‘master/slave’ interlocking circuit-
ry to eliminate the need for external gating.
A similar operation takes place for the output register. Either
a TOS or TOP input initiates a load-from-stack operation
and sets the ORE Request Flip-Flop. If the Master Latch is
set, the last Output Register Flip-Flop is set and ORE goes
HIGH. If the Master Latch is reset, the ORE output will be
LOW until an OES input is received.
In the 9403A array of Figure 6 devices 1 and 5 are defined
as ‘row masters’ and the other devices are slaves to the
TL/F/10193–9
FIGURE 5. A Horizontal Expansion Scheme
7
Functional Description (Continued)
TL/F/10193–10
FIGURE 6. A 31 x 16 FIFO Array
8
Functional Description (Continued)
TL/F/10193–11
FIGURE 7. Serial Data Entry for Array ofFigure 6
TL/F/10193–12
FIGURE 8. Serial Data Extraction for Array ofFigure 6
9
Functional Description (Continued)
TL/F/10193–13
FIGURE 9. Final Position of a 496-Bit Serial Input
TL/F/10193–14
FIGURE 10. Conceptual Diagram, Interlocking Circuitry
10
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Free Air Ambient Temperature
Military
Commercial
b
a
55 C to 125 C
§
0 C to 70 C
§
b
b
b
a
65 C to 150 C
Storage Temperature
§
§
§
§
a
§
§
a
55 C to 125 C
Ambient Temperature under Bias
Junction Temperature under Bias
§
Supply Voltage
Military
Commercial
a
55 C to 175 C
a
a
a
4.5V to 5.5V
a
4.5V to 5.5V
§
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
Voltage Applied to Output
b
a
30 mA to 5.0 mA
e
in HIGH State (with V
Standard Output
TRI-STATE Output
0V)
CC
b
0.5V to 5.5V
0.5V to V
CC
b
a
Current Applied to Output
in LOW State (Max)
twice the rated I (mA)
OL
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
DC Electrical Characteristics
Symbol
Parameter
Input HIGH Voltage
Min
Typ
Max
Units
V
Conditions
CC
V
V
V
V
2.0
V
V
V
Recognized as a HIGH Signal
Recognized as a LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
1.5
Min
Min
I
CD
OH
IN
e b
e b
e b
e b
Output HIGH
Voltage
54F 10% V
2.4
2.4
2.4
2.4
I
I
I
I
400 mA (IRF, ORE)
2.0 mA (Q , Q )
CC
CC
CC
CC
OH
OH
OH
OH
54F 10% V
74F 10% V
74F 10% V
n
s
V
V
400 mA (IRF, ORE)
5.7 mA (Q , Q )
n
s
e
e
e
e
V
OL
Output LOW
Voltage
54F 10% V
54F 10% V
74F 10% V
74F 10% V
0.4
I
I
I
I
4 mA (IRF, ORE)
8 mA (Q , Q )
CC
CC
CC
CC
OL
OL
OL
OL
0.4
0.5
0.5
n
s
Min
8 mA (IRF, ORE)
16 mA (Q , Q )
n
s
e
e
I
I
Input HIGH Current
40
mA
mA
Max
Max
V
V
2.7V
7.0V
IH
IN
IN
Input HIGH Current
Breakdown Test
BVI
100
b
e
I
I
I
I
I
I
Input LOW Current
0.45
mA
mA
mA
mA
mA
mA
Max
Max
Max
Max
Max
Max
V
V
V
V
V
V
0.4V
IL
IN
e
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output HIGH Leakage Current
Power Supply Current
100
2.4V
0.5V
0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
b
e
e
e
100
130
b
b
30
250
170
V
CC
CEX
CCL
e
LOW
O
11
AC Electrical Characteristics
Comm
Mil
CC
Comm
e a
T
25 C
§
5.0V
A
e
e
50 pF
T
, V
Mil
T
A
, V
Com
Fig.
No.
A
CC
e
e a
Symbol
Parameter
V
Units
CC
e
C
50 pF
C
L
L
e
C
50 pF
L
Min
Max
Min
Max
Min
Max
t
t
Propagation Delay,
Negative-Going
PHL
1.5
20.0
1.5
29.0
46.0
1.5
21.0
38.0
CPSI to IRF Output
ns
9403A-a,b
Propagation Delay,
Negative-Going
TTS to IRF
PLH
1.5
36.0
1.5
1.5
t
t
Propagation Delay,
Negative-Going
1.5
1.5
28.0
28.0
1.5
1.5
33.0
33.0
1.5
1.5
29.0
29.0
PLH
ns
nsd
ns
9403A-c, d
9403A-e
PHL
CPSO to Q Output
S
t
t
Propagation Delay,
Positive-Going
1.5
1.5
46.0
46.0
1.5
1.5
53.0
53.0
1.5
1.5
48.0
48.0
PLH
PHL
TOP to Outputs Q –Q
0
3
t
t
t
t
t
t
Propagation Delay,
Negative-Going
CPSO to ORE
PHL
PHL
PLH
PLH
PHL
PLH
1.5
1.5
1.5
1.5
1.5
1.5
35.0
37.0
47.0
42.5
28.0
24.0
1.5
1.5
1.5
1.5
1.5
1.5
41.0
45.0
53.0
50.0
36.0
29.0
1.5
1.5
1.5
1.5
1.5
1.5
37.0
39.0
49.0
45.0
29.0
25.0
9403A-c, d
Propagation Delay,
Negative-Going
TOP to ORE
ns
9403A-e
Propagation Delay,
Positive-Going
TOP to ORE
Propagation Delay,
Negative-Going
ns
ns
9403A-c, d
9403A-g, h
TOS to Positive Going ORE
Propagation Delay,
Positive-Going
PL to Negative-Going IRF
Propagation Delay,
Negative-Going
PL to Positive-Going IRF
12
AC Electrical Characteristics
74F
54F
74F
e a
T
25 C
§
5.0V
A
e
50 pF
e
T
, V
CC
e
Mil
T
, V
Com
e
50 pF
Fig.
No.
A
A CC
e a
Symbol
Parameter
V
Units
CC
C
C
L
L
e
C
50 pF
L
Min
Max
Min
Max
Min
Max
t
t
Propagation Delay,
Positive-Going
OES to ORE
PLH
PLH
1.5
39.5
1.5
38.0
1.5
41.0
21.0
ns
ns
Propagation Delay,
Positive-Going
1.5
20.0
1.5
25.0
1.5
9403A-h
IES to Positive-Going IRF
t
t
Propagation Delay,
MR to IRF
PLH
PHL
1.5
1.5
20.0
33.0
1.5
1.5
20.0
43.0
1.5
1.5
20.0
35.0
ns
ns
Propagation Delay,
MR to ORE
t
t
Propagation Delay,
1.5
1.5
14.0
14.0
1.0
1.0
25.0
25.0
1.5
1.5
14.0
14.0
PZH
PZL
OE to Q , Q , Q , Q
2
0
1
3
ns
ns
t
t
Propagation Delay,
OE to Q , Q , Q , Q
1.5
1.5
14.0
14.0
1.0
1.0
25.0
25.0
1.5
1.5
14.0
14.0
PHZ
PLZ
0
1
2
3
t
t
Propagation Delay,
Negative-Going
1.5
1.5
16.5
17.0
1.0
1.0
30.0
30.0
1.5
1.5
17.0
17.0
PZH
PZL
OES to Q
S
t
t
Propagation Delay,
Negative-Going
1.5
1.5
14.0
14.0
1.0
1.0
30.0
30.0
1.5
1.5
14.0
14.0
PHZ
PLZ
OES to Q
S
t
t
Turn On Time
TOS to Q
1.5
1.5
60.0
60.0
1.5
1.5
60.0
60.0
1.5
1.5
60.0
60.0
PZH
PZL
ns
ns
s
t
t
Fall Through Time
Parallel Appearance Time,
ORE to Q –Q
500
6.5
500
500
7.0
9403A-f
DFT
AP
b
b
b
19.0
20.0
20.0
10.0
20.0
10.0
0
3
ns
ns
t
t
Serial Appearance Time,
ORE to Q
AS
b
b
b
9.5
14.5
470
25.0
500
15.0
500
S
Bubble-Up Time
DBU
13
AC Operating Requirements
74F
54F
74F
e a
T
A
25 C
Fig.
No.
§
5.0V
e
e
Symbol
Parameter
T
, V
CC
Mil
T
, V
A CC
Com
Max
Units
A
e a
V
CC
Min
Max
Min
Max
Min
t (H)
s
Set-up Time HIGH or LOW
15.5
15.5
30.0
30.0
16.0
16.0
t (L)
s
D to Negative CPSI
s
ns
9403A-a, b
t (H)
h
Hold Time, HIGH or LOW
D to CPSI
s
2.0
2.0
8.0
8.0
2.0
2.0
t (L)
h
t (L)
s
Set-up Time, LOW
18.0
65.0
50.0
18.0
70.0
ns
ns
9403A-b
9403A-b
Negative-Going IES to CPSI
t (L)
s
Set-up Time, LOW
110.0
Negative-Going TTS to CPSI
t (H)
s
Set-up Time, HIGH or LOW
Parallel Inputs to PL
0
0
1.0
1.0
0
0
t (L)
s
ns
t (H)
h
Hold Time, HIGH or LOW
Parallel Inputs to PL
0
0
6.0
6.0
0
0
t (L)
h
t
t
(H)
(L)
CPSI Pulse Width
HIGH or LOW
30
20
52.0
25.0
32
20
w
ns
ns
ns
ns
ns
9403A-a, b
9403A-g, h
w
t
(H)
PL Pulse Width, HIGH
16.5
16.0
15.0
20.0
20.0
20.0
17.0
17.0
15.0
w
w
t
(L)
TTS Pulse Width, LOW
Serial or Parallel Mode
9403A-a, b,
c, d
t
w
(L)
MR Pulse Width, LOW
9403A-f
9403A-e
t
t
(H)
(L)
TOP Pulse Width
HIGH or LOW
15.0
15.0
22.0
20.0
17.0
15.0
w
w
t
t
(H)
(L)
CPSO Pulse Width
HIGH or LOW
17.0
17.0
20.0
20.0
17.0
18.0
w
ns
ns
9403A-c, d
9403A-f
w
t
Recovery Time
MR to Any Input
rec
16.5
25.0
19.0
14
Timing Waveforms
TL/F/10193–15
Conditions: stack not full, IES, PL LOW
FIGURE 9403A-a. Serial Input, Unexpanded or Master Operation
TL/F/10193–16
Conditions: stack not full, IES HIGH when initiated, PL LOW
FIGURE 9403A-b. Serial Input, Expanded Slave Operation
TL/F/10193–17
Conditions: data in stack, TOP HIGH, IES LOW when initiated, OES LOW
FIGURE 9403A-c. Serial Output, Unexpanded or Master Operation
15
Timing Waveforms (Continued)
TL/F/10193–18
Conditions: data in stack, TOP HIGH, IES HIGH when initiated
FIGURE 9403A-d. Serial Output, Slave Operation
TL/F/10193–19
Conditions: IES LOW when initiated, OE, CPSO LOW; data available in stack
FIGURE 9403A-e. Parallel Output, 4-Bit Word or Master in Parallel Expansion
TL/F/10193–20
Conditions: TTS connected to IRF, TOS connected to ORE, IES, OES, OE, CPSO LOW, TOP HIGH
FIGURE 9403A-f. Fall Through Time
16
Timing Waveforms (Continued)
TL/F/10193–21
Conditions: stack not full, IES LOW when initialized
FIGURE 9403A-g. Parallel Load Mode, 4-Bit Word (Unexpanded) or Master in Parallel Expansion
TL/F/10193–22
Conditions: stack not full, device initialized (Note 1) with IES HIGH
FIGURE 9403A-h. Parallel Load, Slave Mode
Note 1: Initialization requires a master reset to occur after power has been applied.
Note 2: TTS normally connected to IRF.
Note 3: If stack is full, IRF will stay LOW.
17
Order Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/10193–23
18
Physical Dimensions inches (millimeters)
28 Terminal Ceramic Leadless Chip Carrier (L)
NS Package Number E28A
24-Lead Ceramic Dual-In-Line Package (D)
NS Package Number J24A
19
Ý
Lit. 103753
Physical Dimensions inches (millimeters) (Continued)
24-Lead Slim (0.300 Wide) Ceramic Dual-In-Line Package (SD)
×
NS Package Number J24F
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