74LVX4245WMX [NSC]
8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs; 8位双电源转换收发器，具有三态输出
| 型号： | 74LVX4245WMX |
| 厂家： | 
National Semiconductor |
| 描述： | 8-Bit Dual Supply Translating Transceiver with TRI-STATE Outputs |
| 文件： | 总8页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
October 1995
74LVX4245
8-Bit Dual Supply Translating Transceiver
with TRI-STATE Outputs
É
General Description
Features
Y
Bidirectional interface between 5V and 3V buses
Control inputs compatible with TTL level
5V data flow at A port and 3V data flow at B port
Outputs source/sink 24 mA at 5V bus; 12 mA at 3V
bus
The LVX4245 is a dual-supply, 8-bit translating transceiver
that is designed to interface between a 5V bus and a 3V bus
in a mixed 3V/5V supply environment. The Transmit/Re-
ceive (T/R) input determines the direction of data flow.
Transmit (active-HIGH) enables data from A ports to B
ports; Receive (active-LOW) enables data from B ports to A
ports. The Output Enable input, when HIGH, disables both A
and B ports by placing them in a HIGH Z condition. The A
port interfaces with the 5V bus; the B port interfaces with
the 3V bus.
Y
Y
Y
Y
Guaranteed simultaneous switching noise level and dy-
namic threshold performance
Y
Y
Available in SOIC, QSOP and TSSOP packages
Implements patented Quiet Series EMI reduction
circuitry
The LVX4245 is suitable for mixed voltage applications such
as laptop computers using 3.3V CPU’s and 5V LCD dis-
plays.
Y
Functionally compatible with the 74 series 245
Logic Symbol
Connection Diagram
Pin Assignment
for SOIC, QSOP and TSSOP
TL/F/11540–1
Pin Names
Description
Output Enable Input
OE
T/R
Transmit/Receive Input
A –A
0
Side A Inputs or TRI-STATE Outputs
Side B Inputs or TRI-STATE Outputs
7
B –B
0
7
TL/F/11540–2
SOIC JEDEC
QSOP
TSSOP
Order Number
74LVX4245WM
74LVX4245WMX
74LVX4245QSC
74LVX4245QSCX
74LVX4245MTC
74LVX4245MTCX
See NS Package Number
M24B
MQA24
MTC24
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/11540
RRD-B30M115/Printed in U. S. A.
Truth Table
Inputs
Outputs
OE
T/R
L
L
L
H
X
Bus B Data to Bus A
Bus A Data to Bus B
HIGH-Z State
H
Logic Diagram
TL/F/11540–6
2
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Recommended Operating
Conditions
Supply Voltage
V
CCA
V
CCB
4.5V to 5.5V
2.7V to 3.6V
b
a
0.5V to 7.0V
Supply Voltage (V , V
CCA CCB
)
@
DC Input Voltage (V ) OE, T/R
b
a
0.5V to V
0.5V
@
Input Voltage (V ) OE, T/R
I
CCA
0V to V
I
CCA
DC Input/Output Voltage (V
@
)
I/O
Input/Output Voltage (V
@
)
I/O
b
b
a
a
A(n)
B(n)
0.5V to V
0.5V to V
0.5V
0.5V
CCA
CCB
A(n)
B(n)
0V to V
0V to V
CCA
CCB
@
@
@
g
DC Input Diode Current (I
IN
)
OE, T/R
20 mA
50 mA
50 mA
Free Air Operating Temperature (T )
A
74LVX
b
a
40 C to 85 C
g
g
DC Output Diode Current (I
)
OK
§
§
8 ns/V
DC Output Source or Sink Current (I
)
O
Minimum Input Edge Rate (Dt/DV)
V
V
from 30% to 70% of V
@
IN
CC
DC V
or Ground Current
CC
3.0V, 4.5V, 5.5V
CC
g
per Output Pin (I or I
CC
and Max Current
)
50 mA
GND
@
g
g
I
I
200 mA
100 mA
CCA
@
CCB
b
a
65 C to 150 C
Storage Temperature Range (T
)
§
§
300 mA
STG
g
DC Latch-Up Source or Sink Current
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
DC Electrical Characteristics
74LVX4245
74LVX4245
e b
a
V
V
CCB
T
40 C
§
§
CCA
A
a
Symbol
Parameter
Units
Conditions
T
A
25 C
§
(V)
(V)
to 85 C
Typ
Guaranteed Limits
s
0.1V or
V
V
V
V
V
V
Minimum
A(n), T/R,
OE
5.5
4.5
3.3
3.3
2.0
2.0
2.0
2.0
V
V
IHA
IHB
ILA
OUT
t
b
High Level
V
0.1V
CC
V
V
Input Voltage
B(n)
5.0
5.0
3.6
2.7
2.0
2.0
2.0
2.0
s
Maximum Low Level
Input Voltage
A(n), T/R,
OE
5.5
4.5
3.3
3.3
0.8
0.8
0.8
0.8
0.1V or
OUT
t
b
V
0.1V
CC
B(n)
5.0
5.0
2.7
3.6
0.8
0.8
0.8
0.8
ILB
e b
Minimum High Level
Output Voltage
4.5
4.5
3.0
3.0
4.5
4.4
4.4
I
I
100 mA
OHA
OHB
OUT
V
V
e b
4.25
3.86
3.76
24 mA
OH
e b
4.5
4.5
4.5
3.0
3.0
2.7
2.99
2.8
2.9
2.4
2.4
2.9
2.4
2.4
I
I
I
100 mA
12 mA
8 mA
OUT
e b
e b
OH
OL
2.5
e
V
V
Maximum Low Level
Output Voltage
4.5
4.5
3.0
3.0
0.002
0.18
0.1
0.1
I
I
100 mA
OLA
OUT
V
V
e
24 mA
0.36
0.44
OL
e
4.5
4.5
4.5
3.0
3.0
2.7
0.002
0.1
0.1
0.1
0.4
0.4
I
I
I
100 mA
12 mA
8 mA
OLB
OUT
e
e
0.31
0.31
OL
OL
0.1
e
I
I
Maximum Input
Leakage Current
V
V
, GND
CCA
IN
I
g
g
g
g
5.5
5.5
3.6
3.6
0.1
0.5
1.0
5.0
mA
mA
@
OE, T/R
e
Maximum TRI-STATE
Output Leakage
V
I
V , V
IL IH
OZA
e
e
OE
V
CCA
V , GND
CCA
@
A(n)
V
O
3
DC Electrical Characteristics (Continued)
74LVX4245
74LVX4245
e b
a
V
V
CCB
T
A
40 C
CCA
§
to 85 C
e a
Symbol
Parameter
Units
Conditions
T
25 C
§
A
(V)
(V)
§
Typ
Guaranteed Limits
e
I
I
Maximum TRI-STATE
Output Leakage
V
V
, V
IL IH
OZB
e
e
g
g
5.0
5.5
3.6
0.5
mA
OE
V
CCA
V , GND
CCB
@
B(n)
V
O
e
b
DI
Maximum I
@
/Input
V
V
2.1V
CC
CCT
I
CCA
5.5
5.5
3.6
3.6
1.0
1.35
0.35
1.5
mA
mA
A(n), T/R, OE
@
Input B(n)
e
b
0.5
80
V
I
V
CCB
0.6V
e
e
I
I
Quiescent V
CCA
A(n)
B(n)
V
V
or GND
or GND,
CCA
CCB
CCA
Supply Current
5.5
5.5
3.6
3.6
8
5
mA
mA
CCB
e
e
GND
OE
GND T/R
e
e
Quiescent V
CCB
A(n)
B(n)
V
V
or GND
or GND,
CCA
Supply Current
50
CCB
e
e
V
OE
GND T/R
CCA
V
V
Quiet Output Maximum
5.0
5.0
3.3
3.3
1.5
0.8
(Notes 1, 2)
(Notes 1, 2)
(Notes 1, 3)
(Notes 1, 3)
OLPA
V
V
V
V
Dynamic V
OL
OLPB
b
b
V
V
Quiet Output Minimum
Dynamic V
5.0
5.0
3.3
3.3
1.2
0.8
OLVA
OLVB
OL
V
V
Minimum High Level
5.0
5.0
3.3
3.3
2.0
IHDA
Dynamic Input Voltage
2.0
IHDB
V
V
Maximum Low Level
5.0
5.0
3.3
3.3
0.8
0.8
ILDA
Dynamic Input Voltage
ILDB
²
Maximum test duration 2.0 ms, one output loaded at a time.
Note 1: Worst case package.
Note 2: Max number of outputs defined as (n). Data inputs are driven 0V to V
level; one output at GND.
CC
b
Note 3: Max number of Data Inputs (n) switching. (n 1) inputs switching 0V to V level. Input-under-test switching: V level to threshold (V ), OV to threshold
CC
CC
IHD
e
(V ), f
ILD
1 MHz.
4
AC Electrical Characteristics
74LVX4245
74LVX4245
74LVX4245
e a
e b
a
e b
T
A
a
T
25 C
T
40 C to 85 C
§
40 C to 85 C
§
§
50 pF
§
§
A
A
e
e
e
C
C
L
50 pF
C
L
50 pF
L
Symbol
Parameters
Units
e
e
e
e
e
e
*V
5V
*V
5V
*V
5V
2.7V
CCA
CCA
CCA
**V
3.3V
**V
3.3V
V
CCB
CCB
CCB
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
A to B
1.0
1.0
5.1
5.3
8.5
8.5
1.0
1.0
9.0
9.0
1.0
1.0
10.0
10.0
PHL
ns
ns
ns
ns
ns
ns
PLH
t
t
Propagation Delay
B to A
1.0
1.0
5.4
5.5
8.5
8.5
1.0
1.0
9.0
9.0
1.0
1.0
10.0
10.0
PHL
PLH
t
t
Output Enable Time
OE to B
1.0
1.0
6.5
6.7
10.0
10.0
1.0
1.0
10.5
10.5
1.0
1.0
11.5
11.5
PZL
PZH
t
t
Output Enable Time
OE to A
1.0
1.0
5.2
5.8
9.0
9.0
1.0
1.0
9.5
9.5
1.0
1.0
10.0
10.0
PZL
PZH
t
t
Output Disable Time
OE to B
1.0
1.0
6.0
3.3
9.5
6.5
1.0
1.0
10.0
7.0
1.0
1.0
10.0
7.5
PHZ
PLZ
t
t
Output Disable Time
OE to A
1.0
1.0
3.9
2.9
7.0
6.5
1.0
1.0
7.5
7.0
1.0
1.0
7.5
7.5
PHZ
PLZ
t
t
Output to Output
Skew***
Data to Output
OSHL
1.0
1.5
1.5
1.5
ns
OSLH
g
*Voltage Range 5.0V is 5.0V 0.5V.
g
**Voltage Range 3.3V is 3.3V 0.3V.
***Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The
specification applies to any outputs switching in the same direction, either HIGH to LOW (t
design.
)
or LOW to HIGH (t
). Parameter guaranteed by
OSLH
OSHL
Capacitance
Symbol
Parameter
Typ
Units
Conditions
e
Open
C
C
Input Capacitance
4.5
pF
V
IN
CC
e
Input/Output
Capacitance
V
V
5.0V
3.3V
I/O
CCA
15
pF
e
e
e
CCB
C
PD
Power Dissipation
Capacitance
B
A
x
x
A
B
55
40
pF
pF
V
V
5.0V
3.3V
CCA
CCB
C
is measured at 10 MHz
PD
8-Bit Dual Supply Translating Transceiver
The LVX4245 is a dual supply device capable of bidirection-
al signal translation. This level shifting ability provides an
efficient interface between low voltage CPU local bus with
memory and a standard bus defined by 5V I/O levels. The
device control inputs can be controlled by either the low
voltage CPU and core logic or a bus arbitrator with 5V I/O
levels.
Manufactured on
a sub-micron CMOS process, the
LVX4245 is ideal for mixed voltage applications such as
notebook computers using 3.3V CPU’s and 5V peripheral
devices.
TL/F/11540–3
5
Applications: Mixed Mode Dual Supply Interface Solution
LVX4245 is designed to solve 3V/5V interfacing issues
when CMOS devices cannot tolerate I/O levels above their
This device is also configured as an 8-bit 245 transceiver,
giving the designer TRI-STATE capabilities and the ability to
select either bidirectional or unidirectional modes. Since the
center 20 pins are also pin compatible to 74 series 245, as
shown in Figure 2, the designer could use this device in
either a 3V system or a 5V system without any further work
to re-layout the board.
applied V . If an I/O pin of 3V ICs is driven by 5V ICs, the
CC
P-Channel transistor in 3V ICs will conduct causing current
flow from I/O bus to the 3V power supply. The resulting high
current flow can cause destruction of 3V ICs through latch-
up effects. To prevent this problem, a current limiting resis-
tor is used typically under direct connection of 3V ICs and
5V ICs, but it causes speed degradation.
In a better solution, the LVX4245 configures two different
output levels to handle the dual supply interface issues. The
‘‘A’’ port is a dedicated 5V port to interface 5V ICs. The ‘‘B’’
port is a dedicated port to interface 3V ICs. Figure 1 shows
how LVX4245 fits into a system with 3V subsystem and 5V
subsystem.
TL/F/11540–4
FIGURE 2. LVX4245 Pin Arrangment is Compatible to
20-Pin 74 Series 245
TL/F/11540–5
FIGURE 1. LVX4245 Fits into a System with 3V Subsystem and 5V Subsystem
6
74LVX4245 Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
74LVX 4245 MW
X
Temperature Range Family
e
Special Variations
e
e
74
Commercial
‘‘X’’
‘‘ ’’
Tape and Reel
Rail/Tube
Device Type
Package Code
e
WM
Small Outline JEDEC
SOIC (0.300 Wide)
Molded Shrink Small Outline Package, JEDEC
(also known as QSOP)
×
e
QSC
inches
Physical Dimensions
millimeters
24-Lead (0.300 Wide) Small Outline Package (WM)
×
Order Number 74LVX4245WM or 74LVX4245WMX
NS Package Number M24B
7
Physical Dimensions inches (Continued)
24-Lead, Molded Shrink Small Outline Package, JEDEC (QSC)
(also known as: QSOP)
Order Number 74LVX4245QSC or 74LVX4245QSCX
NS Package Number MQA24
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
SEMICONDUCTOR CORPORATION. As used herein:
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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