74LS174 [NSC]
Hex/Quad D Flip-Flops with Clear; 六/四路D触发器与Clear
| 型号： | 74LS174 |
| 厂家： | 
National Semiconductor |
| 描述： | Hex/Quad D Flip-Flops with Clear |
| 文件： | 总8页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
54LS174/DM54LS174/DM74LS174,
54LS175/DM54LS175/DM74LS175
Hex/Quad D Flip-Flops with Clear
General Description
Features
Y
Y
Y
Y
Y
LS174 contains six flip-flops with single-rail outputs
These positive-edge-triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input, and the quad (175) versions feature complementary
outputs from each flip-flop.
LS175 contains four flip-flops with double-rail outputs
Buffered clock and direct clear inputs
Individual data input to each flip-flop
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
Information at the D inputs meeting the setup time require-
ments is transferred to the Q outputs on the positive-going
edge of the clock pulse. Clock triggering occurs at a particu-
lar voltage level and is not directly related to the transition
time of the positive-going pulse. When the clock input is at
either the high or low level, the D input signal has no effect
at the output.
Y
Y
Y
Typical clock frequency 40 MHz
Typical power dissipation per flip-flop 14 mW
Alternate
Military/Aerospace
device
(54LS174,
54LS175) is available. Contact a National Semiconduc-
tor Sales Office/Distributor for specifications.
Connection Diagrams
Dual-In-Line Package
Dual-In-Line Package
TL/F/6404–1
Order Number 54LS174DMQB, 54LS174FMQB,
54LS174LMQB, DM54LS174J,
TL/F/6404–2
Order Number 54LS175DMQB, 54LS175FMQB,
54LS175LMQB, DM54LS175J
DM54LS174W, DM74LS174M or DM74LS174N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
DM54LS175W, DM74LS175M or DM74LS175N
See NS Package Number E20A, J16A,
M16A, N16E or W16A
Function Table (Each Flip-Flop)
e
H
L
High Level (steady state)
Low Level (steady state)
Don’t Care
Inputs
Clock
Outputs
e
e
²
Q
Clear
D
Q
X
e
Transition from low to high level
u
0
L
H
H
H
X
u
u
L
X
H
L
L
H
L
H
e
Q
The level of Q before the indicated steady-state input conditions were
established.
L
H
e
²
LS175 only
X
Q
Q
0
0
C
1995 National Semiconductor Corporation
TL/F/6404
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
DM54LS and 54LS
DM74LS
b
b
a
a
55 C to 125 C
§
§
0 C to 70 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54LS174
DM74LS174
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
MHz
MHz
OH
OL
4
8
f
f
t
0
0
30
25
0
0
30
25
CLK
CLK
W
Pulse Width
(Note 6)
Clock
Clear
20
20
20
0
20
20
20
0
ns
t
t
t
Data Setup Time (Note 6)
Data Hold Time (Note 6)
ns
ns
ns
SU
H
Clear Release Time (Note 6)
Free Air Operating Temperature
25
25
0
REL
b
T
A
55
125
70
C
§
’LS174 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
(Note 3)
Symbol
Parameter
Conditions
Min
Max
Units
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
DM54
DM74
DM54
DM74
DM74
2.5
2.7
3.4
3.4
OH
CC
OH
e
e
Max, V
IL
IH
e
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
Min
0.25
0.35
0.25
0.4
CC
OL
e
Max, V
IH
IL
0.5
0.4
V
e
e
I
4 mA, V
CC
Min
OL
@
Input Current Max
Input Voltage
e
e
I
V
Max, V
7V
I
CC
I
0.1
mA
e
e
e
I
I
High Level Input Current
V
Max, V
Max
2.7V
20
mA
IH
IL
CC
CC
e
I
b
Low Level Input
Current
V
V
Clock
Clear
Data
0.4
0.4
0.4V
I
b
mA
b
0.36
e
(Note 4)
b
b
b
I
I
Short Circuit
Output Current
V
CC
Max
DM54
DM74
20
20
100
100
OS
CC
mA
mA
b
e
Supply Current
V
CC
Max (Note 5)
16
26
e
e
e
e
e
e
e
5V.
Note 1: C
15 pF, R
50 pF, R
2 kX, T
2 kX, T
25 C and V
§
25 C and V
§
L
L
L
L
A
A
CC
CC
e
Note 2: C
5V.
e
e
Note 3: All typicals are at V
CC
5V, T
25 C.
§
A
Note 4: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 5: With all outputs open and 4.5V applied to all data and clear inputs, I is measured after a momentary ground, then 4.5V applied to the clock.
CC
e
e
5V.
Note 6: T
25 C and V
§
A
CC
2
’LS174 Switching Characteristics
e
e
at V
5V and T
25 C (See Section 1 for Test Waveforms and Output Load)
§
CC
A
e
R
L
2 kX
From (Input)
e
e
L
Symbol
Parameter
C
Min
30
15 pF
C
50 pF
Max
Units
To (Output)
L
Max
Min
f
t
Maximum Clock Frequency
25
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock to
Output
PLH
30
30
35
32
36
42
t
t
Propagation Delay Time
High to Low Level Output
Clock to
Output
PHL
PHL
ns
ns
Propagation Delay Time
High to Low Level Output
Clear to
Output
Recommended Operating Conditions
DM54LS175
DM74LS175
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
MHz
MHz
OH
OL
4
8
f
f
t
0
0
30
25
0
0
30
25
CLK
CLK
W
Pulse Width
(Note 3)
Clock
Clear
20
20
20
0
20
20
20
0
ns
t
t
t
Data Setup Time (Note 3)
Data Hold Time (Note 3)
ns
ns
ns
SU
H
Clear Release Time (Note 3)
Free Air Operating Temperature
25
25
0
REL
b
T
A
55
125
70
C
§
e
e
e
e
e
e
e
e
e
Note 1: C
Note 2: C
Note 3: T
15 pF, R
50 pF, R
2 kX, T
2 kX, T
25 C and V
§
5V.
5V.
L
L
L
A
A
CC
CC
25 C and V
§
L
e
CC
25 C and V
§
5V.
A
3
’LS175 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
DM54
DM74
DM54
DM74
DM74
2.5
2.7
3.4
3.4
OH
CC
OH
e
e
Max, V
IL
IH
e
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
Min
0.25
0.35
0.25
0.4
CC
OL
e
Max, V
IH
IL
0.5
0.4
V
e
e
I
4 mA, V
CC
Min
OL
@
Input Current Max
e
e
I
V
Max, V
7V
I
CC
I
0.1
20
mA
Input Voltage
e
e
e
I
I
High Level Input Current
V
Max, V
Max
2.7V
mA
IH
IL
CC
CC
I
b
Low Level Input
Current
V
V
Clock
Clear
Data
0.4
0.4
e
0.4V
I
b
mA
b
0.36
e
(Note 2)
b
b
b
b
I
I
Short Circuit
V
CC
Max
DM54
DM74
20
20
100
100
OS
CC
mA
mA
Output Current
e
Supply Current
V
CC
Max (Note 3)
11
18
’LS175 Switching Characteristics
e
e
at V
5V and T
25 C (See Section 1 for Test Waveforms and Output Load)
§
CC
A
e
R
L
2 kX
From (Input)
e
e
50 pF
Symbol
Parameter
C
Min
30
15 pF
C
Min
25
Units
To (Output)
L
L
Max
Max
f
t
Maximum Clock Frequency
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock to
Q or Q
PLH
30
30
25
35
32
36
29
42
t
t
t
Propagation Delay Time
High to Low Level Output
Clock to
Q or Q
PHL
PLH
PHL
ns
ns
ns
Propagation Delay Time
Low to High Level Output
Clear to
Q
Propagation Delay Time
High to Low Level Output
Clear to
Q
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
Note 3: With all outputs open and 4.5V applied to all data and clear inputs, I is measured after a momentary ground, then 4.5V applied to the clock input.
A
CC
4
Logic Diagrams
LS174
LS175
TL/F/6404–4
TL/F/6404–3
5
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier (E)
Order Number 54LS174LMQB or 54LS175LMQB
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
Order Number DM54LS174DMQB, 54LS175DMQB, DM54LS174J or DM54LS175J
NS Package Number J16A
6
Physical Dimensions inches (millimeters) (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS174M or DM74LS175M
NS Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS174N or DM74LS175N
NS Package Number N16E
7
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Number 54LS174FMQB, 54LS175FMQB, DM54LS174W or DM54LS175W
NS Package Number W16A
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systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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相关型号：
74LS174B
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 6-Bit, True Output, TTL, PDIP16, DIP-16
NXP
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