74AC378LCQB [NSC]

Parallel D Register with Enable; 并行D寄存器使能
74AC378LCQB
型号: 74AC378LCQB
厂家: National Semiconductor    National Semiconductor
描述:

Parallel D Register with Enable
并行D寄存器使能

文件: 总8页 (文件大小:169K)
中文:  中文翻译
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March 1993  
54AC/74AC378  
Parallel D Register with Enable  
General Description  
The ’AC378 is a 6-bit register with a buffered common En-  
able. This device is similar to the ’AC174, but with common  
Enable rather than common Master Reset.  
Features  
Y
Y
Y
Y
Y
6-bit high-speed parallel register  
Positive edge-triggered D-type inputs  
Fully buffered common clock and enable inputs  
Input clamp diodes limit high-speed termination effects  
Standard Military Drawing (SMD)  
Ð ’AC378: 5962-91605  
Logic Symbols  
Connection Diagrams  
Pin Assignment for  
DIP, SOIC and Flatpak  
Pin Assignment  
for LCC  
TL/F/10231–1  
TL/F/10231–3  
IEEE/IEC  
TL/F/10231–2  
TL/F/10231–4  
Pin Names  
Description  
E
Enable Input (Active LOW)  
Data Inputs  
D D  
0
5
CP  
Clock Pulse Input (Active Rising Edge)  
Outputs  
Q Q  
0
5
FACTTM is a trademark of National Semiconductor Corporation.  
C
1995 National Semiconductor Corporation  
TL/F/10231  
RRD-B30M75/Printed in U. S. A.  
Functional Description  
Truth Table  
The ’AC378 consists of six edge-triggered D-type flip-flops  
with individual D inputs and Q inputs. The Clock (CP) and  
Enable (E) inputs are common to all flip-flops.  
Inputs  
Output  
E
CP  
D
Q
n
n
When the E input is LOW, new data is entered into the  
register on the LOW-to-HIGH transition of the CP input.  
When the E input is HIGH the register will retain the present  
data independent of the CP input.  
H
L
L
L
L
L
X
No Change  
H
L
H
L
e
e
e
H
L
HIGH Voltage Level  
LOW Voltage Level  
Immaterial  
X
e
L
LOW-to-HIGH Clock Transition  
Logic Diagram  
TL/F/10231–5  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
2
Absolute Maximum Ratings (Note 1)  
If Military/Aerospace specified devices are required,  
please contact the National Semiconductor Sales  
Office/Distributors for availability and specifications.  
Recommended Operating  
Conditions  
Supply Voltage (V  
’AC  
)
CC  
2.0V to 6.0V  
b
a
0.5V to 7.0V  
Supply Voltage (V  
)
CC  
Input Voltage (V )  
I
0V to V  
0V to V  
CC  
DC Input Diode Current (I  
)
IK  
Output Voltage (V  
)
O
CC  
e b  
b
a
V
I
V
I
0.5V  
a
20 mA  
20 mA  
Operating Temperature (T )  
A
e
V
CC  
0.5V  
b
b
a
40 C to 85 C  
74AC  
54AC  
§
55 C to 125 C  
§
§
b
b
a
0.5V  
DC Input Voltage (V )  
I
0.5V to V  
0.5V to V  
CC  
a
§
DC Output Diode Current (I  
)
OK  
Minimum Input Edge Rate (DV/Dt)  
’AC Devices  
e b  
b
a
V
V
0.5V  
a
20 mA  
20 mA  
O
O
e
V
CC  
0.5V  
V
V
from 30% to 70% of V  
@
IN  
CC  
a
DC Output Voltage (V  
DC Output Source  
)
O
0.5V  
50 mA  
50 mA  
CC  
3.3V, 4.5V, 5.5V  
125 mV/ns  
CC  
g
g
or Sink Current (I  
)
O
DC V  
or Ground Current  
CC  
per Output Pin (I or I  
CC  
)
GND  
)
b
a
65 C to 150 C  
Storage Temperature (T  
§
§
STG  
Junction Temperature (T )  
J
CDIP  
PDIP  
175 C  
§
140 C  
§
Note 1: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, without  
exception, to ensure that the system design is reliable over its power supply,  
temperature, and output/input loading variables. National does not recom-  
mend operation of FACTTM circuits outside databook specifications.  
DC Characteristics for ’AC Family Devices  
74AC  
54AC  
74AC  
e
a
e
T
A
V
CC  
(V)  
T
A
55 C to 125 C  
e a  
Symbol  
Parameter  
T
25 C  
§
Units  
Conditions  
A
b
b a  
40 C to 85 C  
§
§
Guaranteed Limits  
§
§
Typ  
e
0.1V  
V
V
V
Minimum High Level  
Input Voltage  
3.0  
4.5  
5.5  
1.5  
2.1  
2.1  
2.1  
V
IH  
OUT  
b
2.25  
2.75  
3.15  
3.85  
3.15  
3.85  
3.15  
3.85  
V
V
V
or V  
CC  
0.1V  
e
Maximum Low Level  
Input Voltage  
3.0  
4.5  
5.5  
1.5  
0.9  
0.9  
0.9  
V
OUT  
0.1V  
IL  
b
2.25  
2.75  
1.35  
1.65  
1.35  
1.65  
1.35  
1.65  
or V  
CC  
0.1V  
e b  
OUT  
Minimum High Level  
Output Voltage  
3.0  
4.5  
5.5  
2.99  
4.49  
5.49  
2.9  
4.4  
5.4  
2.9  
4.4  
5.4  
2.9  
4.4  
5.4  
I
50 mA  
OH  
e
*V  
IN  
V
or V  
IH  
12 mA  
IL  
b
b
b
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
2.4  
3.7  
4.7  
2.46  
3.76  
4.76  
V
V
I
24 mA  
24 mA  
OH  
e
e
V
OL  
Maximum Low Level  
Output Voltage  
3.0  
4.5  
5.5  
0.002  
0.001  
0.001  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
0.1  
I
50 mA  
OUT  
*V  
IN  
V or V  
IL IH  
3.0  
4.5  
5.5  
0.36  
0.36  
0.36  
0.5  
0.5  
0.5  
0.44  
0.44  
0.44  
12 mA  
V
I
24 mA  
24 mA  
OL  
e
I
Maximum Input  
Leakage Current  
V
I
V , GND  
CC  
IN  
g
g
g
1.0  
5.5  
0.1  
1.0  
mA  
*All outputs loaded; thresholds on input associated with output under test.  
3
DC Characteristics for ’AC Family Devices (Continued)  
74AC  
54AC  
74AC  
e
25 C  
§
e
a
e
T
A
V
CC  
(V)  
T
a
T
A
A
55 C to 125 C  
Symbol  
Parameter  
Units  
Conditions  
b
b a  
40 C to 85 C  
§
§
Guaranteed Limits  
§
§
Typ  
e
²
I
I
I
Minimum Dynamic  
5.5  
5.5  
50  
75  
mA  
mA  
V
V
V
1.65V Max  
OLD  
OHD  
CC  
OLD  
Output Current  
b
b
e
3.85V Min  
OHD  
50  
75  
e
Maximum Quiescent  
Supply Current  
V
CC  
IN  
5.5  
4.0  
80.0  
40.0  
mA  
or GND  
²
Maximum test duration 2.0 ms, one output loaded at a time.  
@
@
3.0V are guaranteed to be less than or equal to the respective limit 5.5V V  
Note: I and I  
IN  
.
CC  
CC  
@ @  
for 54AC 25 C is identical to 74AC 25 C.  
§ §  
I
CC  
AC Electrical Characteristics  
74AC  
54AC  
e b  
74AC  
e b  
T
55 C  
T
A
40 C  
§
§
A
e a  
A
V
CC  
(V)  
*
T
25 C  
§
50 pF  
a
a
Symbol  
Parameter  
to 125 C  
to 85 C  
Units  
§
50 pF  
§
50 pF  
e
C
L
e
e
C
C
L
L
Min  
Typ  
Max  
Min  
Max  
Min  
Max  
f
t
t
Maximum Clock  
Frequency  
3.3  
5.0  
125  
160  
160  
200  
95  
95  
110  
145  
max  
PLH  
PHL  
MHz  
ns  
Propagation Delay  
3.3  
5.0  
2.5  
1.5  
8.5  
6.0  
11.0  
8.0  
1.5  
1.5  
12.0  
9.0  
2.5  
1.5  
12.5  
9.0  
CP to Q  
n
Propagation Delay  
CP to Q  
3.3  
5.0  
2.5  
1.5  
8.0  
5.5  
10.5  
7.5  
1.5  
1.5  
12.0  
9.0  
2.5  
1.5  
11.0  
8.0  
ns  
n
g
*Voltage Range 3.3 is 3.3V 0.3V  
g
Voltage Range 5.0 is 5.0V 0.5V  
AC Operating Requirements  
74AC  
54AC  
74AC  
e b  
e b  
A
a
T
55 C  
T
40 C  
§
to 125 C  
§
to 85 C  
A
e a  
A
V *  
CC  
(V)  
T
25 C  
§
50 pF  
a
Symbol  
Parameter  
Units  
§
50 pF  
§
e
C
L
e
e
50 pF  
C
C
L
L
Typ  
Guaranteed Minimum  
t
t
t
t
t
Setup Time, HIGH or LOW  
3.3  
5.0  
1.5  
1.0  
3.0  
4.0  
4.0  
3.5  
s
ns  
ns  
ns  
ns  
ns  
D
to CP  
2.0  
2.5  
n
Hold Time, HIGH or LOW  
to CP  
3.3  
5.0  
1.0  
1.0  
2.0  
2.0  
4.0  
4.0  
2.0  
2.0  
h
s
D
n
Setup Time, HIGH or  
LOW, E to CP  
3.3  
5.0  
0
0
2.0  
2.0  
2.5  
2.5  
2.0  
2.0  
Hold Time, HIGH or  
LOW, E to CP  
3.3  
5.0  
1.0  
1.0  
2.0  
2.0  
4.0  
4.0  
2.0  
2.0  
h
w
CP Pulse Width  
HIGH or LOW  
3.3  
5.0  
3.0  
2.0  
4.5  
3.5  
6.5  
6.5  
5.5  
4.0  
g
*Voltage Range 3.3 is 3.3V 0.3V  
g
Voltage Range 5.0 is 5.0V 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation Capacitance  
Typ  
4.5  
28  
Units  
pF  
Conditions  
e
OPEN  
C
C
V
CC  
IN  
e
5.0V  
pF  
V
CC  
PD  
4
Ordering Information  
The device number is used to form part of a simplified purchasing code where a package type and temperature range are  
defined as follows:  
74AC 378  
P
C
QR  
Temperature Range Family  
e
Special Variations  
e
e
74AC Commercial  
X
QR  
Devices shipped in 13 reels  
×
Commercial grade device with  
burn-in  
e
54AC Military  
Device Type  
Package Code  
e
QB  
Military grade with environmental  
and burn-in processing shipped  
in tubes  
e
e
e
e
e
P
D
F
L
Plastic DIP  
Ceramic DIP  
Flatpak  
Leadless Ceramic Chip Carrier (LCC)  
Small Outline (SOIC)  
Temperature Range  
e
e
b a  
C
M
Commercial ( 40 C to 85 C)  
§
§
b a  
Military ( 55 C to 125 C)  
§
§
S
5
Physical Dimensions inches (millimeters)  
20-Terminal Ceramic Leadless Chip Carrier (L)  
NS Package Number E20A  
16-Lead Ceramic Dual-In-Line Package (D)  
NS Package Number J16A  
6
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Small Outline Integrated Circuit (S)  
NS Package Number M16A  
16-Lead Plastic Dual-In-Line Package (P)  
NS Package Number N16E  
7
Ý
Lit. 114805  
Physical Dimensions inches (millimeters) (Continued)  
16-Lead Ceramic Flatpak (F)  
NS Package Number W16A  
LIFE SUPPORT POLICY  
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or  
systems which, (a) are intended for surgical implant  
into the body, or (b) support or sustain life, and whose  
failure to perform, when properly used in accordance  
with instructions for use provided in the labeling, can  
be reasonably expected to result in a significant injury  
to the user.  
2. A critical component is any component of a life  
support device or system whose failure to perform can  
be reasonably expected to cause the failure of the life  
support device or system, or to affect its safety or  
effectiveness.  
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