74ABT373CLCX [NSC]
Octal Transparent Latch with TRI-STATE Outputs; 八路透明锁存器具有三态输出
| 型号： | 74ABT373CLCX |
| 厂家： | 
National Semiconductor |
| 描述： | Octal Transparent Latch with TRI-STATE Outputs |
| 文件： | 总16页 (文件大小：331K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
September 1995
54ABT/74ABT373
Octal Transparent Latch with TRI-STATE Outputs
É
Guaranteed output skew
Y
General Description
The ’ABT373 consists of eight latches with TRI-STATE out-
Y
Guaranteed multiple output switching specifications
Y
Output switching specified for both 50 pF and 250 pF
puts for bus organized system applications. The flip-flops
loads
appear transparent to the data when Latch Enable (LE) is
HIGH. When LE is LOW, the data that meets the setup
times is latched. Data appears on the bus when the Output
Enable (OE) is LOW. When OE is HIGH the bus output is in
the high impedance state.
Y
Guaranteed simultaneous switching, noise level and
dynamic threshold performance
Y
Guaranteed latchup protection
Y
High impedance glitch free bus loading during entire
power up and power down
Y
Y
Nondestructive hot insertion capability
Features
Y
Standard Military Drawing (SMD) 5962-9321801
TRI-STATE outputs for bus interfacing
Y
Output sink capability of 64 mA, source capability of
32 mA
Package
Commercial
Military
Package Description
Number
M20B
M20D
N20B
74ABT373CSC (Note 1)
74ABT373CSJ (Note 1)
74ABT373CPC
20-Lead (0.300 Wide) Molded Small Outline, JEDEC
×
20-Lead (0.300 Wide) Molded Small Outline, EIAJ
×
20-Lead (0.300 Wide) Molded Dual-In-Line
×
54ABT373J/883
J20A
20-Lead Ceramic Dual-In-Line
74ABT373CMSA (Note 1)
MSA20 20-Lead Molded Shrink Small Outline, EIAJ Type II
54ABT373W/883 W20A
54ABT373E/883 E20A
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
74ABT373CMTC (Notes 1, 2)
MTC20 20-Lead Molded Thin Shrink Small Outline, JEDEC
e
Note 1: Devices also available in 13 reel. Use suffix
×
Note 2: Contact factory for package availability.
SCX, SJX, MSAX, and MTCX.
Connection Diagrams
Pin Assignment
for DIP, SOIC, SSOP and Flatpak
Pin Assignment
for LCC
Pin Names
Description
Data Inputs
D –D
0
7
LE
Latch Enable Input
(Active HIGH)
OE
Output Enable Input
(Active LOW)
O –O
0
TRI-STATE Latch
Outputs
7
TL/F/11547–2
TL/F/11547–1
TRI-STATEÉ is a registered trademark of National Semiconductor Corporation.
C
1995 National Semiconductor Corporation
TL/F/11547
RRD-B30M115/Printed in U. S. A.
Functional Description
The ’ABT373 contains eight D-type latches with
Truth Table
Inputs
Output
TRI-STATE output buffers. When the Latch Enable (LE) in-
put is HIGH, data on the D inputs enters the latches. In this
n
LE
OE
D
n
O
n
condition the latches are transparent, i.e., a latch output will
change state each time its D input changes. When LE is
LOW, the latches store the information that was present on
the D inputs a setup time preceding the HIGH-to-LOW tran-
sition of LE. The TRI-STATE buffers are controlled by the
Output Enable (OE) input. When OE is LOW, the buffers are
in the bi-state mode. When OE is HIGH the buffers are in
the high impedance mode but this does not interfere with
entering new data into the latches.
H
H
L
L
L
H
H
L
X
X
L
L
O
(no change)
Z
n
X
H
e
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
Immaterial
X
Z
High Impedance State
Logic Diagram
TL/F/11547–3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
2
Absolute Maximum Ratings (Note 1)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
b
b
DC Latchup Source Current: OE Pin
(Across Comm Operating Range) Other Pins
150 mA
500 mA
Over Voltage Latchup (I/O)
10V
b
b
a
65 C to 150 C
Storage Temperature
Note 1: Absolute maximum ratings are values beyond which the device may
be damaged or have its useful life impaired. Functional operation under
these conditions is not implied.
§
§
a
55 C to 125 C
Ambient Temperature under Bias
§
§
Junction Temperature under Bias
Ceramic
Plastic
Note 2: Either voltage limit or current limit is sufficient to protect inputs.
b
b
a
55 C to 175 C
§
§
a
55 C to 150 C
§
§
Recommended Operating
Conditions
V
Pin Potential to
CC
Ground Pin
b
a
0.5V to 7.0V
Free Air Ambient Temperature
Military
Commercial
Supply Voltage
Military
Commercial
Minimum Input Edge Rate
Data Input
b
a
0.5V to 7.0V
Input Voltage (Note 2)
Input Current (Note 2)
b
a
55 C to 125 C
§
40 C to 85 C
§
§
b
a
30 mA to 5.0 mA
b a
§
Voltage Applied to Any Output
in the Disabled or
Power-Off State
a
a
a
4.5V to 5.5V
a
b
a
0.5V to 5.5V
4.5V to 5.5V
b
in the HIGH State
0.5V to V
CC
(DV/Dt)
50 mV/ns
20 mV/ns
Current Applied to Output
in LOW State (Max)
Enable Input
twice the rated I (mA)
OL
DC Electrical Characteristics
ABT373
Typ
Symbol
Parameter
Units
V
CC
Conditions
Min
Max
V
V
V
V
Input HIGH Voltage
2.0
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
IH
Input LOW Voltage
0.8
IL
b
e b
18 mA
Input Clamp Diode Voltage
Output HIGH Voltage
1.2
Min
Min
I
CD
OH
IN
e b
e b
e b
54ABT/74ABT
54ABT
74ABT
2.5
2.0
2.0
I
I
I
3 mA
24 mA
32 mA
OH
OH
OH
V
V
e
e
V
OL
Output LOW Voltage
Input HIGH Current
54ABT
74ABT
0.55
0.55
I
I
48 mA
64 mA
OL
OL
Min
e
e
I
5
5
V
IN
V
IN
2.7V (Note 2)
V
IH
mA
mA
mA
Max
Max
Max
CC
e
I
I
Input HIGH Current Breakdown Test
Input LOW Current
7
V
IN
7.0V
BVI
IL
b
b
e
e
5
5
V
IN
V
IN
0.5V (Note 2)
0.0V
e
ID
V
ID
Input Leakage Test
I
All Other Pins Grounded
1.9 mA
4.75
V
0.0
b
e
e
e
e
e
e
e
I
I
I
I
I
I
I
I
Output Leakage Current
Output Leakage Current
Output Short-Circuit Current
Output High Leakage Current
Bus Drainage Test
50
mA
mA
0
0
5.5V
5.5V
V
V
V
V
V
2.7V; OE
0.5V; OE
0.0V
2.0V
2.0V
OZH
OZL
OS
OUT
OUT
OUT
OUT
OUT
b
b
50
b
b
275 mA
100
Max
50
mA
mA
mA
mA
Max
0.0
V
CC
CEX
ZZ
100
50
5.5V; All Others GND
Power Supply Current
Power Supply Current
Power Supply Current
Max
Max
All Outputs HIGH
All Outputs LOW
CCH
CCL
CCZ
30
e
OE
V
CC
50
mA
Max
All Others at V or GND
CC
2.1V
e
V
b
I
Additional I /Input
CC
Outputs Enabled
Outputs TRI-STATE
Outputs TRI-STATE
2.5
2.5
2.5
mA
mA
mA
V
I
CCT
CC
e
b
2.1V
2.1V
Enable Input V
Data Input V
V
I
CC
b
Max
e
V
I
CC
All Others at V or GND
CC
e
Outputs Open, LE
GND, (Note 1)
I
Dynamic I
(Note 2)
No Load
V
CC
CCD
CC
mA/
MHz
e
One Bit Toggling, 50% Duty Cycle
0.12
OE
Max
k
Note 1: For 8 bits toggling, I
0.8 mA/MHz.
CCD
Note 2: Guaranteed, but not tested.
3
DC Electrical Characteristics (SOIC Package) (Continued)
Conditions
Symbol
Parameter
Min
Typ
Max
Units
V
CC
e
e
500X
C
L
50 pF, R
L
e
e
e
e
e
V
Quiet Output Maximum Dynamic V
Quiet Output Minimum Dynamic V
0.4
0.8
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
25 C (Note 1)
§
25 C (Note 1)
OLP
OL
A
A
A
A
A
b
b
0.8
3.0
V
1.2
2.5
2.0
T
§
25 C (Note 3)
OLV
OL
V
Minimum High Level Dynamic Output Voltage
T
T
T
§
25 C (Note 2)
OHV
V
Minimum High Level Dynamic Input Voltage
Maximum Low Level Dynamic Input Voltage
1.7
0.9
§
25 C (Note 2)
IHD
V
0.6
§
ILD
b
Note 1: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output at Low. Guaranteed, but not tested.
b
Note 2: Max number of data inputs (n) switching. n
1 inputs switching 0V to 3V. Input-under-test switching: 3V to theshold (V ), 0V to threshold (V ).
ILD IHD
Guaranteed, but not tested.
b
Note 3: Max number of outputs defined as (n). n
1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
AC Electrical Characteristics
74ABT
54ABT
74ABT
e a
e b
a
55 C to 125 C
4.5V to 5.5V
e b a
40 C to 85 C
T
25 C
§
T
T
A
§
§
§
4.5V to 5.5V
§
A
A
e a
5.0V
50 pF
e
e
Symbol
Parameter
Units
V
V
V
CC
CC
CC
e
e
e
C 50 pF
L
C
C
L
50 pF
L
Min
Typ
Max
Min
Max
Min
Max
t
t
Propagation Delay
1.9
1.9
2.7
2.8
4.5
4.5
1.0
1.0
6.8
7.0
1.9
1.9
4.5
4.5
PLH
PHL
ns
ns
ns
ns
D
n
to O
n
t
t
Propagation Delay
LE to O
2.0
2.0
3.1
3.0
5.0
5.0
1.0
1.5
7.7
7.7
2.0
2.0
5.0
5.0
PLH
PHL
n
t
t
Output Enable Time
1.5
1.5
3.1
3.1
5.3
5.3
1.0
1.5
6.7
7.2
1.5
1.5
5.3
5.3
PZH
PZL
t
t
Output Disable Time
2.0
2.0
3.6
3.4
5.4
5.4
1.7
1.0
8.0
7.0
2.0
2.0
5.4
5.4
PHZ
PLZ
AC Operating Requirements
74ABT
54ABT
74ABT
e a
e b
a
55 C to 125 C
4.5V to 5.5V
e b a
40 C to 85 C
T
25 C
T
T
A
§
5.0V
§
§
§
4.5V to 5.5V
§
A
A
e a
e
e
Symbol
Parameter
Units
V
V
V
CC
CC
CC
e
e
e
C 50 pF
L
C
50 pF
C
L
50 pF
L
Min
Typ
100
Max
Min
Max
Min
Max
f
Max Toggle
100
toggle
MHz
ns
Frequency
t (H)
s
Setup Time, HIGH
1.5
1.5
2.5
2.5
1.5
1.5
t (L)
s
or LOW D to LE
n
t (H)
h
Hold Time, HIGH
1.0
1.0
2.5
2.5
1.0
1.0
ns
t (L)
h
or LOW D to LE
n
t (H)
w
Pulse Width,
LE HIGH
3.0
3.3
3.0
ns
4
Extended AC Electrical Characteristics
(SOIC package)
74ABT
74ABT
74ABT
e b
a
40 C to 85 C
e b a
40 C to 85 C
T
T
§
4.5V to 5.5V
§
§
4.5V to 5.5V
§
A
A
e b
a
40 C to 85 C
T
§
§
4.5V to 5.5V
A
e
e
V
V
CC
CC
e
V
CC
e
e
250 pF
Symbol
Parameter
C
50 pF
C
L
Units
L
e
C
250 pF
(Note 5)
L
8 Outputs Switching
(Note 4)
8 Outputs Switching
(Note 6)
Min
Max
Min
Max
Min
Max
t
t
Propagation Delay
1.5
1.5
5.2
5.2
2.0
2.0
6.8
6.8
2.0
2.0
9.0
9.0
PLH
ns
ns
ns
ns
D
n
to O
n
PHL
t
t
Propagation Delay
LE to O
1.5
1.5
5.5
5.5
2.0
2.0
7.5
7.5
2.0
2.0
9.5
9.5
PLH
PHL
n
t
t
Output Enable Time
1.5
1.5
6.2
6.2
2.0
2.0
8.0
8.0
2.0
2.0
10.5
10.5
PZH
PZL
t
t
Output Disable Time
1.0
1.0
5.5
5.5
PHZ
(Note 7)
(Note 7)
PZL
Note 4: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.).
Note 5: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in plce of the 50 pF load capacitors in
the standard AC load. This specificaiton pertains to single output switching only.
Note 6: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 7: The TRI-STATE delay times are dominated by the RC network (500X, 250 pF) on the output and has been excluded from the datasheet.
Skew
74ABT
74ABT
e b
a
40 C to 85 C
e b
A
a
40 C to 85 C
T
T
§
4.5V–5.5V
§
§
4.5V–5.5V
§
A
e
e
V
CC
V
CC
C
Symbol
Parameter
e
e
250 pF
Units
C
50 pF
L
L
8 Outputs Switching
(Note 3)
8 Outputs Switching
(Note 4)
Max
Max
t
Pin to Pin Skew
HL Transitions
OSHL
(Note 1)
1.0
1.5
ns
ns
ns
ns
ns
t
Pin to Pin Skew
LH Transitions
OSLH
(Note 1)
1.0
1.4
1.5
2.0
1.5
3.5
3.9
4.0
t
Duty Cycle
PS
(Note 5)
LH–HL Skew
t
Pin to Pin Skew
OST
(Note 1)
LH/HL Transitions
t
Device to Device Skew
LH/HL Transitions
PV
(Note 2)
Note 1: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device. The
specification applies to any outputs switching HIGH to LOW (t ), LOW to HIGH (t ), or any combination switching LOW to HIGH and/or HIGH to LOW
OSHL OSLH
(t
OST
). This specification is guaranteed but not tested.
Note 2: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not tested.
CC
Note 3: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase (i.e., all LOW-to-HIGH,
HIGH-to-LOW, etc.).
Note 4: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load capacitors in
the standard AC load.
Note 5: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all the
outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
5
Capacitance
Conditions
Symbol
Parameter
Typ Units
e
(T
25 C)
§
A
e
C
C
Input Capacitance
5
9
pF
pF
V
CC
V
CC
0V
IN
e
(Note 1) Output Capacitance
5.0V
OUT
e
1 MHz, per MIL-STD-883B, Method 3012.
Note 1: C
is measured at frequency f
OUT
t
vs Temperature (T
)
t
vs Temperature (T )
PHL A
PLH
A
50 pF, 1 Output Switching
e
C
Data to Output
e
C
Data to Output
50 pF, 1 Output Switching
L
L
TL/F/11547–11
TL/F/11547–13
TL/F/11547–15
TL/F/11547–12
TL/F/11547–14
TL/F/11547–16
t
vs Temperature (T
)
t
vs Temperature (T )
PZL A
PZH
A
50 pF, 1 Output Switching
e
C
OE to Output
e
C
OE to Output
50 pF, 1 Output Switching
L
L
t
vs Temperature (T
A
50 pF, 1 Output Switching
)
t
vs Temperature (T )
PLZ A
PHZ
e
C
OE to Output
e
C
OE to Output
50 pF, 1 Output Switching
L
L
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
6
t
LOW vs Temperature (T
)
t
HIGH vs Temperature (T )
SET
A
50 pF, 1 Output Switching
SET A
e
C
Data to LE
e
C
L
Data to LE
50 pF, 1 Output Switching
L
TL/F/11547–17
TL/F/11547–19
TL/F/11547–21
TL/F/11547–23
TL/F/11547–18
TL/F/11547–20
TL/F/11547–22
TL/F/11547–24
t
HIGH vs Temperature (T
)
t
LOW vs Temperature (T )
HOLD A
e
50 pF, 1 Output Switching
HOLD
A
e
C
Data to LE
50 pF, 1 Output Switching
C
Data to LE
L
L
t
vs Temperature (T
)
t
vs Temperature (T )
PHL A
PLH
A
50 pF, 8 Outputs Switching
e
C
Data to Output
e
C
Data to Output
50 pF, 8 Outputs Switching
L
L
t
vs Temperature (T
)
t
vs Temperature (T )
PZH
A
50 pF, 8 Outputs Switching
PZL A
e
C
OE to Output
e
C
L
OE to Output
50 pF, 8 Outputs Switching
L
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
7
t
vs Temperature (T
)
t
vs Temperature (T )
PLZ A
PHZ
A
50 pF, 8 Outputs Switching
e
C
OE to Output
e
C
OE to Output
50 pF, 8 Outputs Switching
L
L
TL/F/11547–25
TL/F/11547–27
TL/F/11547–29
TL/F/11547–31
TL/F/11547–26
TL/F/11547–28
TL/F/11547–30
TL/F/11547–32
t
vs Load Capacitance
t
vs Load Capacitance
PHL
PLH
e
T
Data to Output
e
T
Data to Output
25 C, 1 Output Switching
§
25 C, 1 Output Switching
§
A
A
t
vs Load Capacitance
t
vs Load Capacitance
PHL
PLH
e
T
Data to Output
e
T
Data to Output
25 C, 8 Outputs Switching
§
25 C, 8 Outputs Switching
§
A
A
t
vs Load Capacitance
t
vs Load Capacitance
PZL
PZH
e
T
OE to Output
e
T
OE to Output
25 C, 8 Outputs Switching
§
25 C, 8 Outputs Switching
§
A
A
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
8
t
vs Temperature (T
)
t
vs Temperature (T )
PHL A
PLH
A
50 pF, 1 Output Switching
e
C
LE to Output
e
C
LE to Output
50 pF, 1 Output Switching
L
L
TL/F/11547–35
TL/F/11547–36
t
vs Temperature (T
)
t
vs Temperature (T )
PHL A
PLH
A
50 pF, 8 Outputs Switching
e
C
LE to Output
e
C
LE to Output
50 pF, 8 Outputs Switching
L
L
TL/F/11547–37
TL/F/11547–38
Typical I vs Output Switching Frequency
CC
e
e
e
e
C
L
0 pF, V
CC
V
IH
5.5V, LE GND,
t
and t
PHL
vs Number Outputs Switching
1 Output Switching at 50% Duty Cycle
Data to Output, Transparent Mode with
PLH
e
e
e
C
Outputs In Phase Data to Output
50 pF, T
25 C, V
5.0V,
§
L
A
CC
e
Unused Data Inputs
V
IH
TL/F/11547–33
Dashed lines represent design characteristics; for specified guarantees, refer to AC Characteristics Tables.
TL/F/11547–34
9
AC Loading
TL/F/11547–4
*Includes jig and probe capacitance
FIGURE 1. Standard AC Test Load
TL/F/11547–5
FIGURE 4. Propagation Delay,
Pulse Width Waveforms
TL/F/11547–6
TL/F/11547–7
FIGURE 2a. Test Input Signal Levels
FIGURE 5. TRI-STATE Output HIGH
and LOW Enable and Disable Times
Amplitude
Rep. Rate
t
w
t
t
f
r
3.0V
1 MHz
500 ns
2.5 ns
2.5 ns
FIGURE 2b. Test Input Signal Requirements
TL/F/11547–9
FIGURE 6. Setup Time, Hold Time
and Recovery Time Waveforms
TL/F/11547–8
FIGURE 3. Propagation Delay Waveforms for
Inverting and Non-Inverting Functions
10
Ordering Information
The device number is used to form part of a simplified purchasing code where the package type and temperature range are
defined as follows:
TL/F/11547–39
11
Physical Dimensions inches (millimeters)
20-Terminal Ceramic Chip Carrier (L)
NS Package Number E20A
12
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Dual-In-Line (D)
NS Package Number J20A
20-Lead Small Outline Integrated Circuit JEDEC (S)
NS Package Number M20B
13
Physical Dimensions inches (millimeters) (Continued)
20-Lead Small Outline Integrated Circuit EIAJ (SJ)
NS Package Number M20D
20-Lead Plastic EIAJ SSOP (MSA)
NS Package Number MSA20
14
Physical Dimensions inches (millimeters) (Continued)
All dimensions are in millimeters.
20-Lead Molded Thin Shrink Small Outline Package JEDEC (MTC)
NS Package Number MTC20
20-Lead Plastic Dual-In-Line Package (P)
NS Package Number N20B
15
Physical Dimensions inches (millimeters) (Continued)
20-Lead Ceramic Flatpak (F)
NS Package Number W20A
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相关型号：
74ABT373CMSAX
Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, 5.30 MM, MO-150, SSOP-20
FAIRCHILD
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