54LS161A [NSC]
Synchronous 4-Bit Binary Counters; 同步4位二进制计数器
| 型号： | 54LS161A |
| 厂家： | 
National Semiconductor |
| 描述： | Synchronous 4-Bit Binary Counters |
| 文件： | 总12页 (文件大小：213K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
May 1992
54LS161A/DM54LS161A/DM74LS161A,
54LS163A/DM54LS163A/DM74LS163A
Synchronous 4-Bit Binary Counters
General Description
These synchronous, presettable counters feature an inter-
nal carry look-ahead for application in high-speed counting
designs. The LS161A and LS163A are 4-bit binary counters.
The carry output is decoded by means of a NOR gate, thus
preventing spikes during the normal counting mode of oper-
ation. Synchronous operation is provided by having all flip-
flops clocked simultaneously so that the outputs change co-
incident with each other when so instructed by the count-
enable inputs and internal gating. This mode of operation
eliminates the output counting spikes which are normally
associated with asynchronous (ripple clock) counters. A
buffered clock input triggers the four flip-flops on the rising
(positive-going) edge of the clock input waveform.
gating. Instrumental in accomplishing this function are two
count-enable inputs and a ripple carry output.
Both count-enable inputs (P and T) must be high to count,
and input T is fed forward to enable the ripple carry output.
The ripple carry output thus enabled will produce a high-lev-
el output pulse with a duration approximately equal to the
high-level portion of the Q output. This high-level overflow
A
ripple carry pulse can be used to enable successive cascad-
ed stages. High-to-low level transitions at the enable P or T
inputs may occur, regardless of the logic level of the clock.
These counters feature a fully independent clock circuit.
Changes made to control inputs (enable P or T or load) that
will modify the operating mode have no effect until clocking
occurs. The function of the counter (whether enabled, dis-
abled, loading, or counting) will be dictated solely by the
conditions meeting the stable set-up and hold times.
These counters are fully programmable; that is, the outputs
may be preset to either level. As presetting is synchronous,
setting up a low level at the load input disables the counter
and causes the outputs to agree with the setup data after
the next clock pulse, regardless of the levels of the enable
input. The clear function for the LS161A is asynchronous;
and a low level at the clear input sets all four of the flip-flop
outputs low, regardless of the levels of clock, load, or en-
able inputs. The clear function for the LS163A is synchro-
nous; and a low level at the clear inputs sets all four of the
flip-flop outputs low after the next clock pulse, regardless of
the levels of the enable inputs. This synchronous clear al-
lows the count length to be modified easily, as decoding the
maximum count desired can be accomplished with one ex-
ternal NAND gate. The gate output is connected to the clear
input to synchronously clear the counter to all low outputs.
Features
Y
Synchronously programmable
Y
Internal look-ahead for fast counting
Y
Carry output for n-bit cascading
Y
Synchronous counting
Y
Load control line
Y
Diode-clamped inputs
Y
Typical propagation time, clock to Q output 14 ns
Y
Typical clock frequency 32 MHz
Y
Typical power dissipation 93 mW
Y
Alternate
Military/Aerospace
device
(54LS161,
The carry look-ahead circuitry provides for cascading coun-
ters for n-bit synchronous applications without additional
54LS163) is available. Contact a National Semiconduc-
tor Sales Office/Distributor for specificaitons.
Connection Diagram
Dual-In-Line Package
Order Numbers 54LS161ADMQB, 54LS161AFMQB,
54LS161ALMQB, 54LS163ADMQB, 54LS163AFMQB,
54LS163ALMQB, DM54LS161AJ, DM54LS161AW,
DM54LS163AJ, DM54LS163AW, DM74LS161AM,
DM74LS161AN, DM74LS163AM or DM74LS163AN
See NS Package Number E20A, J16A,
M16A, N16E or W16A
TL/F/6397–1
C
1995 National Semiconductor Corporation
TL/F/6397
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
DM54LS and 54LS
DM74LS
b
b
a
a
55 C to 125 C
§
§
0 C to 70 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
DM54LS161A
DM74LS161A
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
MHz
MHz
OH
OL
4
8
f
0
25
20
0
25
20
CLK
0
0
t
Pulse Width
(Note 1)
Clock
Clear
20
20
25
25
20
25
25
20
30
30
0
6
9
20
20
25
25
20
25
25
20
30
30
0
6
9
W
ns
ns
Pulse Width
(Note 2)
Clock
Clear
t
Setup Time
(Note 1)
Data
8
8
SU
Enable P
Load
17
15
17
15
ns
ns
Setup Time
(Note 2)
Data
Enable P
Load
b
b
b
b
t
t
Hold Time
(Note 1)
Data
3
3
3
3
H
ns
ns
Others
Data
0
0
Hold Time
(Note 2)
5
5
Others
5
5
Clear Release Time (Note 1)
Clear Release Time (Note 2)
Free Air Operating Temperature
20
25
20
25
0
ns
ns
REL
b
T
55
125
70
C
§
A
e
e
e
e
e
e
e
e
Note 1: C
15 pF, R
50 pF, R
2 kX, T
2 kX, T
25 C and V
§
25 C and V
§
5.5V.
5.5V.
L
L
L
L
A
A
CC
CC
Note 2: C
2
’LS161 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
DM54
DM74
DM54
DM74
DM74
Enable T
Clock
2.5
2.7
3.4
3.4
OH
CC
OH
e
e
Max, V
IL
IH
e
e
e
V
OL
Low Level Output
Voltage
V
V
Min, I
Max
Min
0.25
0.35
0.25
0.4
CC
OL
e
Max, V
IH
IL
0.5
0.4
0.2
0.2
0.2
0.1
40
V
e
e
Min
I
4 mA, V
CC
OL
@
Input Current Max
e
CC
I
I
I
I
V
Max
I
e
Input Voltage
V
I
7V
mA
Load
Others
Enable T
Clock
e
High Level Input
Current
V
V
Max
Max
Max
IH
CC
e
2.7V
I
40
mA
Load
40
Others
Enable T
Clock
20
e
b
Low Level Input
Current
V
V
0.8
0.8
0.8
0.4
100
100
IL
CC
e
0.4V
I
b
b
b
mA
mA
Load
Others
DM54
DM74
e
b
b
b
b
Short Circuit
V
CC
20
20
OS
Output Current
(Note 2)
e
CC
I
I
Supply Current with
Outputs High
V
Max
18
19
31
CCH
CCL
mA
mA
(Note 3)
e
(Note 4)
Supply Current with
Outputs Low
V
CC
Max
32
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
Note 3: I
Note 4: I
is measured with the load high, then again with the load low, with all other inputs high and all outputs open.
CCH
is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
CCL
’LS161 Switching Characteristics
5V and T
e
e
A
at V
25 C (See Section 1 for Test Waveforms and Output Load)
§
CC
e
R
2 kX
L
From (Input)
e
e
50 pF
Symbol
Parameter
C
L
15 pF
C
L
Units
To (Output)
Min
Max
Min
Max
f
t
Maximum Clock Frequency
25
20
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock to
PLH
25
30
22
27
30
38
27
38
Ripple Carry
t
t
t
Propagation Delay Time
High to Low Level Output
Clock to
PHL
PLH
PHL
ns
ns
ns
Ripple Carry
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load High)
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load High)
3
’LS161 Switching Characteristics
5V and T
e
e
at V
25 C (See Section 1 for Test Waveforms and Output Load) (Continued)
§
CC
A
e
R
L
2 kX
From (Input)
To (Output)
e
e
L
Symbol
Parameter
C
L
15 pF
C
50 pF
Max
Units
Min
Max
Min
t
t
t
t
t
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load Low)
PLH
PHL
PLH
PHL
PHL
24
30
38
27
27
45
ns
ns
ns
ns
ns
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load Low)
27
14
15
28
Propagation Delay Time
Low to High Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Clear to
Any Q
Recommended Operating Conditions
DM54LS163A
DM74LS163A
Symbol
Parameter
Units
Min
4.5
2
Nom
Max
Min
4.75
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
5
5.25
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Clock Frequency (Note 1)
Clock Frequency (Note 2)
IH
0.7
0.8
V
IL
b
b
0.4
I
I
0.4
mA
mA
MHz
MHz
OH
OL
4
8
f
0
25
20
0
25
20
CLK
0
0
t
Pulse Width
(Note 1)
Clock
Clear
20
20
25
25
20
25
25
20
30
30
0
6
9
20
20
25
25
20
25
25
20
30
30
0
6
9
W
ns
ns
Pulse Width
(Note 2)
Clock
Clear
t
Setup Time
(Note 1)
Data
8
8
SU
Enable P
Load
17
15
17
15
ns
ns
Setup Time
(Note 2)
Data
Enable P
Load
b
b
b
b
t
t
Hold Time
(Note 1)
Data
3
3
3
3
H
ns
ns
Others
Data
0
0
Hold Time
(Note 2)
5
5
Others
5
5
Clear Release Time (Note 1)
Clear Release Time (Note 2)
Free Air Operating Temperature
20
25
20
25
0
ns
ns
REL
b
T
55
125
70
C
§
A
e
e
e
e
e
e
e
e
Note 1: C
15 pF, R
50 pF, R
2 kX, T
2 kX, T
25 C and V
§
25 C and V
§
5V.
5V.
L
L
L
L
A
A
CC
CC
Note 2: C
4
’LS163 Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
V
V
I
CC
I
High Level Output
Voltage
V
V
Max
Min
DM54
2.5
2.7
3.4
3.4
OH
CC
OH
e
e
Max, V
IL
IH
DM74
e
e
e
V
Low Level Output
Voltage
V
V
Min, I
Max
Min
DM54
0.25
0.35
0.25
0.4
OL
CC
OL
e
Max, V
IH
IL
DM74
0.5
0.4
0.2
0.2
0.2
0.1
40
V
e
e
Min
I
4 mA, V
CC
DM74
OL
@
Input Current Max
e
CC
I
I
I
I
V
Max
Enable T
Clock, Clear
Load
I
e
Input Voltage
V
I
7V
mA
Others
Enable T
Load
e
High Level Input
Current
V
V
Max
Max
Max
IH
CC
e
2.7V
I
40
mA
Clock, Clear
Others
Enable T
Clock, Clear
Load
40
20
e
b
Low Level Input
Current
V
V
0.8
0.8
0.8
0.4
100
100
IL
CC
e
0.4V
I
b
b
b
mA
mA
Others
DM54
e
b
b
b
b
Short Circuit
V
CC
20
20
OS
Output Current
(Note 2)
DM74
e
CC
I
I
Supply Current with
Outputs High
V
Max
18
18
31
CCH
CCL
mA
mA
(Note 3)
e
(Note 4)
Supply Current with
Outputs Low
V
CC
Max
32
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
Note 3: I
Note 4: I
is measured with the load high, then again with the load low, with all other inputs high and all outputs open.
CCH
is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open.
CCL
’LS163 Switching Characteristics
e
e
at V
5V and T
25 C (See Section 1 for Test Waveforms and Output Load)
§
CC
A
e
R
2 kX
L
From (Input)
e
e
L
Symbol
Parameter
C
15 pF
C
50 pF
Max
Units
To (Output)
L
Min
Max
Min
f
t
Maximum Clock Frequency
25
20
MHz
ns
MAX
Propagation Delay Time
Low to High Level Output
Clock to
PLH
25
30
22
27
30
38
27
38
Ripple Carry
t
t
t
Propagation Delay Time
High to Low Level Output
Clock to
PHL
PLH
PHL
ns
ns
ns
Ripple Carry
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load High)
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load High)
5
’LS163 Switching Characteristics
5V and T
e
e
at V
25 C (See Section 1 for Test Waveforms and Output Load) (Continued)
§
CC
A
e
R
L
2 kX
From (Input)
To (Output)
e
e
L
Symbol
Parameter
C
L
15 pF
C
50 pF
Max
Units
Min
Max
Min
t
t
t
t
t
Propagation Delay Time
Low to High Level Output
Clock to Any Q
(Load Low)
PLH
PHL
PLH
PHL
PHL
24
30
38
27
27
45
ns
ns
ns
ns
ns
Propagation Delay Time
High to Low Level Output
Clock to Any Q
(Load Low)
27
14
15
28
Propagation Delay Time
Low to High Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Enable T to
Ripple Carry
Propagation Delay Time
High to Low Level Output
Clear to Any Q
(Note 1)
Note 1: The propagation delay clear to output is measured from the clock input transition.
Logic Diagram
LS163A
TL/F/6397–2
The LS161A is similar, however, the clear buffer is connected directly to the flip flops.
6
Parameter Measurement Information
Switching Time Waveforms
TL/F/6397–3
s
s
s
s
10 ns, t 10 ns.
f
&
Note A: The input pulses are supplied by generators having the following characteristics: PRR
Vary PRR to measure f
1 MHz, duty cycle
50%, Z
50X, t
OUT
r
.
MAX
Note B: Outputs Q and carry are tested at t
D
where t is the bit time when all outputs are low.
a
16 n
n
e
Note C: V
REF
1.5V.
Switching Time Waveforms
TL/F/6397–4
s
Note A: The input pulses are supplied by generators having the following characteristics: PRR 1 MHz, duty cycle 50%, Z
s
s
s
&
50X, t
6 ns, t
f
6 ns. Vary
OUT
r
PRR to measure f
MAX
.
Note B: Enable P and enable T setup times are measured at t
.
0
a
n
e
Note C: V
REF
1.3V.
7
Timing Diagram
LS161A, LS163A Synchronous Binary Counters
Typical Clear, Preset, Count and Inhibit Sequences
TL/F/6397–5
Sequence:
(1) Clear outputs to zero
(2) Preset to binary twelve
(3) Count to thirteen, fourteen, fifteen, zero, one, and two
(4) Inhibit
8
9
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier Package (E)
Order Numbers 54LS161ALMQB or 54LS163ALMQB
NS Package Number E20A
16-Lead Ceramic Dual-In-Line Package (J)
Order Numbers 54LS161ADMQB, 54LS163ADMQB, DM54LS161AJ or DM54LS163AJ
NS Package Number J16A
10
Physical Dimensions inches (millimeters) (Continued)
16-Lead Small Outline Molded Package (M)
Order Number DM74LS161AM or DM74LS163AM
NS Package Number M16A
16-Lead Molded Dual-In-Line Package (N)
Order Numbers DM74LS161AN, DM74LS163AN
NS Package Number N16E
11
Physical Dimensions inches (millimeters) (Continued)
16-Lead Ceramic Flat Package (W)
Order Numbers 54LS161AFMQB, 54LS163AFMQB,
DM54LS161AN or DM54LS163AW
NS Package Number W16A
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DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL
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1. Life support devices or systems are devices or
systems which, (a) are intended for surgical implant
into the body, or (b) support or sustain life, and whose
failure to perform, when properly used in accordance
with instructions for use provided in the labeling, can
be reasonably expected to result in a significant injury
to the user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
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