54LS114 [NSC]
Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears; 双JK负边沿触发触发器与普通时钟并清除
| 型号： | 54LS114 |
| 厂家： | 
National Semiconductor |
| 描述： | Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears |
| 文件： | 总6页 (文件大小：112K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
June 1989
54LS114
Dual JK Negative Edge-Triggered
Flip-Flop with Common Clocks and Clears
General Description
The ’LS114 features individual J, K and set inputs and com-
mon clock and common clear inputs. When the clock goes
HIGH the inputs are enabled and data will be accepted. The
logic level of the J and K inputs may be allowed to change
when the Clock Pulse is HIGH and the bistable will perform
according to the truth table as long as the minimum setup
times are observed. Input data is transferred to the outputs
on the negative-going edge of the clock pulse.
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL/F/10176–1
Order Number 54LS114DMQB,
54LS114FMQB or 54LS114LMQB
TL/F/10176–2
e
V
Pin 14
Pin 7
CC
e
GND
See NS Package Number E20A, J14A or W14B
Pin Names
Description
J1, J2, K1, K2
CP
Data Inputs
Clock Pulse Input (Active Falling Edge)
Direct Clear Input (Active LOW)
Direct Set Inputs (Active LOW)
CD
SD1, SD2
Q1, Q2, Q1, Q2 Outputs
C
1995 National Semiconductor Corporation
TL/F/10176
RRD-B30M105/Printed in U. S. A.
Absolute Maximum Ratings (Note)
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales
Office/Distributors for availability and specifications.
Note: The ‘‘Absolute Maximum Ratings’’ are those values
beyond which the safety of the device cannot be guaran-
teed. The device should not be operated at these limits. The
parametric values defined in the ‘‘Electrical Characteristics’’
table are not guaranteed at the absolute maximum ratings.
The ‘‘Recommended Operating Conditions’’ table will define
the conditions for actual device operation.
Supply Voltage
Input Voltage
7V
7V
Operating Free Air Temperature Range
54LS
b
b
a
55 C to 125 C
§
§
a
65 C to 150 C
Storage Temperature Range
§
§
Recommended Operating Conditions
54LS114
Units
Symbol
Parameter
Min
4.5
2
Nom
Max
V
V
V
Supply Voltage
5
5.5
V
V
CC
High Level Input Voltage
Low Level Input Voltage
High Level Output Current
Low Level Output Current
Free Air Operating Temperature
IH
0.7
V
IL
b
I
I
0.4
mA
mA
OH
OL
4
b
T
A
55
125
C
§
t
t
(H)
Setup Time
20
s
ns
ns
(L)
Jn or Kn to CP
20
s
t
t
(H)
(L)
Hold Time
0
0
h
Jn or Kn to CP
h
t
t
(H)
(L)
CP Pulse Width
20
15
w
ns
ns
w
t
w
CD or SDn Pulse Width
15
Electrical Characteristics Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
e b
e
b
1.5
V
V
Input Clamp Voltage
V
Min, I
Min, I
18 mA
Max,
V
V
I
CC
I
High Level Output Voltage
V
V
OH
CC
OH
2.5
e
Max
IL
e
e
Max,
V
OL
Low Level Output Voltage
V
V
Min, I
0.4
CC
OL
V
e
Min
IH
0.5
@
Input Current Max
e
e
10V; Jn, Kn Inputs
I
I
V
Max, V
I
0.1
0.3
0.6
0.8
mA
mA
mA
mA
I
CC
Input Voltage
SD1, SD2 Inputs
CD Input
CP Input
e
e
2.7V; Jn, Kn Inputs
High Level Input Current
V
Max, V
I
20
60
mA
mA
mA
mA
IH
CC
SD1, SD2 Inputs
CD Input
120
160
CP Input
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
CC
A
2
Electrical Characteristics (Continued)
Over recommended operating free air temperature range (unless otherwise noted)
Typ
Symbol
Parameter
Conditions
Min
Max
Units
(Note 1)
e
e
Max, V
I
b
b
b
I
Low Level Input Current
V
0.4V Jn, Kn Inputs
0.4
0.8
1.6
mA
mA
mA
mA
IL
CC
SD1, SD2 Inputs
CD Input
b
CP Input
1.44
e
CC
I
I
Short Circuit
V
Max
OS
CC
b
b
20
100
8.0
mA
mA
Output Current
(Note 2)
e
e
0V
Supply Current
V
CC
Max, V
CP
e
e
25 C.
Note 1: All typicals are at V
5V, T
§
Note 2: Not more than one output should be shorted at a time, and the duration should not exceed one second.
CC
A
Switching Characteristics
5.0V, T
e a
e a
25 C (See Section 1 for Test Waveforms and Output Load)
V
CC
§
A
e
e
15 pF
R
L
2k, C
L
Symbol
Parameter
Units
Min
Max
f
Maximum Count Frequency
30
MHz
ns
max
t
t
Propagation Delay
CP to Q or Q
16
24
PLH
PHL
t
t
Propagation Delay
16
24
PLH
ns
CD or SDn to Q or Q
PHL
Truth Table
Inputs
Output
@
@
t
n
t
a
1
n
J
L
K
L
Q
Qn
L
L
H
L
H
H
H
H
Qn
Asynchronous Inputs:
LOW input to SD sets Q to HIGH level
LOW input to CD sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD
makes both Q and Q HIGH
e
e
e
H
L
HIGH Voltage Level
LOW Voltage Level
t
t
Bit time before clock pulse.
n
e
Bit time after clock pulse.
a
n
1
3
Logic Diagram (one half shown)
TL/F/10176–3
Physical Dimensions inches (millimeters)
Ceramic Leadless Chip Carrier (E)
Order Number 54LS114LMQB
NS Package Number E20A
4
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Dual-In-Line Package (J)
Order Number 54LS114DMQB
NS Package Number J14A
5
Physical Dimensions inches (millimeters) (Continued)
14-Lead Ceramic Flat Package (W)
Order Number 54LS114FMQB
NS Package Number W14B
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